CN109216317A - 具混合金属化的互连 - Google Patents

具混合金属化的互连 Download PDF

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CN109216317A
CN109216317A CN201810671210.1A CN201810671210A CN109216317A CN 109216317 A CN109216317 A CN 109216317A CN 201810671210 A CN201810671210 A CN 201810671210A CN 109216317 A CN109216317 A CN 109216317A
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conductor layer
dual damascene
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damascene opening
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CN109216317B (zh
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R·J·福克斯三世
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GlobalFoundries US Inc
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Abstract

本发明涉及具混合金属化的互连，揭露一种互连结构以及形成互连的方法。一双镶嵌开口形成于介电层中，以及第一衬垫形成于该双镶嵌开口的一个或多个侧壁处的该介电层上。第一导体层形成于该双镶嵌开口的一部分中。该第一衬垫从垂直位于该第一导体层以及该介电层的顶表面之间的该双镶嵌开口的该一个或多个侧壁上被移除。在移除该第一衬垫后，第二衬垫形成在该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口的该一个或多个侧壁处的该介电层上。第二导体层形成于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口中。该第一以及第二衬垫材料的组成不同。

Description

具混合金属化的互连
技术领域
本发明涉及集成电路以及半导体设备制造，更具体而言，涉及互连结构及形成互连的方法。
背景技术
互连结构可用于电性连接通过前段工艺(FEOL)处理所制造于衬底上的设备结构。该互连结构的后段工艺(BEOL)部分包括使用双镶嵌工艺形成的金属化，其中，在介电层中蚀刻的通孔开口及沟槽同时填充金属以形成一金属化层。该BEOL互连结构的最低金属层可以通过特征(例如接触件)耦接使用通过中段工艺(MOL)处理形成的金属化在BEOL工艺之前形成的设备结构。
互连件的结构以及形成互连结构的方法是需要改善的。
发明内容
根据本发明的一实施例中，一种形成互连结构的方法包括形成一双镶嵌开口于介电层中，形成有第一材料组成的第一衬垫于该双镶嵌开口的一个或多个侧壁处的该介电层上，以及形成第一导体层于该双镶嵌开口的一部分中。该方法还包括从垂直位于该第一导体层以及该介电层的顶表面之间的该双镶嵌开口的该一个或多个侧壁上移除该第一衬垫，以及在移除该第一衬垫后，形成由第二材料组成的第二衬垫于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口的该一个或多个侧壁处的该介电层上。第二导体层形成于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口中。该第二衬垫的该第二材料与该第一衬垫的该第一材料的组成不同。
根据本发明的一实施例，互连结构包括具有顶表面的介电层以及具有一个或多个侧壁的双镶嵌开口。该互连结构还包括位于该双镶嵌开口的一部分中的第一导体层，设置于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口中的第二导体层，设置于该第一导体层以及该双镶嵌开口的该一个或多个侧壁处的该介电层之间的第一衬垫，以及设置于该第二导体层以及该双镶嵌开口的该一个或多个侧壁处的该介电层之间的第二衬垫。该第二衬垫由与该第一衬垫的第一材料的组成不同的第二材料组成。
附图说明
纳入并构成本说明书的一部分的附图用于说明本发明的各种实施例，连同上面所给出的本发明的一般描述以及下面给出的各实施例的详细描述，用于解释本发明的各实施例。
图1至图5为根据本发明的各实施例所示的处理方法的各连续制造阶段的横截面图。
具体实施方式
参考图1，根据本发明的一实施例，介电层10可以通过后段工艺(BEOL)处理来进行处理以形成一互连结构的金属化层。介电层10可以由电绝缘体组成，例如二氧化硅(SiO2)或其他适合的介电材料。介电层10可以通过光刻以及蚀刻被图案化以形成包括通孔开口12,14以及与通孔开口12,14重叠的沟槽16的双镶嵌开口25。为此，可以铺设一光刻胶层，暴露于通过一光掩模投射的的辐射图案，并显影以形成对应于通孔开口12,14的预定位置处的开口的图案。该图案化的光刻胶层用于作为干蚀刻工艺的蚀刻掩膜，例如，反应离子蚀刻(RIE)，其去除介电层10的部分以形成通孔开口12,14。可以铺设另一光刻胶层，暴露于通过一光掩膜投射的辐射图案，并显影以形成位于沟槽16的预定位置处的开口。该图案化的光刻胶层用于作为干蚀刻工艺的蚀刻掩膜，例如反应离子蚀刻(RIE)，其移除介电层10的部分以形成沟槽16。各蚀刻工艺可在单个蚀刻步骤或在具有不同蚀刻化学剂的多个蚀刻步骤中进行。作为双镶嵌开口25的组件，通孔开口12,14可以在形成沟槽16之前形成，或者，视需要地，沟槽16可以在形成通孔开口12,14之前形成。由一层或多层构成的硬掩膜24位于介电层10的顶表面11上，并用于在形成沟槽16时作为蚀刻掩膜。
介电层10位于一底层金属化层上，该底层金属化层包括一介电层18、布置在介电层10中的导电特征20以及一覆盖层22。通孔开口12具有延伸至其中一个导电特征20的一个或多个侧壁13。通孔开口14具有延伸至另一个导电特征20的一个或多个侧壁15。沟槽16具有从介电层10的顶表面11延伸，以与通孔开口12,14的侧壁13,15合并的一个或多个侧壁17。通孔开口12,14和沟槽16可穿过厚度小于介电层10的介电层10，或完全穿过介电层10以及覆盖层22的厚度。
给定厚度的衬垫层26共形地沉积在通孔开口12,14和沟槽16的相应侧壁13,15,17上，以及在通孔开口12,14的底部的导电特征20上，其共同构成双镶嵌开口25的底部。衬垫层26同样沉积在硬掩膜24上的介电层10的顶表面11的场域(field area)中。衬垫层26可以由具有材料特性的材料组成，使得其能够增强导体(例如铜Cu)的回流。于一实施例中，衬垫层26可以由钌(Ru)组成，或包括Ru以及一种或多种附加材料(例如氮化钽(Ta)和/或钽(Ta))的一层叠组合而构成，其中，Ru作为该层叠组合中的最顶层。衬垫层26可通过化学气相沉积(CVD)，原子层沉积(ALD)，通过物理气相沉积(PVD)，例如，溅射辅助工艺，或通过这些方法的组合进行沉积。
晶种层28沉积在覆盖通孔开口12,14的各相应侧壁13,15以及沟槽16的侧壁17的衬垫层26上，以及沉积在通孔开口12,14的底部19的导电特征20上。晶种层28同样沉积在覆盖在介电层10的顶表面11的衬垫层26上的场域中。晶种层28可以由具有高导电性的导体组成，例如铜(Cu)，其通过化学气相沉积(CVD)或PVD沉积。
参考图2，其中，相同的附图标记指的是图1中的类似特征，以及在处理方法的后续制造阶段，可以施加一热工艺以使晶种层28中的导体沉积在相应的侧壁13,15,17上以及介电层10的顶表面11的场域中而回流。晶种层28的导体被传送到通孔开口12,14的底部19(图1)，其增加了通孔开口12,14内部的晶种层28的厚度。该热工艺可以包括在一高温(例如大于250℃的温度，或介于250℃至400℃的范围内的温度)下退火或加热晶种层28。热工艺可以在沉积之后和/或在沉积过程中进行。该热工艺加速了晶种层28的材料的导体表面扩散，并增加了从通孔开口12,14的底部19向上的填充深度(即，厚度)。回流的特征是部分的，因为尽管导体从该场域中被热传导到沟槽16中，但是在热退火之后，晶种层28的剩余厚度仍保留在场域中以及侧壁13,15,17上。由于衬垫层26或构成衬垫层26的多层的最顶层是由可促进回流的材料，例如钌(Ru)，所组成，所以可增加回流。
导体沉积以及部分回流循环可以重复以增加从它们的各自底部19向上的通孔开口12,14内部的晶种层28的厚度，以达到一目标厚度。具体而言，一次或多次额外重复地沉积一晶种层28并将晶种层28的导体导流到通孔开口12,14的各自底部19。由于重复沉积导体以及部分回流工艺，所以在通孔开口12,14内部的导体的厚度随着在每一个循环中从各自底部19向着沟槽16上升而逐渐增加。
在最终沉积/部分回流循环之后，晶种层28的顶表面之上的沟槽16内的开口空间的至少一部分未被填充。在代表性实施例中，晶种层28的厚度略大于通孔开口12,14的深度，以使晶种层28的一区段覆盖位于通孔开口12,14之间的介电层10的区段。或者，晶种层28的厚度可等于或略小于通孔开口12,14的深度。不管其厚度如何，晶种层28主要填充通孔开口12,14。来自该回流的晶种层28的导体的残留层30可位于覆盖沟槽16的侧壁17的衬垫层26上，并且也可存在于介电层10的顶表面11上的场域上。由于不同工具集之间的真空破裂，所以残留层30的材料可以被氧化。
参考图3，其中，相同的附图标记指的是图2中的类似特征，在工艺方法的一后续制造阶段，残留层30以及衬垫层26从晶种层28的水平之上的沟槽16的侧壁17被移除而暴露出位于沟槽16的侧壁17处的介电层10的介电材料。衬垫层26以及残留层30同样从场域被移除。于一实施例中，可以使用一个或多个溅射化学反应工艺从沟槽16的侧壁17移除残留层30和衬垫层26。残留在通孔开口12,14中的晶种层28可以在残留层30被移除时略微变薄。
通孔开口12,14内的晶种层28的导体通过衬垫层26而与介电层的介电材料分离。在代表性实施例中，晶种层28以及底层衬垫层26从布置在通孔开口12与通孔开口14之间的介电层10的区段被移除，通孔开口12,14内的晶种层28具有与沟槽16共同延伸的顶表面。在替代实施例中，晶种层28的顶表面可以被凹陷至通孔开口12,14中，或者可在通孔开口12,14之上凸出到沟槽16中。在前一实施例中，晶种层28的高度之上的各通孔开口12,14的一部分未被填充。在后一实施例中，晶种层28以及衬垫层26的区段可覆盖布置于通孔开口12以及通孔开口14之间的介电层10的区段。在任何布置中，通孔开口12,14主要由来自晶种层28的导体填充。
参考图4，其中相同的附图标记指的是图3中的类似特征，在工艺方法的后续制造阶段中，具有相应给定厚度的阻障层32和衬垫层34共形地沉积在沟槽16的相应侧壁17上以及晶种层28上。阻障层32和衬垫层34同样沉积在硬掩膜24上的介电层10的顶表面11上的场域中。最顶层的衬垫层34可以由一导体组成，例如钴(Co)。阻障层32可以由一层或多层导体组成，例如：钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、导电材料的一层叠堆叠(例如，Ta和TaN组成的一双层)，或这些导体的组合。阻障层32以及衬垫层34不含钌(Ru)。阻障层32以及衬垫层34可以通过物理气相沉积(PVD)，例如溅射辅助工艺进行沉积。
一晶种层(未示出)以及导体层36沉积在衬垫层34上。晶种层以及导体层36通常沉积在衬垫层34上的介电层10的顶表面11上的场域中。晶种层可以由具有高导电性的导体组成，例如铜(Cu)，通过CVD或PVD沉积。导体层36可使用不同于用于形成晶种层28的沉积(及回流)工艺的沉积工艺沉积，例如无电沉积(electroless deposition)。衬垫层34以及阻障层32的各个区段以层叠堆叠布置于导体层36和晶种层28之间。
参考图5，其中相同的附图标记指的是图4中的类似特征，在后续制造阶段，导体层36、其晶种层、衬垫层34和阻障层32通过平坦化从介电层10的顶表面11上的场域被移除，例如通过一个或多个化学机械抛光(CMP)工艺。硬掩膜24通过CMP工艺被移除，介电层10和导体层36通过CMP工艺被平坦化。在每个CMP工艺期间的材料移除结合磨蚀以及抛光目标材料的蚀刻效果，并且可以使用选择的抛光垫以及浆料通过商业工具对目标材料进行抛光。由于阻障层32和衬垫层34不含钌，所以无需用于移除钌的CMP工艺，其可避免诸如撕裂(ripout)、划痕和空隙的抛光伪影(polishing artifact)，以及在CMP工艺过程中，由于过度地与钌有关的凹陷和侵蚀，而导致整体平面性的丧失。
混合导电特征38包括(作为贡献组件(contributing
component))：每一个皆包含来自晶种层28的导体的位于通孔开口12内的导电特征40以及位于通孔开口14内的导电特征42，以及包含来自导体层36的导体的沟槽16内的导电特征44。根据相对于通孔开口12,14的高度的晶种层28的厚度，各导电特征40,42,44可以包括来自晶种层28的贡献体(contribution)以及来自导体层36的贡献体。混合导电特征38可以具有无缝无空隙的结构。导电特征40,42,44在平坦化之后被嵌入介电层10中，导电特征40,42在导电特征44以及导电特征20之间建立垂直互连件。
覆盖层46可形成在导电特征44上。于一实施例中，覆盖层46可以由例如使用一沉积工艺沉积的钴(CO)组成，该沉积工艺例如为化学气相沉积(CVD)或无电沉积，其选择性地仅在导电特征44上沉积钴，而不在介电层10的顶表面11上沉积钴。
导电特征40,42,44具有由促进低电阻、高可靠性互连的衬垫层26,34所组成的混合金属衬垫结构。通过衬垫层26的材料促进的晶种层28的回流的导体会填充通孔开口12,14，减少了随后形成主要用于填充沟槽16的导体层36的高度与宽度的纵横比。在这方面，沟槽16的填充被有效的转化为单一镶嵌金属化工艺，并结合低成本的双镶嵌图案化来形成通孔开口12,14以及沟槽16，且降低形成空隙在导体层36中的风险。衬垫层34中钌的缺乏可以通过消除与一钌衬垫相关的问题(例如刮痕、撕裂、空隙、以及过度凹陷和侵蚀)从而改善下游工艺。另一方面，衬垫层34中存在不同材料(如钴)以取代钌可以促进下游工艺。衬垫层34也与同样包括钴以提高可靠性的覆盖层46的形成兼容。具有钴和钌的复合金属衬垫的混合导电特征38可以表现出增强的金属电阻电容性能，并降低了导电特征40,42在通孔开口12,14中的电阻。
上述方法用于集成电路芯片的制作。所得到的集成电路芯片可以由制造商以原始晶片形式(例如，作为具有多个未封装芯片的一单晶片)，作为一裸片，或在一封装形式中予以分布。该芯片可以与其他芯片、独立电路元件，和/或信号处理设备集成以作为一中间产品或一最终产品的一部分。该最终产品可以是任何包括集成电路芯片的产品，例如具有一中央处理器的计算机或智能手机。
本文引用的术语如“垂直”、“水平”、等均是通过举例的方式而不是通过限制的方式来建立参考框架的。本文所使用的术语“水平”被定义为平行于一半导体衬底的一传统平面的一平面，而不管其实际的三维空间取向。术语“垂直”和“正常”是指垂直于水平的一方向，正如之前所定义的。术语“横向”指的是水平平面内的一方向，诸如“上方”以及“下方”等术语用于表示元件或结构相对于彼此的相对标高的位置。
一特征“连接”或“耦接”到另一元件可以是直接连接或耦接至其他元件，或者，可以存在一个或多个中间元件。如果缺少中间元件，一特征可以“直接连接”或“直接耦接”至另一元件。如果存在至少一个中间元件，一特征可以“间接连接”或“间接耦接”至其他元件。
本发明的各种实施例的描述是为了说明的目的而提出，并不打算穷尽或局限于所公开的实施例。在不脱离所描述的各种实施例的范围和精神的情况下，许多修改和变化对本领域的普通技术人员来说是显而易见的。本文所使用的术语被选择来最好地解释实施例的原理、实际应用或相较于市场上的现有技术的技术改进，或者使本领域的技术人员能够理解本文所揭露的实施例。

Claims (20)

1.一种形成互连结构的方法，该方法包括：
形成双镶嵌开口于介电层中；
形成由第一材料组成的第一衬垫于位于该双镶嵌开口的一个或多个侧壁处的该介电层上；
形成第一导体层于该双镶嵌开口的一部分中；
从垂直位于该第一导体层与该介电层的顶表面之间的该双镶嵌开口的该一个或多个侧壁上移除该第一衬垫；
在移除该第一衬垫后，形成由第二材料组成的第二衬垫于位于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口的该一个或多个侧壁处的该介电层上；以及
形成第二导体层于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口中，
其中，该第二衬垫的该第二材料与该第一衬垫的该第一材料的组成不同。
2.根据权利要求1所述的方法，其中，该双镶嵌开口包括通孔开口以及设置于该介电层的该顶表面以及该通孔开口之间的沟槽，且该第一导体层完全填充该通孔开口。
3.根据权利要求1所述的方法，其中，该双镶嵌开口包括通孔开口以及设置于该介电层的该顶表面以及该通孔开口之间的沟槽，且该第一导体层部分填充该沟槽。
4.根据权利要求1所述的方法，其中，形成该第一导体层于该双镶嵌开口的该部分中包括：
沉积该第一导体层于该双镶嵌开口的底部、该双镶嵌开口的一个或多个侧壁上以及该介电层的该顶表面上；以及
将该介电层的该顶表面上以及该一个或多个侧壁上的该第一导体层向该双镶嵌开口的该底部回流，以增加相对于该双镶嵌开口的该底部的该第一导体层的厚度。
5.根据权利要求4所述的方法，还包括：
通过共形沉积工艺沉积该第一导体层以作为晶种层，
其中，该第一导体层在沉积期间通过热工艺在高温下被回流。
6.根据权利要求4所述的方法，还包括：
通过共形沉积工艺沉积该第一导体层以作为晶种层，
其中，该第一导体层在沉积后通過热工艺在高温下被回流。
7.根据权利要求1所述的方法，其中，该第一衬垫由钌组成。
8.根据权利要求7所述的方法，其中，该第二衬垫不含钌。
9.根据权利要求7所述的方法，其中，该第二衬垫由钴组成。
10.根据权利要求1所述的方法，其中，在该双镶嵌开口的该部分被填充该第一导体层之后，该第一导体层的剩余部分位于该双镶嵌开口的该一个或多个侧壁上，且还包括：
在形成该第二衬垫之前，从位于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口的该一个或多个侧壁上移除该第一导体层的该剩余部分。
11.根据权利要求1所述的方法，其中，该第一导体层通过化学气相沉积或物理气相沉积进行沉积，且该第二导体层通过化学气相沉积或无电沉积进行沉积。
12.一种互连结构，包括：
介电层，具有顶表面以及包括一个或多个侧壁的双镶嵌开口；
第一导体层，位于该双镶嵌开口的一部分中；
第二导体层，设置于该第一导体层以及该介电层的该顶表面之间的该双镶嵌开口中；
第一衬垫，设置于位于该第一导体层以及该双镶嵌开口的该一个或多个侧壁处的该介电层之间，该第一衬垫由第一材料组成；以及
第二衬垫，设置于该第二导体层以及该双镶嵌开口的该一个或多个侧壁处的该介电层之间，该第二衬垫由与该第一衬垫的该第一材料的组成不同的第二材料组成。
13.根据权利要求12所述的互连结构，其中，该双镶嵌开口包括通孔开口以及位于该介电层的该顶表面以及该通孔开口之间的沟槽，且该第一导体层完全填充该通孔开口。
14.根据权利要求12所述的互连结构，其中，该双镶嵌开口包括通孔开口以及位于该介电层的该顶表面以及该通孔开口之间的沟槽，且该第一导体层部分填充该沟槽。
15.根据权利要求12所述的互连结构，其中，该第一衬垫由钌组成，且该第二衬垫不含钌。
16.根据权利要求12所述的互连结构，其中，该第一衬垫由钌组成，且该第二衬垫由钴组成。
17.根据权利要求12所述的互连结构，其中，该第二衬垫还垂直设置于该第一导体层以及该第二导体层之间。
18.根据权利要求12所述的互连结构，还包括：
导电覆盖层，位于该第二导体层上，该导电覆盖层由钴组成。
19.根据权利要求12所述的互连结构，还包括：
金属化层，包括导电特征，
其中，该介电层位于该金属化层上，且该第一导电层直接接触该金属化层中的该导电特征。
20.根据权利要求12所述的互连结构，还包括：
阻障层，位于该第二导体层以及该第二衬垫之间。
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