CN109087855A - 一种改善soi工艺中混合结构边缘凸起的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000005516 engineering process Methods 0.000 title claims abstract description 12
- 230000006872 improvement Effects 0.000 title abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 51
- 239000010703 silicon Substances 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000000873 masking effect Effects 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 5
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 and SOI is high Chemical compound 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 210000000262 cochlear duct Anatomy 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
本发明公开了一种改善SOI工艺中混合结构边缘凸起的方法,其特点是SiN掩蔽下刻蚀形成U形槽后,采用对硅/二氧化硅具有高选择比的气氛用等离子体刻蚀工艺对混合结构的边缘凸起进行横向刻蚀,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等后再进行硅外延生长,使外延硅边缘与SOI硅片表面平齐。本发明与现有技术相比具有工艺简单,制作方便,有效降低了混合结构边缘与SOI的阶高,堆叠栅平整,较好的解决了硅外延生长时横向生长与纵向生长同时存在引起的边缘凸起问题,进一步提高了选择性埋氧器件的性能。
Description
技术领域
本发明涉及半导体绝缘层上硅混合结构技术领域,尤其是一种通过增加刻蚀改善SOI工艺中混合结构边缘凸起的方法。
背景技术
在传统体硅技术中,随着特征尺寸的缩小,器件内部以及器件与器件之间通过衬底的相互耦合作用日渐严重,出现了一系列与材料、器件物理、器件结构和工艺技术等相关的新问题。绝缘层上硅(SOI)技术具有集成密度高,寄生电容小,功耗低,抗闩锁能力及抗辐射能力强等特点,其在集成电路及其他相关应用领域地位日益提升。此外,全耗尽(FD)SOI器件具有更高的电流驱动能力,更小的亚阈值摆幅及良好的等比例缩小能力,而且还能通过改变埋氧层厚度、背板掺杂及背板偏置等参数,实现多种阈值器件以完成电路设计需要。在实现多阈值器件的过程中涉及到的背板偏置就需要涉及到混合结构的形成,即在相应位置把埋氧层(BOX)刻蚀,然后再外延生长硅,使生长的硅表面与SOI表面平齐。
对于上述混合结构,传统的工艺是先刻蚀出混合结构的规则U形槽,然后直接进行硅外延生长。但是由于规则U形槽的侧壁及底部均存在硅种子层,所以在外延过程中,同时存在着硅的横向生长和纵向生长,导致外延结束后在靠近混合结构的边缘处会有凸起。如果混合结构只是作为背板电极,除存在阶高(step high)问题外,外延后存在的边缘凸起对器件特性不会产生太大影响,因为背板电极是通过接触孔引出,而混合结构会设计得比接触孔大很多。但是,该技术形成的选择性埋氧器件,混合结构的上述边缘凸起将会对器件性能产生严重影响,因为这时的混合结构存在于沟道区域,其不仅会改变沟道硅薄膜的厚度,还会引起堆叠栅的不平整,并且也将引起后续工艺过程中阶高问题。
现有技术在硅外延生长时,由于横向生长与纵向生长同时存在而引起的边缘凸起问题,不能降低外延硅边缘与SOI的阶高,使硅外延生长的制备工艺不能应用于选择性埋氧器件(SELBOX device)的制造。
发明内容
本发明的目的是针对现有技术的不足而设计的一种改善SOI工艺中混合结构边缘凸起的方法,采用通过增加刻蚀工艺将形成混合结构时的部分侧壁硅进行补偿刻蚀,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等,较好的解决了硅外延生长时横向生长与纵向生长同时存在引起的边缘凸起问题,使半导体绝缘层上硅混合结构的制备工艺能用于选择性埋氧器件的制造,工艺简单,制作方便,有效降低了混合结构边缘与SOI的阶高,堆叠栅平整,进一步提高了选择性埋氧器件的性能。
本发明的目的是这样实现的:一种改善SOI工艺中混合结构边缘凸起的方法,包括在SOI硅片上淀积SiN薄膜,以及在SiN掩蔽下刻蚀形成U形槽后进行硅外延生长,其特点是SiN掩蔽下刻蚀形成U形槽后,采用对硅/二氧化硅具有高选择比的气氛用等离子体刻蚀工艺对混合结构的边缘凸起进行横向刻蚀,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等后再进行硅外延生长,使外延硅边缘与SOI硅片表面平齐。
本发明与现有技术相比具有简单、实用的特点,较好的解决了硅外延生长时横向生长与纵向生长同时存在引起的边缘凸起问题,使半导体绝缘层上硅混合结构的制备工艺能用于选择性埋氧器件的制造,工艺简单,制作方便,有效降低了混合结构边缘与SOI的阶高,堆叠栅平整,进一步提高了选择性埋氧器件的性能。
具体实施方式
以下通过具体实施例,对本发明作进一步的详细说明。
实施例1
本发明在SOI硅片上淀积SiN薄膜,并在SiN掩蔽下刻蚀形成U形槽后进行硅外延生长,所述SiN掩蔽下刻蚀形成U形槽后采用对硅/二氧化硅具有高选择比的气氛用等离子体刻蚀工艺对混合结构的边缘凸起进行横向刻蚀,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等后再进行硅外延生长,使外延硅边缘与SOI硅片表面平齐,其具体步骤如下:
a、在SOI硅片上淀积SiN薄膜作为掩膜版;
b、淀积光阻并光刻,完成SiN的图形转移;
c、去除光阻;
d、在SiN的掩蔽下刻蚀形成规则U形槽;
e、使用对硅/二氧化硅有着高选择比的刻蚀剂进行刻蚀,并且使等离子体刻蚀剂进行横向刻蚀,即刻蚀U形槽侧壁的硅;
f、硅外延生长;
g、去除SiN。
本发明在FDSOI技术中形成混合结构时,通过在规则U形槽形成之后增加一道刻蚀工艺,刻蚀部分侧壁硅,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等,克服由于硅外延生长时横向生长与纵向生长同时存在引起的边缘凸起问题,可降低混合结构边缘与SOI的阶高,扫除因边缘凸起问题不能用于选择性埋氧器件的障碍。
以上仅为本发明的较佳实施例而已,并不用以限制本发明,凡为本发明等效实施或等同替换的任何修改等,均应包含在本发明的保护范围之内。
Claims (1)
1.一种改善SOI工艺中混合结构边缘凸起的方法,包括在SOI硅片上淀积SiN薄膜,以及在SiN掩蔽下刻蚀形成U形槽后进行硅外延生长,其特征在于SiN掩蔽下刻蚀形成U形槽后,采用对硅/二氧化硅具有高选择比的气氛用等离子体刻蚀工艺对混合结构的边缘凸起进行横向刻蚀,使横向刻蚀掉的侧壁硅厚度恰好与后期外延生长时间内长出来的侧壁硅厚度相等后再进行硅外延生长,使外延硅边缘与SOI硅片表面平齐。
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