TW365696B - Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulation - Google Patents
Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulationInfo
- Publication number
- TW365696B TW365696B TW087101181A TW87101181A TW365696B TW 365696 B TW365696 B TW 365696B TW 087101181 A TW087101181 A TW 087101181A TW 87101181 A TW87101181 A TW 87101181A TW 365696 B TW365696 B TW 365696B
- Authority
- TW
- Taiwan
- Prior art keywords
- silicon
- insulator
- trench
- dimensional
- manufacture
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 title abstract 6
- 239000010703 silicon Substances 0.000 title abstract 6
- 239000012212 insulator Substances 0.000 title abstract 5
- 238000009413 insulation Methods 0.000 title abstract 3
- 239000003990 capacitor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 3
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Method of manufacture of dynamic random access memory using silicon on insulator, including a two-dimensional trench capacitor structure to increase signals of the random access memory cell and the use of a polycrystal silicon memory node structure connecting the on-insulator silicon to the substrate of a semiconductor for the elimination of a floating substrate effect. First, the two-dimensional trench is formed through the on-insulator silicon and the insulation layer beneath it to the semiconductor substrate for forming a vertical trench; and then conduct reactive etch to laterally remove the insulation layer of fixed volume exposed in the vertical trench, forming thus the side of said two-dimensional trench. The polysilicon layer deposited by the two-dimensional trench remains in the two-dimensional trench capacitance, being used as a memory node structure and at the same time, it is connecting the on-insulator silicon to the semiconductor substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW087101181A TW365696B (en) | 1998-02-02 | 1998-02-02 | Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulation |
| JP10150206A JPH11233736A (en) | 1998-02-02 | 1998-05-29 | Manufacture of dynamic random access memory provided with two-dimensional trench capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW087101181A TW365696B (en) | 1998-02-02 | 1998-02-02 | Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW365696B true TW365696B (en) | 1999-08-01 |
Family
ID=21629418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087101181A TW365696B (en) | 1998-02-02 | 1998-02-02 | Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulation |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11233736A (en) |
| TW (1) | TW365696B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI475665B (en) * | 2007-10-26 | 2015-03-01 | Estivation Properties Llc | Semiconductor structure and method of manufacture |
| CN109087855A (en) * | 2018-07-24 | 2018-12-25 | 华东师范大学 | A kind of method of mixed structure edge protuberance in improvement SOI technology |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100532509B1 (en) * | 2004-03-26 | 2005-11-30 | 삼성전자주식회사 | Trench capacitor using SiGe layer and method of fabricating the same |
| JP5758729B2 (en) * | 2011-07-27 | 2015-08-05 | ローム株式会社 | Semiconductor device |
-
1998
- 1998-02-02 TW TW087101181A patent/TW365696B/en not_active IP Right Cessation
- 1998-05-29 JP JP10150206A patent/JPH11233736A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI475665B (en) * | 2007-10-26 | 2015-03-01 | Estivation Properties Llc | Semiconductor structure and method of manufacture |
| CN109087855A (en) * | 2018-07-24 | 2018-12-25 | 华东师范大学 | A kind of method of mixed structure edge protuberance in improvement SOI technology |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11233736A (en) | 1999-08-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |