CN109037424A - 晶片级封装及其制造方法 - Google Patents

晶片级封装及其制造方法 Download PDF

Info

Publication number
CN109037424A
CN109037424A CN201810585187.4A CN201810585187A CN109037424A CN 109037424 A CN109037424 A CN 109037424A CN 201810585187 A CN201810585187 A CN 201810585187A CN 109037424 A CN109037424 A CN 109037424A
Authority
CN
China
Prior art keywords
mentioned
protection dike
wafer
connecting plate
dike
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810585187.4A
Other languages
English (en)
Inventor
韩正勋
朴殷台
河真镐
龙俊佑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TIANJIN WEISHENG ELECTRONICS Co Ltd
Wisol Co Ltd
Original Assignee
TIANJIN WEISHENG ELECTRONICS Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TIANJIN WEISHENG ELECTRONICS Co Ltd filed Critical TIANJIN WEISHENG ELECTRONICS Co Ltd
Publication of CN109037424A publication Critical patent/CN109037424A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/88—Mounts; Supports; Enclosures; Casings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/80411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/80424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/80464—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/80466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/80469—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

适用本发明的晶片级封装，能够包括：基板，包括焊板以及第一保护堤，在一侧面配置有多个电路图案部；印刷电路基板，配置有多个连接板、第二保护堤以及导通孔；以及连接部，与配置在上述印刷电路基板上的上述多个连接板中的一部分以及上述第二保护堤连接。通过适用本发明的晶片级封装及其制造方法，能够提升设计自由度并提升晶片级封装的可靠性。此外，通过本发明，能够在布线设计过程中省略桥接工程并借此简化制造工程并实现元件大小的小型化。

Description

晶片级封装及其制造方法
技术领域
本发明涉及一种晶片级封装及其制造方法。
背景技术
在电子部件中，包括如声表面波(Surface Acoustic Wave；SAW)滤波器、温度补偿晶体振荡器(Temperature Compensation Crystal Osillator；TCXO)、FBAR(薄膜体声波谐振器，FilmBulk Acoustic Resonator)滤波器等需要使内部的特定空间中空的，即需要形成特定空间的气穴(Air Cavity)的芯片。
声表面波(Surface Acoustic Wave；SAW)滤波器是一种利用压电材料通过在表面上传递的频率传递特性而对高频进行滤波的滤波器，为了频率传递而需要确保表面形成气穴，而且如TXCO、FBAR等具有薄膜结构的部件也需要使内部的特定区域形成气穴。
当将如上所述的芯片制作成封装时会以晶片级封装(Wafer Level Package；WLP)的形态进行制作，而且为了防止如水分等污染物质从外部渗透并导致致命性的故障，以其内部空间与外部完全隔离的封装形态实现。
如上所述的半导体元件封装，通常包括：压电基板，形成有包括焊板的电路图案；以及罩盖，为了在保护电路图案免受外部环境影响的同时形成特定空间的气穴(AirCavity)而通过粘合剂粘合到压电基板的表面。
此时，压电基板以及罩盖的CTE(热膨胀系数，Cofficient Thermal Expansion)值之间的差异越大，越有可能因为互不相同的膨胀率而导致其破损的现象，因此通常使用相同类型的物质构成并具有可使紫外线或激光透过的透明性。
晶片级封装的压电基板以及罩盖使用相同类型的物质构成，但是在利用晶片构成压电基板以及罩盖时，具有难以形成导通孔(Via)的问题。
发明内容
本发明提供一种可提升元件的设计自由度的晶片级封装。
适用本发明的晶片级封装，能够包括：基板，包括焊板以及第一保护堤，在一侧面配置有多个电路图案部；印刷电路基板，配置有多个连接板、第二保护堤以及导通孔；以及连接部，与配置在上述印刷电路基板上的上述多个连接板中的一部分以及上述第二保护堤连接。
此外，通过上述连接部与上述第二保护堤连接的连接板能够是接地板。
此外，能够在上述印刷电路基板上与配置于上述基板上的焊板以及第一保护堤对应的位置上，配置连接板以及第二保护堤。
此外，能够在上述印刷电路基板的一侧面配置衬板。
此外，上述衬板能够是用于SMT的衬板。
此外，上述连接板能够利用导电性物质以单层或多层形成。
此外，上述保护堤能够以与上述连接板相同的物质以及结构形成。
此外，在粘合上述焊板和连接板以及第一保护堤和第二保护堤时，其整体结构能够是Cu-Sn-Cu或Au-Sn-Au。
此外，当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Cu-Sn-Cu时，如果上述焊板以及第一保护堤为Cu-Sn层叠结构，则上述连接板以及第二保护堤能够以Cu单层结构构成，而如果上述焊板以及第一保护堤为Cu单层结构，则上述连接板以及第二保护堤能够由Sn-Cu层叠结构构成。
此外，当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Au-Sn-Au时，如果上述焊板以及第一保护堤为Au-Sn层叠结构，则上述连接板以及第二保护堤能够由Au单层结构构成，而如果上述焊板以及第一保护堤为Au单层结构，则上述连接板以及第二保护堤能够由Sn-Au层叠结构构成。
此外，上述印刷电路基板能够由3个铜箔层构成。
此外，能够在与上述焊板对应的位置上，形成贯通上述印刷电路基板的绝缘层的导通孔。
适用本发明的晶片级封装的制造方法，能够包括：在基板上配置电路图案部的步骤；在上述基板的一侧面配置焊板以及第一保护堤的步骤；在印刷电路基板的第二绝缘层的一侧面配置连接板以及第二保护堤的步骤；在第二绝缘层的另一侧面形成第二电路图案层的步骤；在上述连接板上形成贯通第二绝缘层并与第二电路图案层连接的导通孔的步骤；配置对上述第二保护堤和连接板的一部分进行连接的连接部的步骤；在第二绝缘层的另一侧面配置第一绝缘层的步骤；在第一绝缘层的一侧面配置第一电路图案层以及衬板的步骤；在上述第一电路图案层上形成贯通第一绝缘层并与第二电路图案层连接的导通孔的步骤；对上述导通孔内部进行填充的步骤；以及对上述基板和印刷电路基板进行粘合的步骤。
此外，通过上述连接部与上述第二保护堤连接的连接板能够是接地板。
此外，上述印刷电路基板的连接板以及第二保护堤，能够被配置在与配置于上述基板上的焊板以及第一保护堤对应的位置。
此外，在于上述印刷电路基板上配置连接板以及第二保护堤的步骤中，上述连接板能够利用导电性物质以单层或多层形成。
此外，上述第二保护堤能够以与上述连接板相同的导电性物质以及结构形成。
此外，上述衬板能够是用于SMT的衬板。
此外，在对上述基板和印刷电路基板进行粘合的步骤中，能够对上述连接板和焊板以及第一保护堤和第二保护堤进行粘合，而在进行粘合时的整体结构能够是Cu-Sn-Cu或Au-Sn-Au。
此外，当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Cu-Sn-Cu时，如果上述焊板以及第一保护堤为Cu-Sn层叠结构，则上述连接板以及第二保护堤能够由Cu单层结构构成，而如果上述焊板以及第一保护堤为Cu单层结构，则上述连接板以及第二保护堤能够由Sn-Cu层叠结构构成。
此外，当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Au-Sn-Au时，如果上述焊板以及第一保护堤为Au-Sn层叠结构，则上述连接板以及第二保护堤能够由Au单层结构构成，而如果上述焊板以及第一保护堤为Au单层结构，则上述连接板以及第二保护堤能够由Sn-Au层叠结构构成。
通过适用本发明的晶片级封装及其制造方法，能够提升设计自由度。
此外，通过本发明，能够提升晶片级封装的可靠性。
此外，通过本发明，能够在布线设计过程中省略桥接工程并借此简化制造工程。
此外，通过本发明，能够实现元件大小的小型化。
附图说明
图1中对适用本发明的晶片级封装的截面进行了图示。
图2中对适用本发明的晶片级封装的印刷电路基板的截面进行了图示。
图3是对构成印刷电路基板的L3的大致平面图。
图4中对印刷电路基板的连接板位置发生变更后的截面进行了图示。
图5a和图5b中分别对现有的以及适用本发明的基板的平面进行了图示。
图6是用于对适用本发明的晶片级封装的制造方法进行说明的示意图。
图7中对将适用本发明的晶片级封装安装到模块印刷电路基板时的模块的截面进行了图示。
【符号说明】
100：基板
104：电路图案部
106：第一保护堤
108：焊板
130：绝缘层
132：连接板
134：第二保护堤
136：衬板
138：导通孔
140：印刷电路基板
150：绝缘性包装部件
160：模块印刷电路基板
具体实施方式
通过下述的详细说明，将能够进一步明确理解与本发明的上述目的和技术构成及其作用与效果相关的详细信息。在对本发明进行说明的过程中，记载为基板、各个层(膜)、区域、图案或结构体形成或配置于基板、各个层(膜)、区域、板或图案的“上/上侧(On)”或“下/下侧(under)”的内容，包括直接(directly)或以中间介有其他层的状态形成或配置的情况。对各个层的上/上侧或下/下侧的区分，是以附图为基准进行说明。
在下述内容中所使用的如第一、第二等术语，只是用于对相同或相应的构成要素进行区别的识别符号，相同或相应的构成要素并不因为如第一、第二等术语而受到限定。
除非上下文中有明确的相反含义，否则单数型语句还包括复数型含义。如“包括”或“具有”等术语，能够被解释为附加有说明书中所记载的特征、数字、步骤、动作、构成要素、部件或上述之组合的含义。
接下来，将结合附图对本发明进行详细的说明。
图1是适用本发明之实施例的晶片级封装的截面图。
如图1所示，适用本发明的晶片级封装，能够包括：基板100；以及印刷电路基板140。
上述基板100，能够包括：电路图案部104；焊板108；以及第一保护堤106。
上述基板100，能够是LiTaO3晶片、liNbO3晶片以及硅晶片中的一种，但是并不以此为限。
在上述基板100的一侧面，能够配置多个电路图案部104。上述电路图案部104，能够是IDT(叉指式换能器，Inter Digital Transducer)电极部。上述电路图案部104，能够不受限制地利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)以及白金(Pt)等电气特性优秀的物质形成，但是并不以此为限。
上述电路图案部104，能够通过如加成法(Additive)、减成法(Subtractive)、半加成法(semi-Additive)等方法实现，但是并不以此为限。
上述焊板108，能够被配置在上述基板100的一侧面上与上述电路图案部104相隔一定距离的位置。
上述焊板108，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述焊板108，能够采用由导电性物质构成的单层或层叠结构。
上述第一保护堤106，能够以与上述焊板108相隔一定距离的状态配置在上述基板100的周围。
上述第一保护堤106，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述第一保护堤106，能够采用由导电性物质构成的单层或层叠结构。
上述第一保护堤106，能够以与上述焊板108相同的导电性物质以及结构形成。
上述焊板108以及第一保护堤106，能够通过如镀金工艺、蒸镀(Evaporation)工艺以及溅镀(Sputter)工艺等形成，但是并不以此为限。
适用本发明的晶片级封装，能够通过上述基板100与印刷电路基板140的粘合或结合而实现。
接下来，将结合图2对构成上述晶片级封装的印刷电路基板140进行详细的说明。
图2是构成适用本发明之实施例的晶片级封装的印刷电路基板140的截面图。如图2所示，构成适用本发明的晶片级封装的印刷电路基板140，能够包括：绝缘层130；3个铜箔层；连接板132；第二保护堤134；以及连接部a。
上述绝缘层130，能够包括：第一绝缘层130a；以及第二绝缘层130b。
上述铜箔层，能够包括：第一铜箔层L1；第二铜箔层L2；以及第三铜箔层L3。
在上述印刷电路基板140的一侧面上与上述焊板108以及第一保护堤106对应的位置，能够配置多个连接板132以及第二保护堤134。
配置在上述印刷电路基板140上的连接板132以及第二保护堤134，能够与配置在上述基板100上的上述焊板108以及上述第一保护堤106粘合。
上述连接板132，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述第二保护堤134，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述第二保护堤134能够对湿气以及污染物质的流入进行阻隔。
上述第二保护堤134，能够以与上述连接板132相同的导电性物质以及结构形成，但是并不以此为限。
上述绝缘层130能够形成1个以上，在本发明中，是以形成2层绝缘层130的情况为例进行说明，但是并不以此为限。
上述绝缘层130，能够包括：第一绝缘层130a；以及第二绝缘层130b。
上述第一绝缘层130a以及第二绝缘层130b，能够包括如环氧树脂等热硬化性树脂以及如聚酰亚胺等热可塑性树脂。上述第一绝缘层130a，还能够在上述树脂上进一步包括加固材料。上述加固材料能够是如织物、加固材料、无机填充物等，但是并不以此为限。上述织物类加固材料能够是玻璃纤维，能够以玻璃纤维被含浸到树脂中的预浸材料形式形成。
在上述第一绝缘层130a的一侧面，能够形成第一电路图案层(未图示)。
上述第二绝缘层130b，能够被层叠到第一绝缘层130a的另一侧面。即，第二绝缘层130b能够被层叠到包括第一电路图案层(未图示)的一侧面的相反侧面。
在上述第二绝缘层130b的一侧面，能够形成第二电路图案层c。
上述第一绝缘层130a与第二绝缘层130b的厚度能够互不相同。第二绝缘层130b的厚度能够大于第一绝缘层130a的厚度。第一绝缘层130a的厚度只要大于可以配置第一电路图案层(未图示)的程度即可。
在层叠上述绝缘层130之后，能够分别形成导通孔(Via hole)138。即，在分别层叠第一绝缘层130a以及第二绝缘层130b之后，能够配置贯通第一绝缘层130a以及第二绝缘层130b的导通孔138。通过上述导通孔138，能够实现电气连接。
在上述绝缘层130上，能够利用YAG激光或CO2激光以不贯通一侧面的电路图案的方式形成导通孔138。即，能够以保留形成于一侧面上的电路图案的方式形成导通孔138。
上述导通孔138，能够采用在第一绝缘层130a以及第二绝缘层130b的所有层上层叠(stack)形成的结构。
上述导通孔138，能够通过如机械、激光以及化学加工中的某一种加工方式形成，但是并不以此为限。
当通过机械钻孔方式形成上述导通孔138时，导通孔138能够具有一定宽度的截面。
当上述导通孔138的大小小于100um时，采用激光进行加工为宜，而当通过激光加工方式形成导通孔138时，导通孔138的上侧面以及下侧面的大小能够互不相同。作为上述激光加工钻具，使用YAG(钇铝石榴石，Yttriom Alumun Garnet)、CO2激光以及紫外线(UV)激光为宜。
在本发明中，是以通过激光加工方式形成导通孔138的情况为例进行说明，但是并不以此为限。
上述导通孔138的内部被导电性物质填充，导电性物质的填充方式包括如镀金法或导电性浆体填充法等，但是并不以此为限。
在第一铜箔层L1的上部，能够配置衬板136，上述衬板136能够是用于表面安装技术(SMT)的SMT衬板(136)。
表面安装技术(Surface Mount Technology；SMT)是一种将表面安装型部件安装到印刷电路基板的表面之后再进行焊接的技术，是利用多个装备在印刷电路基板的上方安装如半导体或二极管、芯片等并对其进行硬化的方法，在印刷电路基板的两侧面均能够配置部件。
在第二铜箔层L2的上部，能够配置第二电路图案层c，上述第二电路图案层c能够由铜(Cu)层构成，但是并不以此为限。
上述电路图案能够通过印刷电路基板制造工程中的加成工程(AdditiveProcess)、简称工程(Subtractive Process)、MSAP(模拟版加成工程，Modified SemiAdditive Process)以及SAP(半加成工程，Semi Additive Process)等工艺形成。
上述第一电路图案层与上述第二电路图案层c能够通过导通孔138实现电气连接。
在第三铜箔层L3的另一侧面上，能够配置保护堤134与多个连接板132。上述第二保护堤134形成于印刷电路基板140的周围，能够对湿气以及污染物质的流入进行阻隔。
上述连接板132在与基板100的焊板108对应的位置形成。
在上述多个连接板132中的一部分，能够包括与第二保护堤134连接的连接部a。与上述第二保护堤134连接的上述一部分连接板132，能够是接地板GND。
图3是对第三铜箔层L3进行概要性图示的平面图。如图3所示，在上述多个连接板132中的一部分，能够包括与第二保护堤134连接的连接部a。
通过上述连接部a与第二保护堤134连接的连接板132，能够是接地板GND。
上述连接部a能够由Cu单一膜、Sn单一膜、Cu/Sn双重膜等构成，能够通过非电解或电解镀金法形成。
因为借助于上述连接部a能够使接地GND区域增加，因此能够提升晶片级封装的可靠性。
上述基板100与印刷电路基板140能够通过TLP连接(TLP bonding)方式粘合，通过执行TLP连接过程，能够使配置在上述基板100上的焊板108以及保护堤106和配置在上述印刷电路基板140上的连接板132以及第二保护堤相互粘合。
当上述基板100的焊板108为Cu-Sn层叠结构时，上述印刷电路基板140的连接板132以及保护堤134能够是Cu单层结构，而当上述基板100的焊板为Cu单层结构时，上述印刷电路基板140的上述连接板132以及第二保护堤134能够是Sn-Cu层叠结构。
当上述基板100的焊板108以及第一保护堤106与上述印刷电路基板140的连接板132以及第二保护堤134相互粘合时，其整体能够形成Cu-Sn-Cu结构。当上述焊板108与连接板132以及第一保护堤106与第二保护堤134相互粘合时，其整体能够形成Cu-Sn-Cu或Au-Sn-Au结构。
如果上述连接板132与焊板108以及第二保护堤134与第一保护堤106相互粘合且其整体形成Cu-Sn-Cu结构，当上述连接板132以及第二保护堤134为Cu-Sn层叠结构时，则上述焊板108以及第一保护堤106能够由Cu单层结构构成，而当上述连接板132以及第二保护堤134为Cu单层结构时，上述焊板108以及第一保护堤106能够以Sn-Cu层叠结构构成。
如果上述连接板132与焊板108以及第二保护堤134与第一保护堤106相互粘合且其整体形成Au-Sn-Au结构，当上述连接板132以及第二保护堤134为Au-Sn层叠结构时，则上述焊板108以及第一保护堤106能够以Au单层结构构成，而当上述连接板132以及第二保护堤134为Au单层结构时，上述焊板108以及第一保护堤106能够以Sn-Au层叠结构构成。
如上所述的晶片级封装能够由SAW滤波器、TCXO、FBAR中的某一种形成，在晶片级封装由SAW滤波器形成的情况下，当特定频段的电气信号通过导通孔138以及连接板132输入时，电路图案将转换成声表面波并进行滤波，然后再将声表面波转换成具有特定频段频率的电气信号并通过连接板132以及导通孔138传递到外部装置。
图4是印刷电路基板140的连接板132位置发生变更后的截面图。
如图4所示，即使是在连接板132的位置发生变更的情况下，基板100也能够通过由多个铜箔层构成的印刷电路基板140而与衬板136连接。上述衬板136能够是用于表面安装技术(SMT)的衬板。
图5a是现有的基板100的平面图，而图5b是适用本发明之实施例的基板100的平面图。
如图5a以及图5b所示，因为现有的基板需要在衬板上形成导通孔(Via)之后执行SMT，因此焊板108必须位于特定的位置。但是因为在适用本发明的晶片级封装中是通过对基板100和印刷电路基板140进行粘合而固定到模块印刷电路基板中，因此不需要将配置在基板100上的焊板108固定在特定的位置，从而能够自由地配置焊板108以及电路图案部104的位置。
此外，因为在适用本发明的晶片级封装中，能够利用接地端子替代布线设计时所需要的桥接器(Bridge)145，因此能够省略桥接(bridge)工程并借此实现元件的小型化。
借此，在适用本发明的晶片级封装中，因为不需要对衬板136的位置进行固定，因此能够通过上述第二铜箔层L2和第三铜箔层L3以及导通孔138提升基板100的设计自由度。
图6是用于对适用本发明之实施例的晶片级封装的制造方法进行说明的示意图。
如图6的(a)以及(b)所示，能够首先对与印刷电路基板140粘合的基板100进行设计。
在上述基板100上，配置多个电路图案部104。
上述电路图案部104，能够是IDT(叉指式换能器，Inter Digitated Transducer)电极部。上述电路图案部104，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)以及白金(Pt)等电气特性优秀的物质形成，但是并不以此为限。
电路图案部104，能够通过如加成法(Additive)、减成法(Subtractive)、半加成法(semi-Additive)等方法形成，但是并不以此为限。
在上述基板100的一侧面，配置多个焊板108以及第一保护堤106。上述焊板108，能够被配置在与上述电路图案部104相隔一定距离的位置，上述第一保护堤106能够以与上述焊板108相隔一定距离的状态配置在上述基板100的周围。上述焊板108，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)以及白金(Pt)等电气特性优秀的物质形成，但是并不以此为限。上述焊板108，能够采用由导电性物质构成的单层或层叠结构。
上述第一保护堤106，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)以及白金(Pt)等电气特性优秀的物质形成，但是并不以此为限。上述第一保护堤106，能够采用由导电性物质构成的单层或层叠结构。
上述第一保护堤106，能够以与上述焊板108相同的导电性物质以及结构形成。
上述焊板108以及第一保护堤106，能够通过如镀金工艺、蒸镀(Evaporation)工艺以及溅镀(Sputter)工艺等形成，但是并不以此为限。
如图6的(c)至(e)所示，在印刷电路基板140的第二绝缘层130b一侧面上与基板100的焊板108以及第一保护堤106对应的位置，配置有多个连接板132以及第二保护堤134。上述第二保护堤134，能够以与上述连接板132相隔一定距离的状态配置在印刷电路基板140的周围。
上述印刷电路基板140的连接板132，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述印刷电路基板140的第二保护堤134，能够利用导电性物质构成，例如能够利用如铜(Cu)、银(Ag)、钯(Pd)、铝(Al)、镍(Ni)、钛(Ti)、金(Au)、白金(Pt)以及锡(Sn)等电气特性优秀的物质形成，但是并不以此为限。
上述焊板108以及第二保护堤134，能够采用由导电性物质构成的单层或层叠结构。
上述第二保护堤134，能够采用与上述连接板132相同的导电性物质以及结构，但是并不以此为限。
在第二绝缘层130b的上部，能够配置第二电路图案层c。
在上述印刷电路基板140的连接板132以及第二保护堤134上，能够形成贯通第二绝缘层130b并与第二电路图案层c连接的导通孔138。
在形成上述导通孔138之后，上述导通孔138的内部将被如铜(Cu)、金(Au)等导电性物质填充，导电性物质的填充方式包括如镀金法或导电性浆体填充法等，但是并不以此为限。
能够配置与上述第二保护堤134以及上述连接板132的一部分连接的连接部a。通过上述连接部a与第二保护堤134连接的连接板132，能够是接地GND板。上述连接部a能够由Cu单一膜、Sn单一膜、Cu/Sn双重膜等构成，能够通过非电解或电解镀金法形成。
如图6的(f)至(i)所示，在第一绝缘层130a上部的特定位置形成用于表面安装技术(SMT)的衬板136。
在上述第二绝缘层130b的一侧面，能够配置第一绝缘层130a。
在上述第一绝缘层130a的一侧面，能够形成第一电路图案层(未图示)。
为了实现上述第二电路图案层c与上述第一电路图案层的电气连接，能够形成贯通第一绝缘层130a的导通孔138。
在形成上述导通孔138之后，上述导通孔138的内部将被如铜(Cu)、金(Au)等导电性物质填充，导电性物质的填充方式包括如镀金法或导电性浆体填充法等，但是并不以此为限。
如图6的(j)所示，对上述基板100和上述印刷电路基板140进行粘合。
通过上述基板100的焊板108以及第一保护堤106以及上述印刷电路基板140的连接板132以及第二保护堤134，能够对上述基板100和上述印刷电路基板140进行粘合。
上述基板100和上述印刷电路基板140，能够通过适当的温度、压力以及真空度实现TLP连接。
实现上述TLP连接所需的条件包括温度、压力以及真空度，上述温度为230度至350度，上述压力位100kgf至2000kgf，上述真空度为常压至torr。
上述温度、压力以及真空度条件仅为在本发明中实现TLP连接所需的条件，但是并不以此为限。
图7是将适用本发明之实施例的晶片级封装安装到模块印刷电路基板时的模块的截面图。
如图7所示，能够通过将晶片级封装配置到模块印刷电路基板160上并利用绝缘性包装部件150对晶片级封装进行覆盖而制造出模块。
尤其是，内存模块印刷电路基板是通过将多个内存半导体元件封装安装到表面而实现模块化的印刷电路基板，根据适用领域，能够对PC以及服务器的DRAM容量进行扩展。
内存模块印刷电路基板能够起到扩展内存容量或数据输入/输出(data Input/Output)的作用。
在上述内容中对本发明进行了详细的说明，但是具有本发明所属技术领域之一般知识的人员应该能够理解，在维持本发明的技术思想以及必要特征的情况下也能够以其他不同的形态实现。
本发明的范围由权利要求书进行确定，但是从权利要求书的记载事项直接导出的构成以及从与其等价的构成导出的所有变更或变形形态，也应该解释为包含在本发明的权利要求范围之内。

Claims (21)

1.一种晶片级封装，其特征在于，包括：
基板，包括焊板以及第一保护堤，在一侧面配置有多个电路图案部；
印刷电路基板，配置有多个连接板、第二保护堤以及导通孔；以及
连接部，与配置在上述印刷电路基板上的上述多个连接板中的一部分以及上述第二保护堤连接。
2.根据权利要求1所述的晶片级封装，其特征在于：
通过上述连接部与上述第二保护堤连接的连接板为接地板。
3.根据权利要求1所述的晶片级封装，其特征在于：
在上述印刷电路基板上与配置于上述基板上的焊板以及第一保护堤对应的位置上，配置连接板以及第二保护堤。
4.根据权利要求1所述的晶片级封装，其特征在于：
在上述印刷电路基板的一侧面配置衬板。
5.根据权利要求4所述的晶片级封装，其特征在于：
上述衬板为用于SMT的衬板。
6.根据权利要求1所述的晶片级封装，其特征在于：
上述连接板利用导电性物质以单层或多层形成。
7.根据权利要求1所述的晶片级封装，其特征在于：
上述保护堤以与上述连接板相同的物质以及结构形成。
8.根据权利要求1所述的晶片级封装，其特征在于：
在粘合或结合上述焊板和连接板以及第一保护堤和第二保护堤时，其整体结构为Cu-Sn-Cu或Au-Sn-Au。
9.根据权利要求8所述的晶片级封装，其特征在于：
当粘合或结合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Cu-Sn-Cu时，如果上述焊板以及第一保护堤为Cu-Sn层叠结构，则上述连接板以及第二保护堤由Cu单层结构构成，而如果上述焊板以及第一保护堤为Cu单层结构，则上述连接板以及第二保护堤由Sn-Cu层叠结构构成。
10.根据权利要求8所述的晶片级封装，其特征在于：
当粘合或结合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Au-Sn-Au时，如果上述焊板以及第一保护堤为Au-Sn层叠结构，则上述连接板以及第二保护堤由Au单层结构构成，而如果上述焊板以及第一保护堤为Au单层结构，则上述连接板以及第二保护堤由Sn-Au层叠结构构成。
11.根据权利要求1所述的晶片级封装，其特征在于：
上述印刷电路基板由3个铜箔层构成。
12.根据权利要求1所述的晶片级封装，其特征在于：
在与上述焊板对应的位置上，形成贯通上述印刷电路基板的绝缘层的导通孔。
13.一种晶片级封装的制造方法，其特征在于，包括：
在基板上配置电路图案部的步骤；
在上述基板的一侧面配置焊板以及第一保护堤的步骤；
在印刷电路基板的第二绝缘层的一侧面配置连接板以及第二保护堤的步骤；
在第二绝缘层的另一侧面形成第二电路图案层的步骤；
在上述连接板上形成贯通第二绝缘层并与第二电路图案层连接的导通孔的步骤；
配置对上述第二保护堤和连接板的一部分进行连接的连接部的步骤；
在第二绝缘层的另一侧面配置第一绝缘层的步骤；
在第一绝缘层的一侧面配置第一电路图案层以及衬板的步骤；
在上述第一电路图案层上形成贯通第一绝缘层并与第二电路图案层连接的导通孔的步骤；
对上述导通孔内部进行填充的步骤；以及
对上述基板和印刷电路基板进行粘合的步骤。
14.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
通过上述连接部与上述第二保护堤连接的连接板为接地板。
15.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
上述印刷电路基板的连接板以及第二保护堤，被配置在与配置于上述基板上的焊板以及第一保护堤对应的位置。
16.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
上述连接板利用导电性物质以单层或多层形成。
17.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
上述第二保护堤以与上述连接板相同的导电性物质以及结构形成。
18.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
上述衬板为用于SMT的衬板。
19.根据权利要求13所述的晶片级封装的制造方法，其特征在于：
在对上述基板和印刷电路基板进行粘合的步骤中，对上述连接板和焊板以及第一保护堤和第二保护堤进行粘合，而在进行粘合时的整体结构为Cu-Sn-Cu或Au-Sn-Au。
20.根据权利要求19所述的晶片级封装的制造方法，其特征在于：
当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Cu-Sn-Cu时，如果上述焊板以及第一保护堤为Cu-Sn层叠结构，则上述连接板以及第二保护堤由Cu单层结构构成，而如果上述焊板以及第一保护堤为Cu单层结构，则上述连接板以及第二保护堤由Sn-Cu层叠结构构成。
21.根据权利要求19所述的晶片级封装的制造方法，其特征在于：
当粘合上述焊板和连接板以及第一保护堤和第二保护堤时的整体结构为Au-Sn-Au时，如果上述焊板以及第一保护堤为Au-Sn层叠结构，则上述连接板以及第二保护堤由Au单层结构构成，而如果上述焊板以及第一保护堤为Au单层结构，则上述连接板以及第二保护堤由An-Cu层叠结构构成。
CN201810585187.4A 2017-06-08 2018-06-08 晶片级封装及其制造方法 Pending CN109037424A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170071855A KR20180134237A (ko) 2017-06-08 2017-06-08 웨이퍼레벨패키지 및 제조방법
KR10-2017-0071855 2017-06-08

Publications (1)

Publication Number Publication Date
CN109037424A true CN109037424A (zh) 2018-12-18

Family

ID=64564352

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810585187.4A Pending CN109037424A (zh) 2017-06-08 2018-06-08 晶片级封装及其制造方法

Country Status (3)

Country Link
US (1) US10446506B2 (zh)
KR (1) KR20180134237A (zh)
CN (1) CN109037424A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111130481A (zh) * 2019-12-31 2020-05-08 诺思(天津)微系统有限责任公司 具有叠置单元的半导体结构及制造方法、电子设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220111089A (ko) 2021-02-01 2022-08-09 삼성전자주식회사 반도체 패키지
CN113097081B (zh) * 2021-03-31 2022-12-06 苏州汉天下电子有限公司 一种晶圆级封装结构及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378922B2 (en) * 2004-07-20 2008-05-27 Murata Manufacturing Co., Ltd. Piezoelectric filter
CN102386166A (zh) * 2005-04-01 2012-03-21 斯盖沃克斯瑟路申斯公司 包括与无源元件集成的器件晶片的晶片级封装
CN105870317A (zh) * 2015-01-13 2016-08-17 Wisol株式会社 压电元件装置
CN106711319A (zh) * 2016-12-23 2017-05-24 无锡市好达电子有限公司 Csp封装的声表面波滤波器芯片隔离槽

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10251658B4 (de) * 2002-11-01 2005-08-25 Atotech Deutschland Gmbh Verfahren zum Verbinden von zur Herstellung von Mikrostrukturbauteilen geeigneten, mikrostrukturierten Bauteillagen sowie Mikrostrukturbauteil
JP4342174B2 (ja) * 2002-12-27 2009-10-14 新光電気工業株式会社 電子デバイス及びその製造方法
US7061099B2 (en) * 2004-09-30 2006-06-13 Intel Corporation Microelectronic package having chamber sealed by material including one or more intermetallic compounds
JP4744213B2 (ja) * 2005-07-11 2011-08-10 日本電波工業株式会社 電子部品の製造方法
US10873311B2 (en) * 2017-02-15 2020-12-22 Skyworks Solutions, Inc. Acoustic resonators with reduced loss characteristics and methods of manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378922B2 (en) * 2004-07-20 2008-05-27 Murata Manufacturing Co., Ltd. Piezoelectric filter
CN102386166A (zh) * 2005-04-01 2012-03-21 斯盖沃克斯瑟路申斯公司 包括与无源元件集成的器件晶片的晶片级封装
CN105870317A (zh) * 2015-01-13 2016-08-17 Wisol株式会社 压电元件装置
CN106711319A (zh) * 2016-12-23 2017-05-24 无锡市好达电子有限公司 Csp封装的声表面波滤波器芯片隔离槽

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111130481A (zh) * 2019-12-31 2020-05-08 诺思(天津)微系统有限责任公司 具有叠置单元的半导体结构及制造方法、电子设备

Also Published As

Publication number Publication date
US10446506B2 (en) 2019-10-15
KR20180134237A (ko) 2018-12-18
US20180358308A1 (en) 2018-12-13

Similar Documents

Publication Publication Date Title
EP3288184B1 (en) Embedded rf filter package structure and method of manufacturing thereof
US8294535B2 (en) Electrical component and production method
KR100691160B1 (ko) 적층형 표면탄성파 패키지 및 그 제조방법
JP4645233B2 (ja) 弾性表面波装置
CN109037424A (zh) 晶片级封装及其制造方法
CN109937533B (zh) 晶体振动器件
CN103795370A (zh) 电子元件模块
KR20060095092A (ko) 고주파 모듈 부품 및 그 제조 방법
JP2010045201A (ja) 電子部品モジュール及びその製造方法
US8536959B1 (en) Substrate with built-in electronic component
JP2010166018A (ja) 電子部品およびその製造方法
KR102611168B1 (ko) 음향파 디바이스 및 그 제조방법
US20040226741A1 (en) Package for electronic device, base substrate, electronic device and fabrication method thereof
KR100482889B1 (ko) Ｓａｗ 필터 모듈
JP6385883B2 (ja) モジュールおよびモジュールの製造方法
JP2008113894A (ja) 半導体装置及び、電子装置
KR102295454B1 (ko) 전자 부품 및 그것을 구비하는 모듈
KR101145258B1 (ko) 반도체 패키지 생산 시스템 및 방법
CN109037198A (zh) 晶片级封装及其制造方法
JP2013539253A (ja) モジュール及びその製造方法
JP2002359343A (ja) 半導体装置
JP2011097247A (ja) 高周波モジュールおよびその製造方法
JP2003101382A (ja) 弾性表面波装置
JP2022169399A (ja) 弾性波デバイス、その弾性波デバイスを備えるモジュール、およびその弾性波デバイスの製造方法
JP4910953B2 (ja) 電子部品パッケージ構造

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20181218

WD01 Invention patent application deemed withdrawn after publication