CN109037410A - The semiconductor chip and its current extending and manufacturing method of light emitting diode - Google Patents
The semiconductor chip and its current extending and manufacturing method of light emitting diode Download PDFInfo
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- CN109037410A CN109037410A CN201810913923.4A CN201810913923A CN109037410A CN 109037410 A CN109037410 A CN 109037410A CN 201810913923 A CN201810913923 A CN 201810913923A CN 109037410 A CN109037410 A CN 109037410A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 291
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 128
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 460
- 239000011241 protective layer Substances 0.000 claims description 39
- 230000004888 barrier function Effects 0.000 claims description 34
- 239000000872 buffer Substances 0.000 claims description 32
- 150000004767 nitrides Chemical class 0.000 claims description 30
- 230000008021 deposition Effects 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 229910000077 silane Inorganic materials 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 6
- 230000001351 cycling effect Effects 0.000 claims description 5
- 230000034655 secondary growth Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 4
- 241000208340 Araliaceae Species 0.000 claims 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 2
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 2
- 235000008434 ginseng Nutrition 0.000 claims 2
- 238000000151 deposition Methods 0.000 description 22
- 230000012010 growth Effects 0.000 description 9
- 230000005611 electricity Effects 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 3
- 239000011777 magnesium Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses the semiconductor chip of a light emitting diode and its current extending and manufacturing methods, wherein the semiconductor chip includes a substrate, one n type gallium nitride layer, one current extending, one quantum well layer, one p-type gallium nitride layer, one N-type electrode and a P-type electrode, the n type gallium nitride is laminated on the substrate layer by layer, the current extending is laminated in the n type gallium nitride layer, wherein the current extending includes at least a N-GaN layers be layered on top of each other and at least a U-GaN layers, the quantum well layer is laminated in the current extending, the p-type gallium nitride layer is laminated in the quantum well layer, the N-type electrode is electrically connected to the current extending, the P-type electrode is electrically connected to the p-type gallium nitride layer.The current extending can weaken the longitudinal current extended capability of the semiconductor chip and improve lateral current ability, in this way, being conducive to being uniformly distributed for electric current, to improve the luminous efficiency of the semiconductor chip.
Description
Technical field
The present invention relates to light emitting diode, in particular to the semiconductor chip of a light emitting diode and its current extending and
Manufacturing method.
Background technique
In recent years, as LED (Light Emitting Diode) is by large-scale promotion and application, LED the relevant technologies
Also obtained advancing by leaps and bounds the development of formula.And III-V nitride belongs to direct band-gap semicondictor, big with forbidden bandwidth,
The excellent physical characteristics such as high, the electronics saturation mobility height of breakdown electric field, therefore, application of the III-V nitride in LED field
It has received widespread attention.In the LED for applying III-V nitride, sent out by the blue light of main material, white light of GaN base
Optical device has the efficiency more than previous any conventional lighting sources, this is widely used in the luminescent device of the LED of GaN base
Various novel industries, especially high-power, large scale, high current density LED luminescent device, due to its brilliant device
Can and broad application prospect and expected.However, due to the luminescent device of the LED of GaN base current density with higher,
This causes the luminescent device of the LED of GaN base to be inevitably present some defects, for example, the luminescent device of the LED of GaN base holds
It is easily easy to cause undesirable influence to the service life of luminescent device, stability because of electric current congestion effect, and close in high current
Under degree, auger recombination aggravation, non-radiative recombination specific gravity increases, and efficiency rapid drawdown is obvious and current spread scarce capacity, entirety are sent out
Light is uneven, cannot play the performance of luminescent device to the maximum extent.In addition, the luminescent device of the LED in existing GaN base
In, only using GaN layer as current extending, this causes the Longitudinal Extension of the luminescent device of the LED of existing GaN base very capable,
And ability extending transversely gradually weakens with the increase of distance, and then causes the Integral luminous of the luminescent device of LED uneven
Even, be in particular in: luminescent device is stronger more the area luminescent intensity for being proximate to P-type electrode, and is more being proximate to N-type electrode
Area luminescent intensity it is weaker, meanwhile, cause surface resistance to increase because current expansion is insufficient in the region close to N-type electrode,
Fever is serious, and then has severely impacted the service life of luminescent device.
Summary of the invention
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Make method, wherein the semiconductor chip especially suitable for high power, large scale, high current density light emitting diode.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Method is made, wherein can equably be extended from the electric current that the P-type electrode of the semiconductor chip is injected, so that described partly lead
Each light emitting region of body chip can equably shine.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Method is made, wherein the longitudinal current extended capability of the semiconductor chip is weakened, lateral current ability is enhanced, so that
The electric current injected from the P-type electrode can be extended equally to the region of N-type electrode.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Method is made, wherein the semiconductor chip provides a n type gallium nitride layer and is laminated in a current expansion of the n type gallium nitride layer
Layer, wherein the current extending can weaken the longitudinal current extended capability of the semiconductor chip and enhance the semiconductor
The lateral current ability of chip.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Method is made, wherein after the current extending is laminated in the n type gallium nitride layer, longitudinal electricity of the semiconductor chip
Resistance is increased, in this way, on the one hand, the too strong longitudinal current extended capability of the semiconductor chip is weakened,
Reduce the output of auger recombination and non-radiative recombination, on the other hand, improves the lateral current of the semiconductor chip
Ability, so that the homogeneous current distribution of the entire semiconductor chip, luminous efficiency is higher, not only increases partly lead in this way
The optical property of body chip, and can effectively extend the service life of the semiconductor chip.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Method is made, wherein the current extending is formed in such a way that N-GaN layers and U-GaN layers are layered on top of each other, in this way
Mode, the current extending can improve laterally while weakening the longitudinal current extended capability of the semiconductor chip
Current expansion ability.
It is an object of the present invention to provide a kind of semiconductor chip of light emitting diode and its current extending and systems
Make method, wherein any one of U-GaN layers of two sides of the current extending be it is N-GaN layers described, in this way
Mode, can guarantee the stability and reliability of the semiconductor chip.
One aspect under this invention, the present invention provide the semiconductor chip of a light emitting diode comprising:
One substrate；
One n type gallium nitride layer, wherein the n type gallium nitride is laminated on the substrate layer by layer；
One current extending, wherein the current extending is laminated in the n type gallium nitride layer, wherein the current expansion
Layer includes at least a N-GaN layers be layered on top of each other and at least a U-GaN layers；
One quantum well layer, wherein the quantum well layer is laminated in the current extending；
One p-type gallium nitride layer, wherein the p-type gallium nitride layer is laminated in the quantum well layer；
One N-type electrode, wherein the N-type electrode is electrically connected to the current extending；And
One P-type electrode, wherein the P-type electrode is electrically connected to the p-type gallium nitride layer.
According to one embodiment of present invention, any one of U-GaN layers of two sides of the current extending are
It is N-GaN layers described, and described N-GaN layers of one of the current extending contacts with the n type gallium nitride layer, the electric current
Another described the N-GaN layers of extension layer is contacted with the quantum well layer.
According to one embodiment of present invention, if the U-GaN layers of layer number parameter of the current extending is X, institute
The N-GaN layers of layer number parameter for stating current extending is X+1, wherein the value range of parameter X are as follows: 5≤X≤30.
According to one embodiment of present invention, one of the current extending described U-GaN layers in the n type gallium nitride
Layer contact, described N-GaN layers of one of the current extending contacts in the quantum well layer.
According to one embodiment of present invention, the thickness range of the current extending is 0.1 μm -1 μm.
According to one embodiment of present invention, the N-GaN layers of thickness range of the current extending is
5nm-15nm, described U-GaN layers of thickness range are 5nm-15nm.
According to one embodiment of present invention, the N-GaN layers of the current extending are silicon doped layer, wherein adulterating
Concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
According to one embodiment of present invention, the semiconductor chip further comprises a nitride buffer layer, wherein institute
It states nitride buffer layer and is laminated in the substrate, the n type gallium nitride is laminated on the nitride buffer layer layer by layer.
According to one embodiment of present invention, the semiconductor chip further comprises a protective layer, wherein the protection
It is laminated on the quantum well layer layer by layer, the p-type gallium nitride layer is laminated in the protective layer.
According to one embodiment of present invention, the semiconductor chip further comprises a protective layer and an electronic blocking
Layer, wherein the protective layer is laminated in the quantum well layer, the electronic barrier layer is laminated in the protective layer, the p-type nitrogen
Change gallium and is laminated on the electronic barrier layer layer by layer.
According to one embodiment of present invention, the semiconductor chip further comprises an electronic barrier layer, wherein described
Electronic barrier layer is laminated in the quantum well layer, and the p-type gallium nitride layer is laminated in the electronic barrier layer.
Other side under this invention, the present invention further provides the current extendings of semiconductor chip comprising
At least a N-GaN layers and at least a U-GaN layers be layered on top of each other.
According to one embodiment of present invention, any one of U-GaN layers of two sides of the current extending are
It is N-GaN layers described.
According to one embodiment of present invention, if the U-GaN layers of layer number parameter of the current extending is X, institute
The N-GaN layers of layer number parameter for stating current extending is X+1, wherein the value range of parameter X are as follows: 5≤X≤30.
According to one embodiment of present invention, the thickness range of the current extending is 0.1 μm -1 μm.
According to one embodiment of present invention, the N-GaN layers of thickness range of the current extending is
5nm-15nm, described U-GaN layers of thickness range are 5nm-15nm.
According to one embodiment of present invention, the N-GaN layers of the current extending are silicon doped layer, wherein adulterating
Concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
Other side under this invention, the present invention further provides the manufacturers of the semiconductor chip of a light emitting diode
Method, wherein the manufacturing method includes the following steps:
(a) one n type gallium nitride layer of stacking is in a substrate；
(b) from one N-GaN layers of the n type gallium nitride layer cycling deposition and a U-GaN layer, with one current extending of stacking in
The n type gallium nitride layer；
(c) one quantum well layer of stacking is in the current extending；
(d) one p-type gallium nitride layer of stacking is in the quantum well layer；And
(e) one N-type electrode of electrical connection is in the current extending and one P-type electrode of electrical connection in the p-type gallium nitride layer.
According to one embodiment of present invention, further comprise step in the step (b):
(b.1) keep the substrate for being laminated with the n type gallium nitride layer heavy in a Metal Organic Vapor extension
Product equipment；
(b.2) source Ga, the source N and silane are passed through in the Metal Organic Vapor epitaxial deposition equipment, to grow silicon
The N-GaN layers of doping are in the n type gallium nitride layer；
(b.3) it is passed through the source Ga and N is derived from the Metal Organic Vapor epitaxial deposition equipment, it is undoped to grow
Described U-GaN layers in N-GaN layers described；And
(b.4) step (b.2) and the step (b.3) are recycled, the current extending is laminated in the N-type nitrogen
Change gallium layer.
According to one embodiment of present invention, further comprise step in the step (b):
(b.1) keep the substrate for being laminated with the n type gallium nitride layer heavy in a Metal Organic Vapor extension
Product equipment；
(b.2) it is passed through the source Ga and N is derived from the golden Metal Organic Vapor epitaxial deposition equipment, it is undoped to grow
The U-GaN layers in the n type gallium nitride layer；
(b.3) source Ga, the source N and silane are passed through in the Metal Organic Vapor epitaxial deposition equipment, to grow silicon
The N-GaN layers of doping are in N-GaN layers described；And
(b.4) step (b.2) and the step (b.3) are recycled, the current extending is laminated in the N-type nitrogen
Change gallium layer.
According to one embodiment of present invention, in the step (b), the step (b.2) and the step (b.3)
Cycle period range is -30 periods of 5 periods.
According to one embodiment of present invention, if the U-GaN layers of layer number parameter of the current extending is X, institute
The N-GaN layers of layer number parameter for stating current extending is X+1, wherein the value range of parameter X are as follows: 5≤X≤30.
According to one embodiment of present invention, the thickness range of the current extending is 0.1 μm -1 μm.
According to one embodiment of present invention, the N-GaN layers of thickness range of the current extending is
5nm-15nm, described U-GaN layers of thickness range are 5nm-15nm.
According to one embodiment of present invention, the N-GaN layers of the current extending are silicon doped layer, wherein adulterating
Concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
According to one embodiment of present invention, further comprise step in the step (a): growing a nitridation first
Gallium buffer layer is in the substrate, and n type gallium nitride layer described in secondary growth is in the nitride buffer layer, so that the N-type nitrogenizes
Gallium is laminated on the substrate layer by layer.
According to one embodiment of present invention, before the step (d), the manufacturing method into one comprising steps of
A protective layer is grown first in the quantum well layer, and one electronic barrier layer of secondary growth is in the protective layer, then in the step
Suddenly in (d), the p-type gallium nitride layer is grown in the electronic barrier layer, so that the p-type gallium nitride layer is laminated in the quantum
Well layer.
Detailed description of the invention
Fig. 1 is the schematic cross-sectional view of the semiconductor chip of a preferred embodiment under this invention.
Fig. 2 is the section view signal of a current extending of the semiconductor chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 3 is the current expansion schematic illustration of the semiconductor chip of above-mentioned preferred embodiment under this invention.
Specific embodiment
It is described below for disclosing the present invention so that those skilled in the art can be realized the present invention.It is excellent in being described below
Embodiment is selected to be only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It defines in the following description
Basic principle of the invention can be applied to other embodiments, deformation scheme, improvement project, equivalent program and do not carry on the back
Other technologies scheme from the spirit and scope of the present invention.
It will be understood by those skilled in the art that in exposure of the invention, term " longitudinal direction ", " transverse direction ", "upper",
The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed
System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present invention and simplification of the description, without referring to
Show or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore above-mentioned art
Language is not considered as limiting the invention.
It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment,
The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no
It can be interpreted as the limitation to quantity.
With reference to Figure of description of the invention attached drawing 1 to Fig. 3, a light-emitting diodes of a preferred embodiment under this invention
The semiconductor chip of pipe is disclosed for and is set forth in following description, wherein the semiconductor chip include a substrate 10,
One n type gallium nitride layer 20, a current extending 30, a quantum well layer 40, a p-type gallium nitride layer 50, a N-type electrode 60 and one
P-type electrode 70.
The n type gallium nitride layer 20 is laminated in the substrate 10, and the current extending 30 is laminated in the n type gallium nitride
Layer 20, the quantum well layer 40 is laminated in the current extending 30, and the p-type gallium nitride layer 50 is laminated in the quantum well layer
40, the N-type electrode 60 is electrically connected to the current extending 30, and the P-type electrode 70 is electrically connected to the p-type nitridation
Gallium layer 50.
When the N-type electrode 60 of the semiconductor chip and the P-type electrode 70 respectively by access power supply when, from described in
The electric current that P-type electrode 70 is injected the semiconductor chip can be through the quantum well layer 40 to the current extending 30 and institute
It states 20 direction of n type gallium nitride layer to extend along the longitudinal direction of the semiconductor chip, and along 50 He of p-type gallium nitride layer
The current extending 30 is extended along the transverse direction of the semiconductor chip, so that electric current can be evenly distributed over
In the semiconductor chip, in this way, the semiconductor chip can equably shine.I shown in attached drawing 3H
It indicates electric current extending transversely, correspondingly, I is shown in attached drawing 3VExpression Longitudinal Extension electric current.
The current extending 30 increases the longitudinal electrical resistance of the semiconductor chip, in this way, the electricity
Stream extension layer 30 can weaken the longitudinal current extended capability of the semiconductor chip, and the current extending 30 can make
It obtains electric current to extend along the transverse direction of the semiconductor chip, to improve the lateral current energy of the semiconductor chip
Power, so that electric current is distributed evenly at the semiconductor chip.
It is noted that " stacking " involved in the present invention can be direct stacking, it is also possible to be laminated indirectly.Example
Such as, the n type gallium nitride layer 20 is laminated in the substrate 10 can to refer to that the n type gallium nitride layer 20 is laminated in indirectly described
Substrate 10, that is, other layers are also provided between the n type gallium nitride layer 20 and the substrate 10, in following description
In, the present invention will disclose the type of other layers being located between the n type gallium nitride layer 20 and the substrate 10 in detail.Accordingly
Ground, the current extending 30, which is laminated in the n type gallium nitride layer 20, can refer to that the current extending 30 is directly laminated
In the n type gallium nitride layer 20, that is, the current extending 30 is grown on the n type gallium nitride with the current extending 30
The mode of layer 20 is laminated in the n type gallium nitride layer 20.
Specifically, with reference to attached drawing 2, the current extending 30 includes an at least N-GaN layer 31 and at least one U-GaN layers
32, wherein N-GaN layer 31 and U-GaN layer 32 are layered on top of each other, so that the current extending 30 is in short transverse
The resistance states of " low-resistance-high resistant-low-resistance-high resistant ... " can be showed, in this way, on the one hand, the electric current
Extension layer 30 is increased the longitudinal electrical resistance of the semiconductor chip, so that the longitudinal current for weakening the semiconductor chip expands
Exhibition ability, on the other hand, the current extending 30 makes the lateral current ability of the semiconductor chip by effectively
It is promoted, so that being conducive to electric current is evenly distributed over and improves luminous efficiency, this optical property for the semiconductor chip
It has a greater degree of improvement with service life.
That is, the current extending 30 be laminated in the n type gallium nitride layer 20 by 31 He of N-GaN layer
Short period superlattice (Short Period Superlattice, SPS) laminated construction that the U-GaN layer 32 is layered on top of each other.
Preferably, the number of plies of the N-GaN layer 31 of the current extending 30 is more than the number of plies of the U-GaN layer 32,
So that the two sides of any one of U-GaN layer 32 of the current extending 30 are the N-GaN layers 31, and make
A N-GaN layer 31 for obtaining the current extending 30 is contacted with the n type gallium nitride layer 20, the current extending 30
Another described N-GaN layer 31 contacted with the quantum well layer 40.For example, setting the U-GaN of the current extending 30
The number of plies of layer 32 is parameter X, then the number of plies of the N-GaN layer 31 of the current extending 30 is parameter X+1, that is, the electricity
Flow extension layer 30 the N-GaN layer 31 the number of plies than the U-GaN layer 32 the number of plies more than one layer so that the electric current expansion
Exhibition layer 30 a N-GaN layer 31 can be contacted with the n type gallium nitride layer 20, the current extending 30 another
The N-GaN layer 31 can be contacted with the quantum well layer 40, in this way, advantageously ensure that the semiconductor chip
Reliability.
With reference to attached drawing 1, the semiconductor chip further comprises a nitride buffer layer 80, wherein the gallium nitride buffers
Layer 80 is laminated in the substrate 10, and the n type gallium nitride layer 20 is laminated in the nitride buffer layer 80, so that the gallium nitride
Buffer layer 80 is maintained between the substrate 10 and the n type gallium nitride layer 20.That is, the n type gallium nitride layer 20
The nitride buffer layer 80 is laminated in the n type gallium nitride layer 20 and the nitride buffer layer 80 is laminated in the substrate
10 mode is laminated in the substrate 10, that is, the n type gallium nitride layer 20 is laminated in the substrate 10 indirectly.Described half
In conductor chip, the nitride buffer layer 80 can be to be maintained between the substrate 10 and the n type gallium nitride layer 20
Mode avoid the problem that lattice mismatch, to advantageously ensure that the reliability of the semiconductor chip.
With continued reference to attached drawing 1, the semiconductor chip further comprises a protective layer 90, wherein the protective layer 90 is laminated
In the quantum well layer 40, wherein the protective layer 90 is able to maintain that the crystal quality of the quantum well layer 40, to avoid described
Semiconductor chip is in subsequent manufacturing process to the component and/or structural damage of the quantum well layer 40.Preferably, described
The thickness range of protective layer 90 is 30nm-100nm (including 30nm and 100nm).The p-type gallium nitride layer 50 is laminated in institute
State protective layer 90.
With continued reference to attached drawing 1, the semiconductor chip further comprises an electronic barrier layer 100, wherein the electronics hinders
Barrier 100 is laminated in the protective layer 90, and the p-type gallium nitride layer 50 is laminated in the electronic barrier layer 100, wherein the electricity
Sub- barrier layer 100 band gap with higher, to be able to suppress electron leak electric current, to guarantee the reliable of the semiconductor chip
Property.
In following description, by conjunction with the growth course of the semiconductor chip further describe it is of the invention described in
The substrate 10 of semiconductor chip, the nitride buffer layer 80, the n type gallium nitride layer 20, the current extending 30,
The quantum well layer 40, the protective layer 90, the electronic barrier layer 100, the p-type gallium nitride layer 50, the N-type electrode 60
Correlation between the P-type electrode 70.
Specifically, being 200torr-500torr in reaction growth pressure range (including 200torr and 500torr)
Under the conditions of from the substrate 10 successively grow the nitride buffer layer 80, the n type gallium nitride layer 20, the current extending
30, the quantum well layer 40, the protective layer 90, the electronic barrier layer 100, the p-type gallium nitride layer 50, N-type electricity
Pole 60 and the P-type electrode 70.More specifically, the growth step of the semiconductor chip includes: S1, raw from the substrate 10
The long nitride buffer layer 80；S2 grows the n type gallium nitride layer 20 from the nitride buffer layer 80；S3, from the N
Type gallium nitride layer 20 grows the current extending 30；S4 grows the quantum well layer 40 from the current extending 30；S5,
The protective layer 90 is grown from the quantum well layer 40；S6 grows the electronic barrier layer 100 from the protective layer 90；S7, from
The electronic barrier layer 100 grows the p-type gallium nitride layer 50；S8 grows the N-type electrode 60 from the current extending 30
The P-type electrode 70 is grown with from the p-type gallium nitride layer 50.
In the following, each growth course of the above-mentioned preferred embodiment to semiconductor chip according to the present invention is carried out
It is described in detail.
In step S1, the nitride buffer layer 80 is grown from the substrate 10.Specifically, firstly, by the substrate
10 are put into a Metal Organic Vapor epitaxial deposition equipment (Metal-organic Chemical Vapor
Deposition, MOCVD).Secondly, the cavity temperature in the Metal Organic Vapor epitaxial deposition equipment is 1100 DEG C
High-purity hydrogen (H2) is passed through when left and right, wherein the duration range for being passed through high-purity hydrogen (H2) be -15 minutes 10 minutes (including 10 points
Clock and 15 minutes).Third is reduced in the cavity temperature range of the Metal Organic Vapor epitaxial deposition equipment
It is passed through the source Ga and the source N when 900 DEG C -1000 DEG C (including 900 DEG C and 1000 DEG C) and grows the nitride buffer layer 80 in the lining
Bottom 10, so that the nitride buffer layer 80 is laminated in the substrate 10.
Preferably, the nitride buffer layer 80 is non-doped gallium nitride buffer layer.Preferably, the nitride buffer layer
80 thickness range is 20nm-50nm (including 20nm and 50nm).
It is noted that the type of the substrate 10 is unrestricted in the semiconductor chip of the invention, for example,
In a preferable examples of the semiconductor chip of the invention, the substrate 10 can be Sapphire Substrate.
Then, in step S2, the n type gallium nitride layer 20 is grown from the nitride buffer layer 80.Specifically, institute
The cavity temperature range for stating Metal Organic Vapor epitaxial deposition equipment is raised to 1100 DEG C -1200 DEG C (including 1100
DEG C and 1200 DEG C) when be passed through the source Ga, the source N and silane (SiH4), with grow silicon doping the n type gallium nitride layer 20 in the nitrogen
Change gallium buffer layer 80, wherein the source Ga and the source N are carrier gas, and silane (SiH4) is doped source.
Preferably, the thickness range of the n type gallium nitride layer 20 is 3 μm -6 μm (including 3 μm and 6 μm).Preferably,
The doping concentration of the n type gallium nitride layer 20 is 1-10x1018cm-3。
Then, in step S3, the current extending 30 is grown from the n type gallium nitride layer 20.Specifically, firstly,
After the n type gallium nitride layer 20 is grown on the nitride buffer layer 80, continue to the Metal Organic Vapor
Epitaxial deposition equipment is passed through the source Ga, the source N and silane (SiH4), with the N- adulterated from the n type gallium nitride layer 20 growth silicon
GaN layer 31.Secondly, being passed through the source Ga and the source N to the Metal Organic Vapor epitaxial deposition equipment grows undoped institute
U-GaN layer 32 is stated in the N-GaN layer 31, then the layer of N-GaN described in cycling deposition 31 and U-GaN layer 32, cycle period
Range is -30 periods (including 5 periods and 30 periods) of 5 periods, thus the N-GaN layer 31 being layered on top of each other and institute
It states U-GaN layer 32 and forms the current extending 30 for being laminated in the n type gallium nitride layer 20.
Preferably, the number of plies of the N-GaN layer 31 of the current extending 30 than the U-GaN layer 32 the number of plies more than one
Layer, so that a N-GaN layer 31 of the current extending 30 is contacted with the n type gallium nitride layer 20, and makes
Another described N-GaN layer 31 of the current extending 30 is contacted with the quantum well layer 40.For example, described in of the invention
In one preferable examples of semiconductor chip, the current extending 30 includes 6 layers of described 31 and 5 layers of U-GaN of N-GaN layer
Layer 32, and in another preferable examples of the semiconductor chip of the invention, the current extending 30 includes 31 layers of institute
State 31 and 30 layers of the N-GaN layer U-GaN layer 32.In other words, in a preferable examples of the semiconductor chip of the invention
In, when growing the current extending 30, started in the n type gallium nitride layer 20 and with growing the N-GaN layer 31 with life
The long N-GaN layer 31 terminates in the U-GaN layer 32, in this way, can effectively guarantee the semiconductor core
The reliability of piece.
Preferably, the thickness range of the current extending 30 is 0.1 μm -1 μm (including 0.1 μm and 1 μm).It is described
The thickness range of the N-GaN layer 31 of current extending 30 is 5nm-15nm (including 5nm and 15nm), the U-GaN
The thickness range of layer 32 is 5nm-15nm (including 5nm and 15nm).Preferably, the N- of the current extending 30
The doping concentration of GaN layer 31 is 1-5x1018cm-3。
It is noted that although the thickness range of the N-GaN layer 31 of the current extending 30 and described
The thickness range of U-GaN layer 32 is 5nm-15nm, it is not intended that the thickness and the U-GaN of N-GaN layer 31
Thickness it is equal.In a preferable examples of the semiconductor chip of the invention, the N- of the current extending 30
The thickness of the thickness of GaN layer 31 and U-GaN layer 32 can be different, and each N-GaN layer 31 is not according to
Same needs can have different thickness and each U-GaN layer 32 to need it that can have different thickness according to different,
In this way, electric current can be more evenly distributed in the semiconductor chip.
It is understood that the N-GaN layer 31 of the current extending 30 is silicon doped layer, and it is U-GaN layers described
32 be non-doped layer, and therefore, the N-GaN layer 31 and U-GaN layer 32 of the current extending 30 have different electricity
Resistance, so that the current extending 30 can show the electricity of " low-resistance-high resistant-low-resistance-high resistant ... " in short transverse
Resistance state, in this way, on the one hand, the current extending 30 increases the longitudinal electrical resistance of the semiconductor chip
Add, to weaken the longitudinal current extended capability of the semiconductor chip, on the other hand, the current extending 30 makes described
The lateral current ability of semiconductor chip is sufficiently elevated, to be conducive to described in electric current is evenly distributed over and improves
The luminous efficiency of semiconductor chip, this, which has the optical property and service life of the semiconductor chip, largely changes
It is kind.In addition, the thickness of the N-GaN layer 31 and U-GaN layer 32 can influence the N-GaN layer 31 and U-GaN layers described
32 resistance, so that the mode by adjusting the N-GaN layer 31 and the thickness of U-GaN layer 32 enables to electric current
More uniformly it is distributed and improves the luminous efficiency of the semiconductor chip.
Optionally, it in another preferable examples of the semiconductor chip of the invention, grows first U-GaN layers described
32 in the n type gallium nitride layer 20, and secondly N-GaN layer 31 described in regrowth is grown in the U-GaN layer 32 according to such rule
The current extending 30 is formed after -30 periods of 5 periods.
Then, in step S4, the quantum well layer 40 is grown from the current extending 30.Specifically, firstly, institute
State Metal Organic Vapor epitaxial deposition equipment cavity temperature range be reduced to 800 DEG C -900 DEG C (including 800 DEG C and
900 DEG C) when, it is passed through the source In, the source Ga, the source N and silane (SiH4), to grow the InxGa1-xN (0 < X < 1) of the quantum well layer 40
Quantum build in the N-GaN layer 31 of the current extending 30, doping concentration 1-5x1018cm-3.Secondly, described in growth
The undoped InyGa1-yN Quantum Well of quantum well layer 40 is built in the quantum.Preferably, In component ratio quantum is built in Quantum Well
The middle high 0.05-0.1 of In component (including 0.05 and 0.1).Then, cycling deposition quantum is built and Quantum Well, cycle period were 4 week
- 10 periods (including 4 periods and 10 periods) of phase, thus the quantum that is layered on top of each other build and Quantum Well formation be laminated in it is described
The quantum well layer 40 of current extending 30.
Preferably, the quantum well layer 40 each quantum build thickness range be 10nm-12nm (including 10nm and
12nm), the thickness range of each Quantum Well is 3nm-5nm (including 3nm and 5nm).
Then, in step S5, the protective layer 90 is grown from the quantum well layer 40.Specifically, having in the metal
The internal temperature range of machine compound gas phase epitaxial deposition equipment be reduced to 700 DEG C -800 DEG C (including 700 DEG C and 800 DEG C) it
Afterwards, it is passed through the source Ga and the source N to the Metal Organic Vapor epitaxial deposition equipment, to grow the protective layer 90 in described
Quantum well layer 40, so that the protective layer 90 is laminated in the quantum well layer 40.That is, the protective layer 90 is to be laminated in
The low temperature GaN cap of the quantum well layer 40.Preferably, the thickness range of the protective layer 90 is 30nm-100nm (packet
Include 30nm and 100nm).By way of growing the protective layer 90 in the quantum well layer 40, it can be grown subsequent
The crystal quality that the quantum well layer 40 is maintained in journey, avoid subsequent high growth temperature to the component of the quantum well layer 40 and/
Or structural damage.
Then, in step S6, the electronic barrier layer 100 is grown from the protective layer 90.Specifically, in the metal
The internal temperature range of Organic Vapor epitaxial deposition equipment is raised to 900 DEG C -1000 DEG C (including 900 DEG C and 1000
DEG C) after, it is passed through the source Al, the source Ga, the source N and the source Mg, the electronic barrier layer 100 of the AlGaN of growth magnesium doping, wherein adulterating dense
Degree is 1-10x1018cm-3, wherein the source Al, the source Ga and the source N are carrier gas, and the source Mg is doped source.Preferably, the electronic barrier layer
100 thickness range is 0.1 μm -0.5 μm (including 0.1 μm and 0.5 μm).
Then, in step S7, the p-type gallium nitride layer 50 is grown from the electronic barrier layer 100.Specifically, to institute
It states Metal Organic Vapor epitaxial deposition equipment and is passed through the source Ga, the source N and silane (SiH4), to grow the P of silicon doping
Type gallium nitride layer 50 is in the electronic barrier layer 100, and wherein the source Ga and the source N are carrier gas, and silane (SiH4) is doped source.
Preferably, the thickness range of the p-type gallium nitride layer 50 be 100nm-200nm (including 100nm and
200nm).Preferably, the doping concentration of the p-type gallium nitride layer 50 is 5-10x1018cm-3。
In addition, annealing 20 points under nitrogen (N2) atmosphere in 800 DEG C -900 DEG C (including 800 DEG C and 900 DEG C) temperature ranges
Clock -30 minutes (including 20 minutes and 30 minutes), to complete the growth of the semiconductor chip.It is noted that annealing
Before, the N-type electrode 60 is grown in the current extending 30 and grows the P-type electrode 70 in the p-type gallium nitride layer
50。
Other side under this invention, the present invention further provides the manufacturers of the semiconductor chip of a light emitting diode
Method, wherein the manufacturing method includes the following steps:
(f) the n type gallium nitride layer 20 is laminated in the substrate 10；
(g) from N-GaN layer 31 and U-GaN layer 32 described in 20 cycling deposition of n type gallium nitride layer, described in stacking
Current extending 30 is in the n type gallium nitride layer 20；
(h) quantum well layer 40 is laminated in the current extending 30；
(i) the p-type gallium nitride layer 50 is laminated in the quantum well layer 40；And
(j) N-type electrode 60 is electrically connected in the current extending 30 and is electrically connected the P-type electrode 70 in the P
Type gallium nitride layer 50.
Further, further comprise step in the step (b):
(b.1) keep the substrate 10 for being laminated with the n type gallium nitride layer 20 in the Metal Organic Vapor
Epitaxial deposition equipment；
(b.2) source Ga, the source N and silane are passed through in the Metal Organic Vapor epitaxial deposition equipment, to grow silicon
The N-GaN layer 31 of doping is in the n type gallium nitride layer 20；
(b.3) it is passed through the source Ga and N is derived from the Metal Organic Vapor epitaxial deposition equipment, it is undoped to grow
The U-GaN layer 32 is in the N-GaN layer 31；And
(b.4) step (b.2) and the step (b.3) are recycled, the current extending 30 is laminated in the N-type
Gallium nitride layer 20.
Preferably, in the step (b), the cycle period range of the step (b.2) and the step (b.3) is 5
- 30 periods of a period.
It is worth noting that, in the attached drawing of the invention only substrate 10 of the semiconductor chip shown in, described
Nitride buffer layer 80, the n type gallium nitride layer 20, the current extending 30, the quantum well layer 40, the protective layer
90, the thickness of the electronic barrier layer 100, the p-type gallium nitride layer 50, the N-type electrode 60 and the P-type electrode 70 is only
Example is not offered as the substrate 10, the nitride buffer layer 80, the n type gallium nitride layer 20, the current extending
30, the quantum well layer 40, the protective layer 90, the electronic barrier layer 100, the p-type gallium nitride layer 50, N-type electricity
The actual thickness of pole 60 and the P-type electrode 70.Also, the substrate 10, the nitride buffer layer 80, the N-type nitrogenize
Gallium layer 20, the current extending 30, the quantum well layer 40, the protective layer 90, the electronic barrier layer 100, the p-type
Actual proportions between gallium nitride layer 50, the N-type electrode 60 and the P-type electrode 70 are also unlike shown in the accompanying drawings.
Correspondingly, the N-GaN layer 31 of the current extending 30 and the thickness of U-GaN layer 32 are merely illustrative,
Its actual thickness for being not offered as the N-GaN layer 31 and U-GaN layer 32, also, N-GaN layer 31 and the U-
The actual proportions of GaN layer 32 are also unlike shown in the accompanying drawings.
It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments
It can be combined with each other, with the reality that the content disclosed according to the present invention is readily conceivable that but is not explicitly pointed out in the accompanying drawings
Apply mode.
It should be understood by those skilled in the art that foregoing description and the embodiment of the present invention shown in the drawings are only used as illustrating
And it is not intended to limit the present invention.The purpose of the present invention has been fully and effectively achieved.Function and structural principle of the invention exists
It shows and illustrates in embodiment, under without departing from the principle, embodiments of the present invention can have any deformation or modification.
Claims (32)
1. the semiconductor chip of a light emitting diode characterized by comprising
One substrate；
One n type gallium nitride layer, wherein the n type gallium nitride is laminated on the substrate layer by layer；
One current extending, wherein the current extending is laminated in the n type gallium nitride layer, wherein the current extending packet
Include at least a N-GaN layers be layered on top of each other and at least a U-GaN layers；
One quantum well layer, wherein the quantum well layer is laminated in the current extending；
One p-type gallium nitride layer, wherein the p-type gallium nitride layer is laminated in the quantum well layer；
One N-type electrode, wherein the N-type electrode is electrically connected to the current extending；And
One P-type electrode, wherein the P-type electrode is electrically connected to the p-type gallium nitride layer.
2. semiconductor chip according to claim 1, wherein any one of U-GaN layers of the current extending
Two sides are N-GaN layers described, and described N-GaN layers of one of the current extending contacts with the n type gallium nitride layer,
Another described the N-GaN layers of the current extending is contacted with the quantum well layer.
3. semiconductor chip according to claim 2, wherein setting the U-GaN layers of the number of plies ginseng of the current extending
Number is X, and the N-GaN layers of layer number parameter of the current extending is X+1, wherein the value range of parameter X are as follows: 5≤X≤
30。
4. semiconductor chip according to claim 1, wherein described U-GaN layers of one of the current extending is in described
The contact of n type gallium nitride layer, described N-GaN layers of one of the current extending contacts in the quantum well layer.
5. semiconductor chip according to claim 2, wherein the thickness range of the current extending is 0.1 μm -1
μm。
6. semiconductor chip according to claim 3, wherein the thickness range of the current extending is 0.1 μm -1
μm。
7. according to claim 1 to any semiconductor chip in 6, wherein the N-GaN layers of the current extending
Thickness range be 5nm-15nm, described U-GaN layer of thickness range is 5nm-15nm.
8. according to claim 1 to any semiconductor chip in 7, wherein the N-GaN layers of the current extending
For silicon doped layer, wherein doping concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
9. further comprise a nitride buffer layer according to claim 1 to the semiconductor chip any in 8, wherein institute
It states nitride buffer layer and is laminated in the substrate, the n type gallium nitride is laminated on the nitride buffer layer layer by layer.
10. further comprising a protective layer, wherein the protection according to claim 1 to any semiconductor chip in 8
It is laminated on the quantum well layer layer by layer, the p-type gallium nitride layer is laminated in the protective layer.
11. semiconductor chip according to claim 9 further comprises a protective layer, wherein the protective layer is laminated in
The quantum well layer, the p-type gallium nitride layer are laminated in the protective layer.
12. further comprising a protective layer and an electronic blocking according to claim 1 to any semiconductor chip in 8
Layer, wherein the protective layer is laminated in the quantum well layer, the electronic barrier layer is laminated in the protective layer, the p-type nitrogen
Change gallium and is laminated on the electronic barrier layer layer by layer.
13. semiconductor chip according to claim 10 further comprises an electronic barrier layer, wherein the electronic blocking
It is laminated on the quantum well layer layer by layer, the p-type gallium nitride layer is laminated in the electronic barrier layer.
14. semiconductor chip according to claim 11 further comprises an electronic barrier layer, wherein the electronic blocking
It is laminated on the quantum well layer layer by layer, the p-type gallium nitride layer is laminated in the electronic barrier layer.
15. the current extending of semiconductor chip, which is characterized in that including be layered on top of each other a at least N-GaN layers and at least
One U-GaN layers.
16. current extending according to claim 14, wherein any one of U-GaN layers of the current barrier layer
Two sides be N-GaN layers described.
17. current extending according to claim 16, wherein setting the U-GaN layers of the number of plies of the current extending
Parameter is X, and the N-GaN layers of layer number parameter of the current extending is X+1, wherein the value range of parameter X are as follows: 5≤X
≤30。
18. any current extending in 5 to 17 according to claim 1, wherein the thickness of the current extending
Range is 0.1 μm -1 μm.
19. any current extending in 5 to 18 according to claim 1, wherein the N-GaN of the current extending
The thickness range of layer is 5nm-15nm, and described U-GaN layers of thickness range is 5nm-15nm.
20. any current extending in 5 to 19 according to claim 1, wherein the N-GaN of the current extending
Layer is silicon doped layer, and wherein doping concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
21. the manufacturing method of the semiconductor chip of a light emitting diode, which is characterized in that the manufacturing method includes following step
It is rapid:
(a) one n type gallium nitride layer of stacking is in a substrate；
(b) from one N-GaN layers and a U-GaN layers of the n type gallium nitride layer cycling deposition, a current extending is laminated in described
N type gallium nitride layer；
(c) one quantum well layer of stacking is in the current extending；
(d) one p-type gallium nitride layer of stacking is in the quantum well layer；And
(e) one N-type electrode of electrical connection is in the current extending and one P-type electrode of electrical connection in the p-type gallium nitride layer.
22. manufacturing method according to claim 21, wherein further comprising step in the step (b):
(b.1) substrate for being laminated with the n type gallium nitride layer is kept to set in a Metal Organic Vapor epitaxial deposition
It is standby；
(b.2) source Ga, the source N and silane are passed through in the Metal Organic Vapor epitaxial deposition equipment, to grow silicon doping
The N-GaN layers in the n type gallium nitride layer；
(b.3) source Ga and N are passed through derived from the golden Metal Organic Vapor epitaxial deposition equipment, to grow undoped institute
U-GaN layers are stated in N-GaN layers described；And
(b.4) step (b.2) and the step (b.3) are recycled, the current extending is laminated in the n type gallium nitride
Layer.
23. manufacturing method according to claim 21, wherein further comprising step in the step (b):
(b.1) substrate for being laminated with the n type gallium nitride layer is kept to set in a Metal Organic Vapor epitaxial deposition
It is standby；
(b.2) source Ga and N are passed through derived from the golden Metal Organic Vapor epitaxial deposition equipment, to grow undoped institute
U-GaN layers are stated in the n type gallium nitride layer；
(b.3) source Ga, the source N and silane are passed through in the Metal Organic Vapor epitaxial deposition equipment, to grow silicon doping
The N-GaN layers in N-GaN layers described；And
(b.4) step (b.2) and the step (b.3) are recycled, the current extending is laminated in the n type gallium nitride
Layer.
24. manufacturing method according to claim 22, wherein in the step (b), the step (b.2) and the step
Suddenly cycle period range (b.3) is -30 periods of 5 periods.
25. manufacturing method according to claim 23, wherein in the step (b), the step (b.2) and the step
Suddenly cycle period range (b.3) is -30 periods of 5 periods.
26. manufacturing method according to claim 24, wherein setting the U-GaN layers of the number of plies ginseng of the current extending
Number is X, and the N-GaN layers of layer number parameter of the current extending is X+1, wherein the value range of parameter X are as follows: 5≤X≤
30。
27. the manufacturing method according to claim 21 to 26, wherein the thickness range of the current extending is 0.1
μm-1μm。
28. according to the manufacturing method any in claim 20 to 27, wherein the N-GaN layers of the current extending
Thickness range be 5nm-15nm, described U-GaN layer of thickness range is 5nm-15nm.
29. according to the manufacturing method any in claim 20 to 28, wherein the N-GaN layers of the current extending
For silicon doped layer, wherein doping concentration is 1-5x1018cm-3, wherein described U-GaN layers is non-doped layer.
30. according to the manufacturing method any in claim 20 to 29, wherein further comprising in the step (a)
Step: a nitride buffer layer is grown first in the substrate, n type gallium nitride layer described in secondary growth is buffered in the gallium nitride
Layer, so that the n type gallium nitride is laminated on the substrate layer by layer.
31. according to the manufacturing method any in claim 20 to 29, wherein before the step (d), the manufacture
Method is into one comprising steps of growing a protective layer first in the quantum well layer, one electronic barrier layer of secondary growth is in described
Protective layer grows the p-type gallium nitride layer in the electronic barrier layer, so that the p-type nitrogen then in the step (d)
Change gallium and is laminated on the quantum well layer layer by layer.
32. manufacturing method according to claim 30, wherein the manufacturing method is into one before the step (d)
Comprising steps of growing a protective layer first in the quantum well layer, one electronic barrier layer of secondary growth is in the protective layer, then
In the step (d), the p-type gallium nitride layer is grown in the electronic barrier layer, so that the p-type gallium nitride layer is laminated in
The quantum well layer.
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| CN112652686A (en) * | 2021-01-04 | 2021-04-13 | 厦门乾照光电股份有限公司 | Large-size LED chip and manufacturing method thereof |
| CN112652686B (en) * | 2021-01-04 | 2022-01-28 | 厦门乾照光电股份有限公司 | Large-size LED chip and manufacturing method thereof |
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