CN112652686A - Large-size LED chip and manufacturing method thereof - Google Patents
Large-size LED chip and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 90
- 239000002131 composite material Substances 0.000 claims abstract description 36
- 238000003892 spreading Methods 0.000 claims abstract description 30
- 230000007480 spreading Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000005641 tunneling Effects 0.000 claims abstract description 25
- 238000003475 lamination Methods 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 28
- 230000009286 beneficial effect Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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Abstract
The invention provides a large-size LED chip and a manufacturing method thereof.A tunneling junction and a plurality of current expansion composite layers are arranged on the surface of one side of an epitaxial lamination layer, which is far away from a substrate, wherein the current expansion composite layers are laminated on the surface of one side of the tunneling junction, which is far away from the epitaxial lamination layer, and each current expansion composite layer comprises a second N-type semiconductor layer and an ohmic contact layer which are sequentially laminated along a first direction; the current spreading composite layer is provided with a first through hole which penetrates from the ohmic contact layer on the top layer to a part of the first N-type semiconductor layer and exposes a part of the surface of the first N-type semiconductor layer; and forming a tunneling effect between the P-type semiconductor layer and the second N-type semiconductor layer at the bottommost layer. Therefore, the transparent conducting layer with the traditional structure is replaced by the epitaxial material layer (namely the N-type semiconductor layer), and the stable and reliable chip structure can be better realized while the current expansion effect of the chip structure is ensured.
Description
Technical Field
The invention relates to the field of light emitting diodes, in particular to a large-size LED chip and a manufacturing method thereof.
Background
With the rapid development of light emitting diodes, the application of LEDs is changing day by day; the market demand for light emitting power of light emitting diodes is higher and higher, so that the size of an LED chip is larger and larger. Meanwhile, the LED chip structure is continuously improved and optimized due to the problem that the large-size chip has poor current expansion effect; at present, a large-sized chip generally adopts an extended electrode structure combined with a transparent conductive layer, and the transparent conductive layer (such as conductive metal oxide like ITO) is used as a P-type ohmic contact layer, so that current can be better extended in the large-area chip.
However, although the transparent conductive layer has a high light transmittance after high-temperature fusion, the transparent conductive layer still has a certain loss, which cannot reach 100%, and is not beneficial to improving the brightness of the chip; meanwhile, if the transparent conductive layer is not used as an ohmic contact layer, ohmic contact of the P-type semiconductor layer is difficult to realize.
In view of the above, the present inventors have specially designed a large-sized LED chip and a method for manufacturing the same, and have resulted in the present invention.
Disclosure of Invention
The invention aims to provide a large-size LED chip and a manufacturing method thereof, and aims to solve the problems that a P-type semiconductor layer in the large-size LED chip cannot be thickened and a transparent conducting layer loses light.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a large-sized LED chip comprising:
a substrate;
the epitaxial lamination layer is positioned on the surface of the substrate and at least comprises a first N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked along a first direction; the first direction is perpendicular to the substrate and directed from the substrate to the epitaxial stack;
the tunneling junction is arranged on the surface of one side, away from the substrate, of the epitaxial laminated layer;
the current spreading composite layers are stacked on the surface of one side, away from the epitaxial stacked layer, of the tunneling junction, and each current spreading composite layer comprises a second N-type semiconductor layer and an ohmic contact layer which are sequentially stacked along a first direction;
the first through hole penetrates through the first N-type semiconductor layer from the ohmic contact layer on the top layer to a part of the first N-type semiconductor layer, and exposes a part of the surface of the first N-type semiconductor layer;
an insulating layer attached to a sidewall of the first via;
an N-type electrode stacked on an exposed portion of the first N-type semiconductor layer so as to be held in the first through hole, and separated from the remaining layers by the insulating layer;
and the P-type electrode is laminated on the surface of the ohmic contact layer of the top layer.
Preferably, a current diffusion layer is arranged between two adjacent current spreading composite layers.
Preferably, the current diffusion layer includes at least one N-GaN layer and at least one U-GaN layer stacked one on another.
Preferably, both sides of any one of the U-GaN layers are the N-GaN layers.
Preferably, the N-type electrode further comprises at least one N-type extension electrode;
the first through hole is provided with a plurality of first grooves which extend horizontally and expose the first N-type semiconductor layer, and the side wall of each first groove is provided with an insulating layer; the N-type extension electrode is stacked on the first N-type semiconductor layer so as to be held in the first trench; wherein the N extension electrode is electrically connected to the N-type electrode.
Preferably, the P-type electrode further comprises at least one P-type extension electrode;
the P-type extended electrode is stacked on the surface of the ohmic contact layer on the top layer and partially extends downwards to the ohmic contact layer on the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode.
Preferably, the number of groups of the current spreading composite layers is 1-5 groups, inclusive.
Preferably, the tunneling junction comprises a P-type high-doping layer and an N-type high-doping layer which are sequentially stacked along the first direction, so that a tunneling effect is formed between the P-type semiconductor layer and the second N-type semiconductor layer at the bottommost layer.
The invention also provides a manufacturing method of the large-size LED chip, which comprises the following steps:
step S01, providing a substrate;
step S02, stacking an epitaxial lamination on the surface of the substrate, wherein the epitaxial lamination at least comprises a first N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked along the growth direction;
step S03, laminating a tunnel junction on the surface of the epitaxial lamination;
step S04, laminating a plurality of current spreading composite layers on the surface of the tunnel junction; the current spreading composite layer comprises a second N-type semiconductor layer and an ohmic contact layer which are sequentially stacked along the growth direction;
further, a current diffusion layer can be grown between two adjacent current spreading composite layers;
step S05, etching a local region of the structure formed in step S04 to a portion of the first N-type semiconductor layer, forming a first via and a mesa;
step S06, growing an insulating layer, wherein the insulating layer is attached to the side wall of the first through hole;
step S07 of depositing and forming an N-type electrode and a P-type electrode, wherein the N-type electrode is stacked on the exposed portion of the first N-type semiconductor layer in a manner of being held in the first via hole, and is separated from the rest layers by the insulating layer;
the P-type electrode is laminated on the surface of the ohmic contact layer of the mesa.
Preferably, the current diffusion layer includes at least one N-GaN layer and at least one U-GaN layer stacked on each other, and both sides of any one of the U-GaN layers are the N-GaN layers.
Preferably, the N-type electrode further comprises at least one N-type extension electrode, and the P-type electrode further comprises at least one P-type extension electrode;
the first through hole is provided with a plurality of first grooves which extend horizontally and expose the first N-type semiconductor layer, and the side wall of each first groove is provided with an insulating layer; the N-type extension electrode is stacked on the first N-type semiconductor layer so as to be held in the first trench; wherein the N extension electrode is electrically connected to the N-type electrode;
the P-type extended electrode is stacked on the surface of the ohmic contact layer on the top layer and partially extends downwards to the ohmic contact layer on the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode.
According to the technical scheme, the large-size LED chip provided by the invention has the advantages that the tunneling junction and the current expansion composite layers are arranged on the surface of one side, away from the substrate, of the epitaxial lamination layer, wherein the current expansion composite layers are laminated on the surface of one side, away from the epitaxial lamination layer, of the tunneling junction, and each current expansion composite layer comprises the second N-type semiconductor layer and the ohmic contact layer which are sequentially laminated along the first direction; the current spreading composite layer is provided with a first through hole which penetrates from the ohmic contact layer on the top layer to a part of the first N-type semiconductor layer and exposes a part of the surface of the first N-type semiconductor layer; and forming a tunneling effect between the P-type semiconductor layer and the second N-type semiconductor layer at the bottommost layer. Further, the tunneling junction comprises a P-type high-doping layer and an N-type high-doping layer which are sequentially stacked along the first direction, so that a tunneling effect is formed between the P-type semiconductor layer and the second N-type semiconductor layer at the bottommost layer. Therefore, the transparent conducting layer with the traditional structure is replaced by the epitaxial material layer (namely the N-type semiconductor layer), and the stable and reliable chip structure can be better realized while the current expansion effect of the chip structure is ensured.
Secondly, a current diffusion layer is arranged between two adjacent current expansion composite layers, and further comprises at least one N-GaN layer and at least one U-GaN layer which are mutually laminated, the N-GaN layers are arranged on two sides of any one U-GaN layer, so that the resistance of the current diffusion layer is in a low-resistance/high-resistance … … low-resistance state along the longitudinal direction, on the basis of the structure, on one hand, the longitudinal resistance can be increased, the over-strong longitudinal expansion current is weakened, the Auger recombination and non-radiative recombination output are reduced, on the other hand, the transverse current expansion is greatly enhanced, the whole current distribution is more uniform, and the luminous efficiency is higher; therefore, the service life and the performance of the chip can be well improved, and the effect is extremely obvious particularly in the application background of the large-size LED chip.
Then, by setting: the N-type electrode further comprises at least one N-type extension electrode, and the P-type electrode further comprises at least one P-type extension electrode; the first through hole is provided with a plurality of first grooves which extend horizontally and expose the first N-type semiconductor layer, and the side wall of each first groove is provided with an insulating layer; the N-type extension electrode is stacked on the first N-type semiconductor layer so as to be held in the first trench; wherein the N extension electrode is electrically connected to the N-type electrode; the P-type extended electrode is stacked on the surface of the ohmic contact layer on the top layer and partially extends downwards to the ohmic contact layer on the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode. The transverse expansion and the longitudinal uniform distribution of the current can be further ensured.
According to the technical scheme, the manufacturing method of the large-size LED chip provided by the invention has the beneficial effects that the manufacturing process is simple and convenient, and the production is convenient while the beneficial effects of the large-size LED chip are realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a large-sized LED chip according to an embodiment of the present invention;
fig. 2 is a schematic top view of a large-sized LED chip according to an embodiment of the present invention;
fig. 3.1 to fig. 3.7 are schematic structural diagrams corresponding to steps of a method for manufacturing a large-sized LED chip according to an embodiment of the present invention;
fig. 4 is a schematic top view of the structure after step S06 is performed in the method for manufacturing a large-sized LED chip according to the embodiment of the invention;
the symbols in the drawings illustrate that: 1. the epitaxial structure comprises a substrate, 2, an epitaxial lamination layer, 2.1, a first N-type semiconductor layer, 2.2, an active layer, 2.3, a P-type semiconductor layer, 3, a tunneling junction, 4, a current expansion composite layer, 4.1, a second N-type semiconductor layer, 4.2, an ohmic contact layer, 5, a current diffusion layer, L1, a table top, L2, a first through hole, L2.1, a first groove, 6, an insulating layer, 7, a P-type electrode, 7.1, a P-type expansion electrode, 8, an N-type electrode, 8.1 and an N-type expansion electrode.
Detailed Description
In order to make the content of the present invention clearer, the content of the present invention is further explained below with reference to the attached drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a large-sized LED chip includes:
a substrate 1;
the epitaxial lamination layer 2 is positioned on the surface of the substrate 1, and the epitaxial lamination layer 2 at least comprises a first N-type semiconductor layer 2.1, an active layer 2.2 and a P-type semiconductor layer 2.3 which are sequentially stacked along a first direction; the first direction is perpendicular to the substrate 1 and directed from the substrate 1 to the epitaxial stack 2;
the tunneling junction 3 is arranged on the surface of one side, away from the substrate 1, of the epitaxial laminated layer 2;
the current spreading composite layers 4 are stacked on the surface of one side, away from the epitaxial stacked layer 2, of the tunneling junction 3, and each current spreading composite layer 4 comprises a second N-type semiconductor layer 4.1 and an ohmic contact layer 4.2 which are sequentially stacked along a first direction;
a first via L2, wherein the first via L2 penetrates from the top ohmic contact layer 4.2 to a part of the first N-type semiconductor layer 2.1, and exposes a part of the surface of the first N-type semiconductor layer 2.1;
an insulating layer 6, the insulating layer 6 being attached to a sidewall of the first via L2;
an N-type electrode 8 laminated on an exposed portion of the first N-type semiconductor layer 2.1 so as to be held in the first via hole L2, and separated from the remaining layers by an insulating layer 6;
and the P-type electrode 7 is laminated on the surface of the ohmic contact layer 4.2 on the top layer.
In other embodiments of the present invention, the epitaxial stack 2 may further include a buffer layer, a first N-type semiconductor layer 2.1, an active layer 2.2, and a P-type semiconductor layer 2.3 stacked in sequence along the first direction.
It is worth mentioning that the type of the substrate 1 is not limited in the large-sized LED chip of the present embodiment, for example, the substrate 1 may be, but is not limited to, a sapphire substrate 1, a silicon substrate 1, or the like. In addition, the specific material types of the first N-type semiconductor layer 2.1, the active layer 2.2 and the P-type semiconductor layer 2.3 of the epitaxial stack 2 may also be not limited in the large-sized LED chip of the present embodiment, for example, the first N-type semiconductor layer 2.1 may be, but is not limited to, a gallium nitride layer, and correspondingly, the P-type semiconductor layer 2.3 may be, but is not limited to, a gallium nitride layer.
In the embodiment of the invention, a current diffusion layer 5 is arranged between two adjacent current spreading composite layers 4.
In the embodiment of the present invention, the current diffusion layer 5 includes at least one N-GaN layer and at least one U-GaN layer stacked one on another.
In the embodiment of the invention, both sides of any one U-GaN layer are N-GaN layers.
In other embodiments of the present invention, a parameter of the number of layers of the U-GaN layer of the current diffusion layer is X, and a parameter of the number of layers of the N-GaN layer of the current diffusion layer is X +1, where a value range of the parameter X is: x is more than or equal to 1 and less than or equal to 30.
In the embodiment of the present invention, as shown in fig. 2, the N-type electrode 8 further includes at least one N-type extension electrode 8.1;
as shown in fig. 4, the first via L2 has a plurality of first trenches L2.1 extending horizontally and exposing the first N-type semiconductor layer 2.1, and the sidewalls of the first trenches have insulating layers 6; the N-type extension electrode 8.1 is laminated on the first N-type semiconductor layer 2.1 so as to be held in the first trench L2.1; wherein the N extension electrode is electrically connected to the N-type electrode 8.
In the embodiment of the present invention, as shown in fig. 2, the P-type electrode 7 further includes at least one P-type extension electrode 7.1;
the P-type extension electrode 7.1 is laminated on the surface of the ohmic contact layer 4.2 at the top layer and partially extends downwards to the ohmic contact layer 4.2 at the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode 7.
In the embodiment of the invention, the number of the groups of the current spreading composite layers 4 is 1-5 groups including endpoint values.
In the embodiment of the invention, the tunneling junction 3 includes a P-type high-doped layer and an N-type high-doped layer stacked in sequence along the first direction, so that a tunneling effect is formed between the P-type semiconductor layer 2.3 and the second N-type semiconductor layer 4.1 at the bottom layer.
The embodiment of the invention also provides a manufacturing method of the large-size LED chip, which comprises the following steps as shown in fig. 3.1 to 3.7:
step S01, as shown in fig. 3.1, providing a substrate 1;
step S02, as shown in fig. 3.2, stacking an epitaxial stack 2 on the surface of the substrate 1, where the epitaxial stack 2 at least includes a first N-type semiconductor layer 2.1, an active layer 2.2, and a P-type semiconductor layer 2.3 stacked in sequence along the growth direction;
step S03, as shown in fig. 3.3, a tunnel junction 3 is stacked on the surface of the epitaxial stack 2;
step S04, as shown in fig. 3.4, stacking a plurality of current spreading composite layers 4 on the surface of the tunnel junction 3; the current spreading composite layer 4 comprises a second N-type semiconductor layer 4.1 and an ohmic contact layer 4.2 which are sequentially stacked along the growth direction;
further, a current diffusion layer 5 can be grown between two adjacent current spreading composite layers 4;
step S05, as shown in fig. 3.5, etching the local region of the structure formed in step S04 to a portion of the first N-type semiconductor layer 2.1, forming a first via L2 and a mesa L1;
step S06, as shown in fig. 3.6, growing an insulating layer 6, the insulating layer 6 being attached to the sidewall of the first via L2;
step S07, as shown in fig. 3.7, depositing to form an N-type electrode 8 and a P-type electrode 7, wherein the N-type electrode 8 is stacked on the exposed portion of the first N-type semiconductor layer 2.1 in such a manner as to be held in the first via hole L2, and is separated from the rest of the layers by the insulating layer 6;
the P-type electrode 7 is laminated on the surface of the ohmic contact layer 4.2 of the mesa L1.
In the embodiment of the present invention, the current diffusion layer 5 includes at least one N-GaN layer and at least one U-GaN layer stacked on each other, and both sides of any one U-GaN layer are N-GaN layers.
In the embodiment of the present invention, the N-type electrode 8 further includes at least one N-type extension electrode 8.1, and the P-type electrode 7 further includes at least one P-type extension electrode 7.1;
as shown in fig. 4, the first via L2 has a plurality of first trenches L2.1 extending horizontally and exposing the first N-type semiconductor layer 2.1, and the sidewalls of the first trenches L2.1 have insulating layers 6; the N-type extension electrode 8.1 is laminated on the first N-type semiconductor layer 2.1 so as to be held in the first trench L2.1; wherein, the N-type extension electrode is electrically connected with the N-type electrode 8;
the P-type extension electrode 7.1 is laminated on the surface of the ohmic contact layer 4.2 at the top layer and partially extends downwards to the ohmic contact layer 4.2 at the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode 7.
It should be noted that, in the embodiment of the present invention, the first trench L2.1 and the first via L2 may be etched simultaneously; similarly, the N-type extension electrode 8.1 and the N-type electrode 8 can be deposited simultaneously. It should be noted that the N-type extension electrode 8.1 may completely fill the first trench L2.1, and at this time, the surface of the N-type extension electrode 8.1 is partially exposed and isolated from the rest layers by the insulating layer 6; or, the N-type extension electrode 8.1 may partially fill the first trench L2.1, and the insulating layer 6 covers the N-type extension electrode 8.1, so that the N-type extension electrode 8.1 is embedded in the first trench L2.1 and connected to the N-type electrode 8.
According to the technical scheme, the tunneling junction 3 and the plurality of current spreading composite layers 4 are arranged on the surface of one side, away from the substrate 1, of the epitaxial stacked layer 2, wherein the current spreading composite layers 4 are stacked on the surface of one side, away from the epitaxial stacked layer 2, of the tunneling junction 3, and each current spreading composite layer 4 comprises the second N-type semiconductor layer 4.1 and the ohmic contact layer 4.2 which are sequentially stacked along the first direction; the current spreading composite layer 4 has a first via L2, the first via L2 penetrates from the top ohmic contact layer 4.2 to a part of the first N-type semiconductor layer 2.1, and exposes a part of the surface of the first N-type semiconductor layer 2.1; so that a tunneling effect is formed between the P-type semiconductor layer 2.3 and the second N-type semiconductor layer 4.1 at the bottom. Further, the tunnel junction 3 includes a P-type highly doped layer and an N-type highly doped layer stacked in sequence along the first direction, so that a tunneling effect is formed between the P-type semiconductor layer 2.3 and the second N-type semiconductor layer 4.1 at the bottom layer. Therefore, the transparent conducting layer with the traditional structure is replaced by the epitaxial material layer (namely the N-type semiconductor layer), and the stable and reliable chip structure can be better realized while the current expansion effect of the chip structure is ensured.
Secondly, a current diffusion layer 5 is arranged between two adjacent current expansion composite layers 4, and further the current diffusion layer 5 comprises at least one N-GaN layer and at least one U-GaN layer which are mutually laminated, and the N-GaN layers are arranged on two sides of any one U-GaN layer, so that the resistance of the current diffusion layer 5 is in a low-resistance/high-resistance … … low-resistance state along the longitudinal direction; therefore, the service life and the performance of the chip can be well improved, and the effect is extremely obvious particularly in the application background of the large-size LED chip.
Then, by setting: the N-type electrode 8 further comprises at least one N-type extension electrode 8.1, and the P-type electrode 7 further comprises at least one P-type extension electrode 7.1; the first through hole L2 is provided with a plurality of first trenches L2.1 extending horizontally and exposing the first N-type semiconductor layer 2.1, and the side walls of the first trenches L2.1 are provided with insulating layers 6; the N-type extension electrode 8.1 is laminated on the first N-type semiconductor layer 2.1 so as to be held in the first trench L2.1; wherein, the N-type extension electrode is electrically connected with the N-type electrode 8; the P-type extension electrode 7.1 is laminated on the surface of the ohmic contact layer 4.2 at the top layer and partially extends downwards to the ohmic contact layer 4.2 at the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode 7. The transverse expansion and the longitudinal uniform distribution of the current can be further ensured.
According to the technical scheme, the manufacturing method of the large-size LED chip provided by the invention has the beneficial effects that the manufacturing process is simple and convenient, and the production is convenient while the beneficial effects of the large-size LED chip are realized.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. A large-sized LED chip, comprising:
a substrate;
the epitaxial lamination layer is positioned on the surface of the substrate and at least comprises a first N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked along a first direction; the first direction is perpendicular to the substrate and directed from the substrate to the epitaxial stack;
the tunneling junction is arranged on the surface of one side, away from the substrate, of the epitaxial laminated layer;
the current spreading composite layers are stacked on the surface of one side, away from the epitaxial stacked layer, of the tunneling junction, and each current spreading composite layer comprises a second N-type semiconductor layer and an ohmic contact layer which are sequentially stacked along a first direction;
the first through hole penetrates through the first N-type semiconductor layer from the ohmic contact layer on the top layer to a part of the first N-type semiconductor layer, and exposes a part of the surface of the first N-type semiconductor layer;
an insulating layer attached to a sidewall of the first via;
an N-type electrode stacked on an exposed portion of the first N-type semiconductor layer so as to be held in the first through hole, and separated from the remaining layers by the insulating layer;
and the P-type electrode is laminated on the surface of the ohmic contact layer of the top layer.
2. The large-sized LED chip according to claim 1, wherein a current spreading layer is disposed between two adjacent current spreading composite layers.
3. The large-sized LED chip according to claim 2, wherein the current spreading layer comprises at least one N-GaN layer and at least one U-GaN layer stacked on each other.
4. The large-sized LED chip according to claim 3, wherein both sides of any one of the U-GaN layers are the N-GaN layers.
5. The large-sized LED chip according to claim 1, wherein the N-type electrode further comprises at least one N-type extension electrode;
the first through hole is provided with a plurality of first grooves which extend horizontally and expose the first N-type semiconductor layer, and the side wall of each first groove is provided with an insulating layer; the N-type extension electrode is stacked on the first N-type semiconductor layer so as to be held in the first trench; wherein the N extension electrode is electrically connected to the N-type electrode.
6. The large-sized LED chip according to claim 1, wherein the P-type electrode further comprises at least one P-type extension electrode;
the P-type extended electrode is stacked on the surface of the ohmic contact layer on the top layer and partially extends downwards to the ohmic contact layer on the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode.
7. The large-sized LED chip according to claim 1, wherein the number of groups of the current spreading composite layer is 1-5 groups, inclusive.
8. The large-sized LED chip according to claim 1, wherein the tunneling junction comprises a P-type highly doped layer and an N-type highly doped layer stacked in sequence along the first direction, so that a tunneling effect is formed between the P-type semiconductor layer and a second N-type semiconductor layer at the lowest layer.
9. A manufacturing method of a large-size LED chip is characterized by comprising the following steps:
step S01, providing a substrate;
step S02, stacking an epitaxial lamination on the surface of the substrate, wherein the epitaxial lamination at least comprises a first N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked along the growth direction;
step S03, laminating a tunnel junction on the surface of the epitaxial lamination;
step S04, laminating a plurality of current spreading composite layers on the surface of the tunnel junction; the current spreading composite layer comprises a second N-type semiconductor layer and an ohmic contact layer which are sequentially stacked along the growth direction;
further, a current diffusion layer can be grown between two adjacent current spreading composite layers;
step S05, etching a local region of the structure formed in step S04 to a portion of the first N-type semiconductor layer, forming a first via and a mesa;
step S06, growing an insulating layer, wherein the insulating layer is attached to the side wall of the first through hole;
step S07 of depositing and forming an N-type electrode and a P-type electrode, wherein the N-type electrode is stacked on the exposed portion of the first N-type semiconductor layer in a manner of being held in the first via hole, and is separated from the rest layers by the insulating layer;
the P-type electrode is laminated on the surface of the ohmic contact layer of the mesa.
10. The method according to claim 9, wherein the current spreading layer comprises at least one N-GaN layer and at least one U-GaN layer stacked on each other, and both sides of any one of the U-GaN layers are the N-GaN layers.
11. The method of claim 9, wherein the N-type electrode further comprises at least one N-type extension electrode, and the P-type electrode further comprises at least one P-type extension electrode;
the first through hole is provided with a plurality of first grooves which extend horizontally and expose the first N-type semiconductor layer, and the side wall of each first groove is provided with an insulating layer; the N-type extension electrode is stacked on the first N-type semiconductor layer so as to be held in the first trench; wherein the N extension electrode is electrically connected to the N-type electrode;
the P-type extended electrode is stacked on the surface of the ohmic contact layer on the top layer and partially extends downwards to the ohmic contact layer on the bottom layer; wherein the P extension electrode is electrically connected to the P type electrode.
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