CN109037065A - 半导体器件及其制造方法 - Google Patents
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Abstract
本申请提出了一种半导体器件及其制造方法,包括:在第一衬底上依次生长缓冲层和势垒层;在所述势垒层上生长源极、漏极和第一栅极,形成第一结构;在所述第一结构上生长介质层;将所述介质层与第二衬底键合,并去除所述第一衬底,形成第二结构;将所述第二结构倒置,并对所述缓冲层进行减薄处理;在减薄后的缓冲层上生长第二栅极。本申请所提出的半导体器件及其制造方法,减小了背栅与二维电子气之间的距离,增强对沟道的控制能力;并且可以将低成本,高质量的外延薄膜转移到高导热性衬底上以满足功率器件对散热的要求;或者将外延薄膜从难以做背通孔工艺的衬底转移到易于做该工艺的衬底上,满足微波器件对接地的要求。
Description
技术领域
本发明涉及半导体制造技术领域,特别是涉及一种半导体器件及其制造方法。
背景技术
以砷化镓(GaAs)、氮化镓(GaN)为代表的化合物半导体材料具有许多优良的特性,如高临界击穿电场、高电子迁移率、高二维电子气浓度和良好的高温工作能力等。基于化合物半导体的高电子迁移率晶体管(HEMT)、异质结构场效应晶体管(HFET)等器件已经得到了广泛应用,尤其在射频、微波等需要大功率和高频率的领域具有明显优势。
背栅结构的化合物半导体是在传统的源、漏、栅三极化合物半导体的基础上,在导电沟道的背面增加一个栅极,此栅极通常被称为背栅。在两个栅极的同时控制下,导电沟道可以被很好的控制,从而降低漏电或者增加对沟道电流的调制能力。但是,在化合物半导体领域,一直没有合适的工艺来实现背栅结构,仅有的学术文献报道采用的是各向异性的深硅刻蚀来局部去除衬底,但这种方法仅仅适用于硅基的氮化镓器件,而且制造的背栅结构距离导电沟道太远,对沟道的控制作用较弱。
发明内容
基于此,有必要针对背栅对沟道控制作用较弱的问题,提供一种新的器件结构及其制造方法。
本申请提出了一种半导体器件制造方法,包括:
在第一衬底上依次生长缓冲层和势垒层;
在所述势垒层上生长源极、漏极和第一栅极,形成第一结构;
在所述第一结构上生长介质层;
将所述介质层与第二衬底键合,并去除所述第一衬底,形成第二结构;
将所述第二结构倒置,并对所述缓冲层进行减薄处理;
在减薄后的缓冲层上生长第二栅极。
在一个实施例中,对所述缓冲层进行减薄处理之后,生长第二栅极之前,在所述减薄后的缓冲层上生长介电层。
在一个实施例中,所述介电层的厚度为1nm-10nm。
在一个实施例中,将所述介质层与第二衬底键合之前,在所述介质层上形成键合层。
在一个实施例中,减薄前缓冲层厚度大于1um,减薄后缓冲层为20nm-100nm。
在一个实施例中,所述第二栅极与所述第一栅极对准。
相应的,本申请还提出一种半导体器件,采用上述任意项所述的半导体制造方法制备而成。
本申请所提出的半导体器件及其制造方法,减小了背栅与二维电子气之间的距离,增强对沟道的控制能力;并且可以将低成本,高质量的外延薄膜转移到高导热性衬底上以满足功率器件对散热的要求;或者将外延薄膜从难以做背通孔工艺的衬底转移到易于做该工艺的衬底上,满足微波器件对接地的要求。
附图说明
图1为本发明所提出的半导体制造方法的流程图;
图2-图7表示制备根据本发明的一些实施例的半导体器件的示意图;
图8为本发明所提出的半导体器件的结构图。
具体实施方式
以下结合附图和具体实施例对本发明提出的半导体器件及其制造方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1-图7,本实施例提出一种半导体器件制造方法,包括:
S10:第一衬底1上依次生长缓冲层2和势垒层3。
其中,所述第一衬底1材料可以为蓝宝石、硅、碳化硅等,所述第一衬底1的厚度在300um以上。所述缓冲层2靠近所述势垒层3一端的表面形成二维电子气(2DEG),所述2DEG具有高电子密度和高电子迁移率,从而形成导电沟道。所述缓冲层2是氮化镓高质量晶体,所述势垒层3可以为铝镓氮、铟铝氮等三五族化合物半导体合金。所述缓冲层2的厚度大于1um,所述势垒层3的厚度为10nm-50nm。所述第一衬底1、缓冲层2和势垒层3形成的结构如图2所示。
S20:在所述势垒层3上生长所述源极4、漏极5和第一栅极6。
在所述势垒层3上的欧姆接触区生长源极和漏极,使源极4和漏极5与所述势垒层3产生欧姆接触,所述源极4和漏极5通过二维电子气导通。所述第一栅极6生长在所述势垒层3上的非欧姆接触区,与所述势垒层3形成肖特基接触,形成如图3所示的结构。生长所述源极4、漏极5和第一栅极6的包括光刻、金属蒸镀、清洗和快速退火等工艺。可以理解是,上述工艺为本领域的公知常识,此处不再进行具体的阐述。所述非欧姆接触区位于所述欧姆接触区的中间,从而第一栅极6位于所述源极4和漏极5之间。所述第一栅极6可以为镍、金、铂等构成的金属叠层,所述源极4和漏极5可以为钛、铝、镍、金、钨等材料中任意多种组成的合金。所述缓冲层2、势垒层3、源极4、漏极5和第一栅极6组成第一结构。
S30:在所述第一结构上生长介质层7。
其中,在所述源极4、漏极5和第一栅极6制作完成后,需要在覆盖一层介质层7用来保护电极,所述介质层7覆盖住第一结构的表面,即将源极4、漏极5、第一栅极6和势垒层3全部覆盖。覆盖完成后,对所述介质层7表面进行研磨抛光工艺,使介质层7表面平坦化,形成如图4所示的结构。所述介质层7可以为氮化硅或者二氧化硅等绝缘材料。
S40:将所述介质层7与第二衬底8键合,并去除所述第一衬底1。
所述介质层7形成后,选取另外一块衬底晶圆,即第二衬底8,将所述第二衬底8与所述介质层7键合。所述第二衬底8的材料可以是与第一衬底1相同的材料,也可以与第二衬底8不同,例如氮化铝、碳化硅、陶瓷、石英、金属基板等。键合的方法可以有多种,例如范德华力键合、有机薄膜键合、合金键合、金属热压键合等,具体选择何种键合方法需要根据具体的所述第二衬底8材料的物理特性特别是热膨胀特性,以及器件的工作温度而定。为了更好使第二衬底8与介质层7键合,可以在第二衬底8与第一结构之间先形成一层键合层,从而将第二衬底8与介质层7结合在一起。所述键合层材料可以是二氧化硅、氧化铝、聚四氟乙烯、环氧树脂、苯并环丁烯、基础树脂高聚物、金、铜、银、锡、硅或铟等材料中的任意一种。
待所述第二衬底8与所述介质层7键合后,去除所述第一衬底1。针对不同的衬底材料,使用的去除工艺也有很大不同。例如对于蓝宝石晶圆,蓝宝石衬底可以使用激光扫描剥离技术。对于硅基的晶圆,硅衬底可以使用研磨后再加干法刻蚀去除。去除衬底后形成的结构如图5所示。在所述第一结构的基础上去除第一衬底并键合第二衬底所形成的结构称为第二结构。
S50:将所述第二结构倒置,并对所述缓冲层2进行减薄处理。
原先的第二结构是缓冲层2位于底端,第二衬底8位于顶端。倒置后的结果是缓冲层2位于顶端,第二衬底8位于底端。经过上述的第二衬底7键合、第一衬底1去除后和倒置第二结构后,原先的外延结构和制作好的电极被转移到了新的晶圆上,第二衬底8作为支撑衬底,在此基础上可以继续后续的制造工艺。所述缓冲层2位于顶端后,需要对所述缓冲层2进行减薄处理。减薄处理可以采用刻蚀、研磨等工艺,具体工艺条件需要根据所述缓冲层2的材料结构而定。减薄后的缓冲层2的厚度为20nm-100nm,形成如图6所示的结构。
S60:在减薄后的缓冲层2上生长第二栅极9。
缓冲层减薄后,在所述缓冲层2上生长第二栅极9,所述生长第二栅极9的工艺包括光刻、蒸镀、清洗等步骤。所述第二栅极9可以为镍、金、铂等构成的金属叠层。并且,为了使第一栅极6与第二栅极9能够同时控制沟道的导通或者截断,所述第二栅极9需要与第一栅极6对准,由于减薄以后的缓冲层、势垒层厚度很薄,常用的光刻对准技术可以透视材料,对第二栅极的金属层进行套刻,最终形成如图7所示的结构。此外,在其它实施例中,在缓冲层减薄之后,第二栅极生长之前,在减薄后的缓冲层上生长介电层,以减少第二栅极的漏电流。所述介电层的厚度为1-10nm,材料可以是氮化硅或者二氧化硅。
本申请所提供的半导体器件制造方法实现了双栅结构,两个栅极与器件沟道里二维电子气之间的距离很小,相比于传统的共面单栅极晶体管,其增强了对导电沟道的控制能力。两个栅极如果简单的施加同一控制信号,相比于传统的单栅极晶体管,也可以从两个表面同步截断沟道,因此可以降低漏电,改善晶体管截断特性。两个栅极还可以施加不同的控制信号,例如一个栅极做直流偏置,另一个栅极上施加脉冲控制信号,这样直流偏置可以预截断沟道,然后由脉冲信号来开启,从而实现了增强型HEMT器件,大大拓宽了化合物半导体器件在功率器件领域的应用。
此外本申请采用晶圆键合技术转移材料,可以充分利用两种衬底材料的优点,从而提高器件的性能。例如,氮化镓材料通常可以外延生长在蓝宝石、硅或者碳化硅衬底上,且各有优缺点。采用本发明的方法,可以将低成本,高质量的外延薄膜从导热差的衬底如蓝宝石转移到高导热性衬底如导热氮化铝基片上以满足功率器件对散热的要求;或者将外延薄膜从难以做背通孔工艺的衬底如蓝宝石转移到易于做该工艺的衬底如硅片上,满足微波器件对接地的要求。并且,采用本申请所提供的方法,有利于将不同功能的器件集成在一起,提高系统的集成度来实现片上系统(SOC)。例如,将氮化镓微波功率放大器的结构同含有数字预失真电路(DPD)的硅基大规模集成电路相结合,从而实现混合信号(Mix Signal)射频前端的单片集成。
相应的,本申请还提出一种半导体结构,采用上述任一实施例所提出的半导体制造方法制备而成。
请参考图8,所述半导体结构包括:衬底8(即第二衬底)、介质层7、势垒层3、缓冲层2、源极4、漏极5、第一栅极6和第二栅极9。所述介质层7位于所述衬底8上,所述势垒层3位于所述介质层上。所述源极4、漏极5和第一栅极6(即背栅)位于所述介质层7的凹槽内,与所述势垒层3相连接。所述源极4和漏极5的分别位于所述第一栅极6的两侧。所述缓冲层2位于所述势垒层3上。所述第二栅极9位于缓冲层3上,与所述第一栅极6对准。
所述衬底8材料可以为蓝宝石、硅、氮化铝、碳化硅、陶瓷、石英、金属基板等,所述衬底8的厚度在300um以上。所述缓冲层2靠近所述势垒层3一端的表面形成二维电子气(2DEG),所述2DEG具有高电子密度和高电子迁移率。所述缓冲层2是氮化镓高质量晶体,所述势垒层3可以为铝镓氮、铟铝氮等三五族化合物半导体合金。所述缓冲层2的厚度为20nm-100nm,所述势垒层3的厚度为10nm-50nm。
所述第一栅极6和第二栅极9可以为镍、金、铂等构成的金属叠层,所述源极4和漏极5可以为为钛、铝、镍、金等金属中任意多种组成的合金。
所述介质层7可以为氮化硅或者二氧化硅等绝缘材料。
在本实施例中,所述第二栅极9与所示缓冲层2之间还设有介电层10,以减少第二栅极的漏电流。所述介电层10的厚度为1-10nm,材料可以是氮化硅或者二氧化硅。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (7)
1.一种半导体器件制造方法,其特征在于,包括:
在第一衬底上依次生长缓冲层和势垒层;
在所述势垒层上生长源极、漏极和第一栅极,形成第一结构;
在所述第一结构上生长介质层;
将所述介质层与第二衬底键合,并去除所述第一衬底,形成第二结构;
将所述第二结构倒置,并对所述缓冲层进行减薄处理;
在减薄后的缓冲层上生长第二栅极。
2.根据权利要求1所述的半导体器件制造方法,其特征在于,对所述缓冲层进行减薄处理之后,生长第二栅极之前,在所述减薄后的缓冲层上生长介电层。
3.根据权利要求2所述的半导体器件制造方法,其特征在于,所述介电层的厚度为1nm-10nm。
4.根据权利要求1所述的半导体器件制造方法,其特征在于,将所述介质层与第二衬底键合之前,在所述介质层上形成键合层。
5.根据权利要求1所述的半导体器件制造方法,其特征在于,减薄前缓冲层厚度大于1um,减薄后缓冲层为20nm-100nm。
6.根据权利要求1所述的半导体器件制造方法,其特征在于,所述第二栅极与所述第一栅极对准。
7.一种半导体器件,其特征在于,采用如权利要求1-6任意项所述的半导体制造方法制备而成。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114695114A (zh) * | 2022-05-31 | 2022-07-01 | 绍兴中芯集成电路制造股份有限公司 | 半导体器件及其制作方法 |
WO2023100058A1 (en) * | 2021-12-05 | 2023-06-08 | International Business Machines Corporation | A high electron mobility transistor with source and drain electrodes below the channel |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4821093A (en) * | 1986-08-18 | 1989-04-11 | The United States Of America As Represented By The Secretary Of The Army | Dual channel high electron mobility field effect transistor |
US20090072272A1 (en) * | 2007-09-17 | 2009-03-19 | Transphorm Inc. | Enhancement mode gallium nitride power devices |
US20100065923A1 (en) * | 2008-09-16 | 2010-03-18 | Alain Charles | Iii-nitride device with back-gate and field plate and process for its manufacture |
CN103715235A (zh) * | 2014-01-09 | 2014-04-09 | 苏州能屋电子科技有限公司 | 具有背面场板结构的增强型mis-hemt器件及其制备方法 |
-
2018
- 2018-08-06 CN CN201810881343.1A patent/CN109037065A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4821093A (en) * | 1986-08-18 | 1989-04-11 | The United States Of America As Represented By The Secretary Of The Army | Dual channel high electron mobility field effect transistor |
US20090072272A1 (en) * | 2007-09-17 | 2009-03-19 | Transphorm Inc. | Enhancement mode gallium nitride power devices |
US20100065923A1 (en) * | 2008-09-16 | 2010-03-18 | Alain Charles | Iii-nitride device with back-gate and field plate and process for its manufacture |
CN103715235A (zh) * | 2014-01-09 | 2014-04-09 | 苏州能屋电子科技有限公司 | 具有背面场板结构的增强型mis-hemt器件及其制备方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023100058A1 (en) * | 2021-12-05 | 2023-06-08 | International Business Machines Corporation | A high electron mobility transistor with source and drain electrodes below the channel |
CN114695114A (zh) * | 2022-05-31 | 2022-07-01 | 绍兴中芯集成电路制造股份有限公司 | 半导体器件及其制作方法 |
CN114695114B (zh) * | 2022-05-31 | 2022-09-09 | 中芯越州集成电路制造(绍兴)有限公司 | 半导体器件及其制作方法 |
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