CN109004083A - Chip-packaging structure and preparation method thereof with single cofferdam and scolding tin - Google Patents
Chip-packaging structure and preparation method thereof with single cofferdam and scolding tin Download PDFInfo
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- CN109004083A CN109004083A CN201810929729.5A CN201810929729A CN109004083A CN 109004083 A CN109004083 A CN 109004083A CN 201810929729 A CN201810929729 A CN 201810929729A CN 109004083 A CN109004083 A CN 109004083A
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- cofferdam
- hole
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 title claims abstract description 62
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 238000005476 soldering Methods 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims description 59
- 239000004033 plastic Substances 0.000 claims description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000003384 imaging method Methods 0.000 claims description 16
- 238000005538 encapsulation Methods 0.000 claims description 9
- 238000005253 cladding Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 11
- 239000000126 substance Substances 0.000 abstract description 9
- 239000010949 copper Substances 0.000 description 71
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 68
- 229910052802 copper Inorganic materials 0.000 description 68
- 239000002184 metal Substances 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 27
- 241000208340 Araliaceae Species 0.000 description 26
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 26
- 235000003140 Panax quinquefolius Nutrition 0.000 description 26
- 235000008434 ginseng Nutrition 0.000 description 26
- 239000000463 material Substances 0.000 description 13
- 238000000465 moulding Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229920006336 epoxy molding compound Polymers 0.000 description 6
- 238000010897 surface acoustic wave method Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 230000033001 locomotion Effects 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 238000010068 moulding (rubber) Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000011218 segmentation Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 235000021384 green leafy vegetables Nutrition 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/88—Mounts; Supports; Enclosures; Casings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/02—Forming enclosures or casings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
Present invention discloses a kind of chip-packaging structure and preparation method thereof with single cofferdam and scolding tin, encapsulating structure include: package substrate, and the side of base lower surface has external pin；Filter chip, chip lower surface are arranged face-to-face with upper surface of base plate, and chip lower surface has electrode；Interconnection structure, for several electrodes and several external pins to be connected；Cofferdam cooperates with chip lower surface and upper surface of base plate and encloses to set to form cavity；Package substrate has several through-holes passed through for several interconnection structures, and cofferdam is located at the inside of several through-holes, and interconnection structure includes the cooperate soldering structure interconnected and electroplated layer structure, soldering structure conduction electrode, electroplated layer structure conducting external pin.The present invention forms cavity by setting cofferdam, it is possible to prevente effectively from external substance enters cavity inside and influences the normal use of filter chip in encapsulating structure manufacturing process or in encapsulating structure use process, to improve the overall performance of encapsulating structure.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to a kind of chip-packaging structure with single cofferdam and scolding tin and
Its production method.
Background technique
RF IC (RFIC) is widely used in wireless device, for example, cellular telephone.
RFIC is on matrix the discrete of transmission line, matching network and inductance coil, resistance, capacitor and transistor etc
Element is combined together the subsystem for providing and capable of transmitting and receive high-frequency signal, for example, in about 0.1 to 100 gigabits
In the range of conspicuous (GHz), the encapsulation of RFIC differs markedly from the encapsulation of digital integrated electronic circuit, because the encapsulation is often radio frequency electrical
The a part on road, moreover, because the rf electric field and/or magnetic field energy of RFIC complexity and any neighbouring insulator and conductor are mutual
Effect, in order to meet wireless industrial increasing demand, RFIC encapsulation development is tried to provide more small and exquisite, more cheap, performance more
High adapts to the device of more bare die radio-frequency modules, while providing higher reliability and using unleaded solder and other " greens
" material.The one chip encapsulation that single or multiple bare die RFIC is encapsulated individually is to solve the small size and inexpensive demand of RFIC
Direct solution, and be used for most of RFIC now.
Microelectromechanical systems (MEMS) permits the controlled conversion between miniature scale mechanical movement and specified electric signal,
For example, consistent with specified frequency, MEMS is being widely used for RFIC.
Based on mechanical movement, RF MEMS is able to achieve fabulous signal quality for radio frequency band filter, and citing comes
It says, SAW filter converts electrical signals into mechanical wave, and the latter propagates before its converted back into electric signals along piezo-electric crystal matrix
When be delayed by；BAW filter realizes expected special resonance using volume mass motion；And in RF switch, electric signal
For controlling the movement of microelectrode, switch is opened or closed.
Present MEMS technology grows up from semiconductor fabrication process, however, mechanical fortune associated with MEMS
Dynamic packaging structure and the requirement for requiring to be totally different from traditional semiconductor integrated circuit, specifically, in all MEMS collection
Inside circuit, some materials must be moved freely uninterruptedly, and therefore, MEMS integrated circuit must be shielded in movement material
Small vacuum or air pocket are formed around material to allow them to move while to protect them.
And in the prior art, a closing and reliable cavity can not be formed to realize the protection of circuit or other structures.
Summary of the invention
The purpose of the present invention is to provide a kind of chip-packaging structure and preparation method thereof with single cofferdam and scolding tin.
One of for achieving the above object, an embodiment of the present invention provides a kind of chip with single cofferdam and scolding tin
Encapsulating structure, comprising:
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, the side tool of the base lower surface
There are several external pins；
Filter chip, has the chip upper surface that is oppositely arranged and a chip lower surface, the chip lower surface with it is described
Upper surface of base plate is arranged face-to-face, and the chip lower surface has several electrodes；
Several interconnection structures, for several electrodes and several external pins to be connected；
Cofferdam cooperates with the chip lower surface and the upper surface of base plate and encloses to set to form cavity；
Wherein, the package substrate has several through-holes passed through for several interconnection structures, and the cofferdam is located at several logical
The inside in hole, the interconnection structure include the cooperate soldering structure interconnected and electroplated layer structure, the soldering structure conducting
The external pin is connected in the electrode, the electroplated layer structure.
As the further improvement of an embodiment of the present invention, the soldering structure include scolding tin and the conducting scolding tin and
The UBM layer of the electrode, the electroplated layer structure include being covered in the through-hole wall and extending to the upper surface of base plate, institute
The electricity stating the plating seed layer of base lower surface and being mutually matched outside the plating seed layer and with the plating seed layer
Coating, the scolding tin extend to the through-hole and the electroplated layer of the through-hole wall are connected.
As the further improvement of an embodiment of the present invention, the electroplated layer structure extends to the upper surface of base plate
Width is less than the width that the electroplated layer structure extends to the base lower surface.
As the further improvement of an embodiment of the present invention, upper surface and the UBM layer of the electroplated layer structure
With overlapping region and with gap between lower surface.
As the further improvement of an embodiment of the present invention, there is gap between the cofferdam and several through-holes.
As the further improvement of an embodiment of the present invention, the cross-sectional area of the UBM layer is equal to the electrode
Surface area, and the cross-sectional area of the scolding tin is less than the cross-sectional area of the UBM layer.
As the further improvement of an embodiment of the present invention, the encapsulating structure further includes remote positioned at the package substrate
The plastic packaging layer of side from the base lower surface, the plastic packaging layer coat the cofferdam lateral area and the filter simultaneously
Chip, and the encapsulating structure further includes the soldermask layer for being set to the base lower surface and exposing the external pin.
One of for achieving the above object, an embodiment of the present invention provides a kind of chip with single cofferdam and scolding tin
The production method of encapsulating structure, comprising steps of
S1: providing filter chip, has the chip upper surface being oppositely arranged and chip lower surface, the chip following table
Face has several electrodes；
S2: UBM layer is formed in the lower surface of the electrode；
S3: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S4: in forming several through-holes on the package substrate；
S5: electroplated layer is formed in the upper surface of base plate of the through-hole wall and the connection through-hole wall, base lower surface
Structure；
S6: cofferdam is formed in the upper surface of base plate；
S7: the filter chip is assembled to the package substrate, the chip lower surface and the upper surface of base plate
Setting face-to-face, the cofferdam are located at the inside of several through-holes, and on the cofferdam and the chip lower surface and the substrate
Surface engagement and enclose and set to form cavity；
S8: in the scolding tin for forming the conducting electrode and the electroplated layer structure on the UBM layer；
S9: external pin is formed below the electroplated layer structure.
As the further improvement of an embodiment of the present invention, step S5 is specifically included:
Electricity is formed in the part substrate upper surface of the through-hole wall and the connection through-hole wall, whole base lower surfaces
Plate seed layer；
The second photoresist film is formed in the lower section of the plating seed layer of the base lower surface, and in second light
Photoresist film exposure and imaging forms several second holes, and second hole exposes the through-hole and plating seed layer；
Electroplated layer is formed in being exposed on outer plating seed layer；
Remove the second photoresist film；
Removal is exposed to outer plating seed layer.
As the further improvement of an embodiment of the present invention, step S8, S9 is specifically included:
Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats institute simultaneously
Cofferdam lateral area and the filter chip are stated, several UBM layers are aligned to several through-holes；
The plastic packaging layer is etched to expose the UBM layer；
In forming scolding tin on the UBM layer, the scolding tin extends to the through-hole and the plating of the through-hole wall is connected
Layer；
In base lower surface formed soldermask layer, the soldermask layer coat simultaneously the base lower surface, the electroplated layer and
The scolding tin；
Several third holes are formed in the soldermask layer exposure and imaging, the third hole exposes the electroplated layer；
In forming ball grid array in several third holes.
Compared with prior art, the beneficial effects of the present invention are: present embodiments forms cavity by setting cofferdam, can
With effectively avoid in encapsulating structure manufacturing process or in encapsulating structure use process external substance enter cavity inside and
The normal use for influencing filter chip, to improve the overall performance of encapsulating structure.
Detailed description of the invention
Fig. 1 is the encapsulating structure cross-sectional view of first embodiment of the invention；
Fig. 2 is the package substrate of first embodiment of the invention and the schematic diagram in cofferdam；
Fig. 3 is the production method block diagram of the encapsulating structure of first embodiment of the invention；
Fig. 4 a- Fig. 4 v is the production method flow chart of the encapsulating structure of first embodiment of the invention；
Fig. 5 is the encapsulating structure cross-sectional view of second embodiment of the invention；
Fig. 6 is the package substrate of second embodiment of the invention and the schematic diagram in cofferdam；
Fig. 7 is the production method block diagram of the encapsulating structure of second embodiment of the invention；
Fig. 8 a- Fig. 8 w is the production method flow chart of the encapsulating structure of second embodiment of the invention；
Fig. 9 is the encapsulating structure cross-sectional view of third embodiment of the invention；
Figure 10 is the package substrate of third embodiment of the invention and the schematic diagram in cofferdam；
Figure 11 is the production method block diagram of the encapsulating structure of third embodiment of the invention；
Figure 12 a- Figure 12 w is the production method flow chart of the encapsulating structure of third embodiment of the invention.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1, is the cross-sectional view of the chip-packaging structure 100 with single cofferdam of first embodiment of the invention.
Encapsulating structure 100 includes package substrate 10, filter chip 20, several interconnection structures 30 and cofferdam 40.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, the side of base lower surface 12
With several external pins 121.
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical
Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121
For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
Filter chip 20 has the chip upper surface 21 and chip lower surface 22, chip lower surface 22 and base being oppositely arranged
Plate upper surface 11 is arranged face-to-face, and chip lower surface 22 has several electrodes 221.
Here, filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW)
Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, 20 surface of filter chip
Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs
A cavity is formed in the lower section of filter chip 20 to protect the active region.
Electrode 221 protrudes out chip lower surface 22 towards the direction far from chip upper surface 21, and but not limited to this.
In general, the size of filter chip 20 is less than the size of package substrate 10.
Several interconnection structures 30 are for being connected several electrodes 221 and several external pins 121.
Cofferdam 40 and chip lower surface 22 and upper surface of base plate 11 cooperate and enclose to set to form cavity S, the corresponding filtering of cavity S
The active region on 20 surface of device chip.
Here, package substrate 10 has several through-holes 13 passed through for several interconnection structures 30, and cofferdam 40 is located at several logical
The inside in hole 13.
It should be noted that " package substrate 10 has several through-holes 13 passed through for several interconnection structures 30 " refers to interconnection
At least partly structure of structure 30 passes through corresponding through-hole 13, to realize the interconnection of electrode 221 and external pin 121.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100.
In conjunction with Fig. 2, several through-holes 13 are in array distribution in upper surface of base plate 11, and have interval between adjacent through-holes 13,
There is a space, cofferdam 40 is located in the space, and cofferdam 40 is located at several 13 insides of through-hole between two column through-holes 13.
Cofferdam 40 is closed cyclic structure, and chip lower surface 22 covers the upper surface in cofferdam 40, and upper surface of base plate 11 covers
The lower surface in lid cofferdam 40, in this way, cofferdam 40, chip lower surface 22 and upper surface of base plate 11 complement each other to form case type sky
Chamber S.
There is gap between cofferdam 40 and several through-holes 13.
Cofferdam 40 is made of photaesthesia insulating materials, and but not limited to this.
In the present embodiment, encapsulating structure 100 further includes coating 40 lateral area of cofferdam and filter chip 20 simultaneously
Plastic packaging layer 50, and plastic packaging layer 50 is located at side of the package substrate 10 far from base lower surface 12.
Here, " 40 lateral area of cofferdam " refers to all open areas of the side positioned at cofferdam 40 far from cavity S, also
It is to say, plastic packaging layer 50 coats open area all around filter chip 20, and plastic packaging layer 50 is located at the upper of package substrate 10
Side.
Plastic packaging layer 50 can be EMC (Epoxy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes
Weir 40 can stop external substance to enter cavity S, without considering whether plastic packaging layer 50 can influence in cavity S because of problem of materials
Protection zone, therefore, the range of choice of 50 material of plastic packaging layer expands significantly, and then can evade the choosing of specific capsulation material
It selects, substantially widen plastic packaging making technology window and effectively reduce cost.
In the present embodiment, encapsulating structure 100 further includes being set to base lower surface 12 and exposing external pin 121
Soldermask layer 60.
Continue to join Fig. 1 and Fig. 2, in the present embodiment, interconnection structure 30 includes the metal column structures interconnected that cooperate
31 and metal-layer structure 32, external pin 121 is connected in 31 conduction electrode 221 of metal column structures, metal-layer structure 32.
Specifically, metal column structures 31 include metal column 311 and the UBM layer 312 that metal column 311 and electrode 221 is connected, gold
Belonging to layer structure 32 includes metal layer 321 and the plating seed layer 322 that metal layer 321 and metal column 311 is connected, metal-layer structure 32
Filling 13 interior zone of through-hole simultaneously extends to base lower surface 12, and the lower section of metal layer 321 connects external pin 121.
Plating seed layer 322 and the outer profile of metal layer 321 are mutually matched, plating seed layer 322 along 13 inner wall of through-hole to
Base lower surface 12 extends, and metal layer 321 is filled through-hole 13 and extended along base lower surface 12, and the lower surface of metal layer 321 is
Plane.
It should be noted that base lower surface 12 is also equipped with plating seed layer 322, metal layer far from the region of through-hole 13
321 and external pin 121.
Here, metal column 311 is copper post 311, and metal layer 321 is layers of copper 321, and UBM layer 312 and plating seed layer 322 can
Think Ti/Cu layers, but not limited to this.
For UBM layer 312 as the transition zone between copper post 311 and electrode 221, the molding that copper post 311 can be effectively reduced is difficult
Degree, improves molding, the fixed effect of copper post 311, and the electrical transmission performance between copper post 311 and electrode 221 can be improved.
Likewise, plating seed layer 322 is as between copper post 311 and layers of copper 321, between layers of copper 321 and package substrate 10
Transition zone, can be effectively reduced the molding difficulty of layers of copper 321, improve molding, the fixed effect of layers of copper 321, and copper can be improved
Electrical transmission performance between column 311 and layers of copper 321.
The upper surface of metal-layer structure 32 has the groove 323 for accommodating metal column structures 31, and in the present embodiment, recessed
Only accommodating portion copper post 311, UBM layer 312 are located at outside groove 323 slot 323.
Here, groove 323 can be all round closure only structure of the top with opening, copper post 311, groove 323 and through-hole
13 advantages being equipped with are: (1) groove 323 and copper post 311 mutually align, and groove 323 plays limit to copper post 311 and makees
With improving the aligning accuracy and final products yield in encapsulation process, reduce the difficulty of packaging technology, and filter at this time
The problem of position of chip 20 is fixed, is not in die drift；(2) copper post 311 has already taken up a part of space of through-hole 13,
The plating amount that layers of copper 321 can be reduced when copper electroplating layer 321 in the through-hole 13 at this time, reduces electroplating technique difficulty, contracting
Short electroplating time, and then improve plating production capacity；(3) 311 appearance of copper post is significant, can be used as identification part to improve identification effect
Rate, and then convenient for the detection of automatic aspect and possible defect recognition.
In the present embodiment, the outer collar region of the upper surface of metal-layer structure 32 is flushed with upper surface of base plate 11.
That is, other than 323 region of groove is in indent form, table on the upper surface of plating seed layer 322 and substrate
Face 11 is in the same plane.
With overlapping region and with gap between the upper surface of metal-layer structure 32 and the lower surface of electrode 221, moreover,
The cross-sectional area of UBM layer 312 is less than the surface area of electrode 221, and the cross-sectional area of copper post 311 is equal to UBM layer 312
Cross-sectional area.
It can be seen that UBM layer 312 is laid in the intermediate region of electrode 221, the corresponding UBM layer 312 of copper post 311 is arranged, this
When, there is gap between the upper surface of plating seed layer 322 and the lower surface of electrode 221, filled out in the gap and its extended segment
Filled with plastic packaging layer 50.
An embodiment of the present invention also provides a kind of production method of chip-packaging structure with single cofferdam, in conjunction with aforementioned
The explanation and Fig. 3, Fig. 4 a to Fig. 4 v of chip-packaging structure 100 with single cofferdam, production method comprising steps of
S1: ginseng Fig. 4 a provides filter chip 20, has the chip upper surface 21 being oppositely arranged and chip lower surface
22, chip lower surface 22 has several electrodes 221；
S2: ginseng Fig. 4 b to Fig. 4 g forms several first interconnection structures in the lower surface of several electrodes 221；
It is specific as follows:
Join Fig. 4 b, forms UBM layer 312 in chip lower surface 22；
Join Fig. 4 c, forms the first photoresist film 70 in the lower section of UBM layer 312；
Join Fig. 4 d, forms several first holes 71, the corresponding electricity of the first hole 71 in 70 exposure and imaging of the first photoresist film
Pole 221, and the first hole 71 exposes UBM layer 312；
Join Fig. 4 e, in forming several copper posts 311 in several first holes 71；
Join Fig. 4 f, removes the first photoresist film 70；
Join Fig. 4 g, removal is exposed to outer UBM layer 312.
S3: ginseng Fig. 4 h provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S4: ginseng Fig. 4 i, in forming several through-holes 13 on package substrate 10；
S5: ginseng Fig. 4 j and Fig. 4 k forms cofferdam 40 in upper surface of base plate 11；
It is specific as follows:
Join Fig. 4 j, lays photaesthesia insulating film 80 in upper surface of base plate 11；
Join Fig. 4 k, exposure and imaging forms cofferdam 40, and cofferdam 40 is located at the inside of several through-holes 13, and cofferdam 40 and through-hole
There is gap between 13.
It should be noted that being formed since independent package substrate 10 can be divided by the large substrates of wafer scale, molding is enclosed
When weir 40, can on large substrates the multiple cofferdam 40 of straight forming, then carry out the segmentation of large substrates again and obtain having single
The single package substrate 10 in cofferdam 40, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic in filter core
On piece 20.
Filter chip 20 is assembled to package substrate 10, chip lower surface 22 and 11 face of upper surface of base plate by S6: ginseng Fig. 4 l
It is provided opposite to, cofferdam 40 is located at the inside of several through-holes 13, and cofferdam 40 and chip lower surface 22 and upper surface of base plate 11 cooperate
And it encloses and sets to form cavity S；
S7: ginseng Fig. 4 m to Fig. 4 s forms the second interconnection structure of the first interconnection structure of conducting, the first interconnection structure and second
Interconnection structure at least partially by through-hole 13；
It is specific as follows:
Join Fig. 4 m, forms plastic packaging layer 50 far from the side of base lower surface 12 in package substrate 10, plastic packaging layer 50 wraps simultaneously
40 lateral area of cofferdam and filter chip 20 are covered, several copper posts 311 extend towards several through-holes 13；
Join Fig. 4 n, forms continuous plating seed layer 322 along base lower surface 12,13 inner wall of through-hole and copper post 311；
Join Fig. 4 o, forms the second photoresist film 90 in the lower section of plating seed layer 322；
Join Fig. 4 p, forms several second holes 91 in 90 exposure and imaging of the second photoresist film, the exposure of the second hole 91 is logical
Hole 13 and plating seed layer 322；
Join Fig. 4 q, in plating fill copper layer 321 in several second holes 91；
Join Fig. 4 r, removes the second photoresist film 90；
Join Fig. 4 s, removal is exposed to outer plating seed layer 322.
S8: ginseng Fig. 4 t to Fig. 4 v forms external pin 121 below the second interconnection structure.
It is specific as follows:
Join Fig. 4 t, forms soldermask layer 60 in base lower surface 12, soldermask layer 60 coats base lower surface 12 and layers of copper simultaneously
321；
Join Fig. 4 u, forms several third holes 61 in 60 exposure and imaging of soldermask layer, third hole 61 exposes layers of copper
321；
Join Fig. 4 v, in formation ball grid array 121 in several third holes 61.
Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100
Bright, details are not described herein.
Join Fig. 5, is the cross-sectional view of the encapsulating structure 100a of second embodiment of the invention.
For ease of description, present embodiment is identical with first embodiment or similar structure uses similar label,
Certainly, the structure of like numerals also can have different effects, depending on needing according to the actual situation, below other embodiments
And in this way, subsequent repeat no more.
Encapsulating structure 100a includes package substrate 10a, filter chip 20a, several interconnection structure 30a and cofferdam 40a.
Package substrate 10a has the upper surface of base plate 11a and base lower surface 12a being oppositely arranged, base lower surface 12a's
Side has several external pin 121a.
Here, package substrate 10a is the loading plate for carrying chip, and package substrate 10a can be print made of organic resin
Printed circuit board is also possible to glass substrate or ceramic substrate etc..
External pin 121a can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100a
It can be electrically connected with realizations such as other chips or substrates by external pin 121a, here, external pin 121a is with ball bar battle array
For arranging 121a, external pin 121a protrudes out the lower surface of encapsulating structure 100a.
Filter chip 20a has the chip upper surface 21a and chip lower surface 22a being oppositely arranged, chip lower surface 22a
It is arranged face-to-face with upper surface of base plate 11a, chip lower surface 22a has several electrode 221a.
Here, filter chip 20a can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW)
Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20a
Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs
A cavity is formed in the lower section of filter chip 20a to protect the active region.
Electrode 221a protrudes out chip lower surface 22a towards the direction far from chip upper surface 21a, and but not limited to this.
In general, the size of filter chip 20a is less than the size of package substrate 10a.
Several interconnection structure 30a are for being connected several electrode 221a and several external pin 121a.
Cofferdam 40a and chip lower surface 22a and upper surface of base plate 11a cooperates and encloses to set to form cavity S, and cavity S is corresponding
The active region on the surface filter chip 20a.
Here, package substrate 10a has several through-hole 13a passed through for several interconnection structure 30a, if cofferdam 40a is located at
The inside of dry through-hole 13a, interconnection structure 30a include the soldering structure 33a and electroplated layer structure 32a interconnected that cooperate, scolding tin
External pin 121a is connected in structure 33a conduction electrode 221a, electroplated layer structure 32a.
Present embodiment by setting cofferdam 40a formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20a in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100a.
In conjunction with Fig. 6, several through-hole 13a in array distribution in upper surface of base plate 11a, and between having between adjacent through-holes 13a
Every there is a space, cofferdam 40a is located in the space, and cofferdam 40a is located at the interior of several through-hole 13a between two column through-hole 13a
Side.
Cofferdam 40a is closed cyclic structure, and chip lower surface 22a covers the upper surface of cofferdam 40a, upper surface of base plate
11a covers the lower surface of cofferdam 40a, in this way, cofferdam 40a, chip lower surface 22a and upper surface of base plate 11a are complemented each other to form
Case type cavity S.
There is gap between cofferdam 40a and several through-hole 13a.
Cofferdam 40a is made of photaesthesia insulating materials, and but not limited to this.
In the present embodiment, encapsulating structure 100a further includes coating cofferdam 40a lateral area and filter chip simultaneously
The plastic packaging layer 50a of 20a, and plastic packaging layer 50a is located at side of the package substrate 10a far from base lower surface 12a.
Here, " cofferdam 40a lateral area " refers to all open areas of the side positioned at cofferdam 40a far from cavity S,
That is open area all around plastic packaging layer 50a cladding filter chip 20a, and plastic packaging layer 50a is located at package substrate
The top of 10a.
Plastic packaging layer 50a can be EMC (Epoxy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes
Weir 40a can stop external substance to enter cavity S, without considering whether plastic packaging layer 50a can influence cavity S because of problem of materials
Interior protection zone, therefore, the range of choice of plastic packaging layer 50a material expand significantly, and then can effectively evade specific plastic packaging material
The selection of material substantially widens plastic packaging making technology window and reduces cost.
In the present embodiment, encapsulating structure 100a further includes being set to base lower surface 12a and exposing external pin
The soldermask layer 60a of 121a.
Continue join Fig. 5 and Fig. 6, in the present embodiment, soldering structure 33a include scolding tin 331a and conducting scolding tin 331a and
The UBM layer 312a of electrode 221a, electroplated layer structure 32a include be covered in through-hole 13a inner wall and extend to upper surface of base plate 11a,
It the plating seed layer 322a of base lower surface 12a and is mutually matched outside plating seed layer 322a and with plating seed layer 322a
Electroplated layer 321a, scolding tin 331a extends to through-hole 13a and the electroplated layer 321a of through-hole 13a inner wall is connected, electroplated layer 321a's
Lower section connects external pin 121a.
Plating seed layer 322a and the outer profile of electroplated layer 321a are mutually matched, and plating seed layer 322a is by through-hole 13a
Wall extends to upper surface of base plate 11a and base lower surface 12a respectively, electroplated layer 321a according to plating seed layer 322a laying area
Domain is also extended to upper surface of base plate 11a and base lower surface 12a from through-hole 13a inner wall respectively, and the lower surface of electroplated layer 321a is
Plane.
It should be noted that base lower surface 12a is also equipped with plating seed layer 322a, electricity far from the region of through-hole 13a
Coating 321a and external pin 121a.
Here, it can be Ti/Cu layers that electroplated layer 321a, which is layers of copper 321a, UBM layer 312a and plating seed layer 322a, but not
As limit.
UBM layer 312a as the transition zone between scolding tin 331a and electrode 221a, can be effectively reduced scolding tin 331a at
Type difficulty, improves molding, the fixed effect of scolding tin 331a, and the electrical transporting between scolding tin 331a and electrode 221a can be improved
Energy.
Likewise, plating seed layer 322a can effectively be dropped as the transition zone between layers of copper 321a and package substrate 10a
The molding difficulty of low layers of copper 321a improves molding, the fixed effect of layers of copper 321a.
Here, tin cream 331a is extended in through-hole 13a by UBM layer 312a, and mutual with the layers of copper 321a of through-hole 13a inner wall
Contact, which is realized, to be electrically connected, so as to conduction electrode 221a and external pin 121a.
The advantage that scolding tin 331a and through-hole 13a is arranged is: (1) scolding tin 331a is molten condition in reflow soldering process,
Convenient for effectively filling through-hole 13a and in conjunction with UBM layer 312a, and combine effect preferable；(2) scolding tin 331a can be with through-hole 13a
The layers of copper 321a of entire internal perisporium contacts with each other, and contact area is big, and electrical transmission performance can be improved, and scolding tin 331a also can be improved
Strong degree in conjunction with layers of copper 321a；(3) reflow soldering process that scolding tin 331a is used is succinct, and high production efficiency can be greatly reduced
Production cost and shortening product delivery cycle.
In the present embodiment, the width that electroplated layer structure 32a extends to upper surface of base plate 11a is less than electroplated layer structure
32a extends to the width of base lower surface 12a.
Here, on the one hand, upper surface of base plate 11a and base lower surface 12a is provided with electroplated layer structure 32a, Ke Yiti
Strong degree of the high electroplated layer structure 32a in conjunction with package substrate 10a；On the other hand, the electroplated layer structure of base lower surface 12a
32a width is greater than the electroplated layer structure 32a width of upper surface of base plate 11a, can make the external pin of base lower surface 12a
121a be combined with each other consequently facilitating encapsulating structure 100a is subsequent with other chips or other substrates etc. far from through-hole 13a.
With overlapping region and with gap between the upper surface of electroplated layer structure 32a and the lower surface of UBM layer 312a, and
The cross-sectional area of tin cream 331a is less than the cross-sectional area of UBM layer 312a.
It can be seen that UBM layer 312a is distributed in the lower surface area of electrode 221a, and tin cream 331a is only laid in UBM layer
The intermediate region of 312a, at this point, between having between the upper surface and UBM layer 312a of the layers of copper 321a of upper surface of base plate 11a
Gap is filled with plastic packaging layer 50a in the gap and its extended segment.
An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100a
Bright and Fig. 7, Fig. 8 a to Fig. 8 w, production method comprising steps of
S1: ginseng Fig. 8 a provides filter chip 20a, has the chip upper surface 21a being oppositely arranged and chip lower surface
22a, chip lower surface 22a have several electrode 221a；
S2: ginseng Fig. 8 b to Fig. 8 f forms UBM layer 312a in the lower surface of electrode 221a；
It is specific as follows:
Join Fig. 8 b, forms UBM layer 312a in chip lower surface 22a；
Join Fig. 8 c, forms the first photoresist film 70a in the lower section of UBM layer 312a；
Join Fig. 8 d, forms several first hole 71a in the first photoresist film 70a exposure and imaging, the first hole 71a is corresponding
Other regions of electrode 221a are removed, and the first hole 71a exposes UBM layer 312a；
Join Fig. 8 e, the UBM layer 312a that the first hole 71a of etching exposes；
Join Fig. 8 f, removes the first photoresist film 70a.
S3: ginseng Fig. 8 g provides package substrate 10a, has the upper surface of base plate 11a and base lower surface being oppositely arranged
12a；
S4: ginseng Fig. 8 h, in forming several through-hole 13a on package substrate 10a；
S5: ginseng Fig. 8 i to Fig. 8 n in through-hole 13a inner wall and connects under the upper surface of base plate 11a of through-hole 13a inner wall, substrate
Surface 12a forms electroplated layer structure 32a；
It is specific as follows:
Join Fig. 8 i, in the part substrate upper surface 11a of through-hole 13a inner wall and connection through-hole 13a inner wall, whole substrate following tables
Face 12a forms plating seed layer 322a；
Join Fig. 8 j, forms the second photoresist film 90a in the lower section of the plating seed layer 322a of base lower surface 12a；
Join Fig. 8 k, forms several second hole 91a, the second hole 91a exposure in the second photoresist film 90a exposure and imaging
Through-hole 13a and plating seed layer 322a；
Join Fig. 8 l, forms layers of copper 321a in being exposed on outer plating seed layer 322a；
Join Fig. 8 m, removes the second photoresist film 90a；
Join Fig. 8 n, removal is exposed to outer plating seed layer 322a.
S6: ginseng Fig. 8 o and Fig. 8 p forms cofferdam 40a in upper surface of base plate 11a；
It is specific as follows:
Join Fig. 8 o, lays photaesthesia insulating film 80a in upper surface of base plate 11a；
Join Fig. 8 p, exposure and imaging forms cofferdam 40a, and cofferdam 40a is located at the inside of several through-hole 13a, and cofferdam 40a and
There is gap between through-hole 13a.
It should be noted that being formed since independent package substrate 10a can be divided by the large substrates of wafer scale, molding is enclosed
When the 40a of weir, can on large substrates the multiple cofferdam 40a of straight forming, then carry out the segmentation of large substrates again and obtain having single
The single package substrate 10a of a cofferdam 40a, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40a is also plastic to be filtered
On device chip 20a.
Filter chip 20a is assembled to package substrate 10a, chip lower surface 22a and upper surface of base plate by S7: ginseng Fig. 8 q
11a is arranged face-to-face, and cofferdam 40a is located at the inside of several through-hole 13a, and table on cofferdam 40a and chip lower surface 22a and substrate
Face 11a cooperates and encloses and set to form cavity S；
S8: ginseng Fig. 8 r to Fig. 8 t, in the scolding tin for forming conduction electrode 221a and electroplated layer structure 32a on UBM layer 312a
331a；
It is specific as follows:
Join Fig. 8 r, forms plastic packaging layer 50a far from the side of base lower surface 12a in package substrate 10a, plastic packaging layer 50a is same
When cladding cofferdam 40a lateral area and filter chip 20a, several UBM layer 312a be aligned to several through-hole 13a；
Join Fig. 8 s, etches plastic packaging layer 50a to expose UBM layer 312a；
Join Fig. 8 t, in forming scolding tin 331a on UBM layer 312a, tin cream 331a extends to through-hole 13a and is connected in through-hole 13a
The layers of copper 321a of wall.
S9: ginseng Fig. 8 u to Fig. 8 w forms external pin 121a below electroplated layer structure 32a.
It is specific as follows:
Join Fig. 8 u, forms soldermask layer 60a in base lower surface 12a, soldermask layer 60a coats base lower surface 12a, copper simultaneously
Layer 321a and scolding tin 331a；
Join Fig. 8 v, forms several third hole 61a in soldermask layer 60a exposure and imaging, third hole 61a exposes layers of copper
321a；
Join Fig. 8 w, in formation ball grid array 121a in several third hole 61a.
Other explanations of the production method of the encapsulating structure 100a of present embodiment can refer to above-mentioned encapsulating structure 100a
Explanation, details are not described herein.
Join Fig. 9, is the cross-sectional view of the encapsulating structure 100b of third embodiment of the invention.
Encapsulating structure 100b includes package substrate 10b, filter chip 20b, several interconnection structure 30b and cofferdam 40b.
Package substrate 10b has the upper surface of base plate 11b and base lower surface 12b being oppositely arranged, base lower surface 12b's
Side has several external pin 121b.
Here, package substrate 10b is the loading plate for carrying chip, and package substrate 10b can be print made of organic resin
Printed circuit board is also possible to glass substrate or ceramic substrate etc..
External pin 121b can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100b
It can be electrically connected with realizations such as other chips or substrates by external pin 121b, here, external pin 121b is with ball bar battle array
For arranging 121b, external pin 121b protrudes out the lower surface of encapsulating structure 100b.
Filter chip 20b has the chip upper surface 21b and chip lower surface 22b being oppositely arranged, chip lower surface 22b
It is arranged face-to-face with upper surface of base plate 11b, chip lower surface 22b has several electrode 221b.
Here, filter chip 20b can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW)
Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20b
Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs
A cavity is formed in the lower section of filter chip 20b to protect the active region.
Electrode 221b protrudes out chip lower surface 22b towards the direction far from chip upper surface 21b, and but not limited to this.
In general, the size of filter chip 20b is less than the size of package substrate 10b.
Several interconnection structure 30b are for being connected several electrode 221b and several external pin 121b.
Cofferdam 40b and chip lower surface 22b and upper surface of base plate 11b cooperates and encloses to set to form cavity S, and cavity S is corresponding
The active region on the surface filter chip 20b.
Here, package substrate 10b has several through-hole 13b passed through for several interconnection structure 30b, if cofferdam 40b is located at
The inside of dry through-hole 13b, interconnection structure 30b include metal column structures 31b, scolding tin 331b and electroplated layer structure 32b, metal column knot
External pin 121b is connected in structure 31b conduction electrode 221b, electroplated layer structure 32b, and scolding tin 331b is for being connected metal column structures 31b
And electroplated layer structure 32b.
Present embodiment by setting cofferdam 40b formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20b in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100b.
In conjunction with Figure 10, several through-hole 13b in array distribution in upper surface of base plate 11b, and between having between adjacent through-holes 13b
Every there is a space, cofferdam 40b is located in the space, and cofferdam 40b is located at the interior of several through-hole 13b between two column through-hole 13b
Side.
Cofferdam 40b is closed cyclic structure, and chip lower surface 22b covers the upper surface of cofferdam 40b, upper surface of base plate
11b covers the lower surface of cofferdam 40b, in this way, cofferdam 40b, chip lower surface 22b and upper surface of base plate 11b are complemented each other to form
Case type cavity S.
There is gap between cofferdam 40b and several through-hole 13b.
Cofferdam 40b is made of photaesthesia insulating materials, and but not limited to this.
In the present embodiment, encapsulating structure 100b further includes coating cofferdam 40b lateral area and filter chip simultaneously
The plastic packaging layer 50b of 20b, and plastic packaging layer 50b is located at side of the package substrate 10b far from base lower surface 12b.
Here, " cofferdam 40b lateral area " refers to all open areas of the side positioned at cofferdam 40b far from cavity S,
That is open area all around plastic packaging layer 50b cladding filter chip 20b, and plastic packaging layer 50b is located at package substrate
The top of 10b.
Plastic packaging layer 50b can be EMC (Epoxy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes
Weir 40b can stop external substance to enter cavity S, without considering whether plastic packaging layer 50b can influence cavity S because of problem of materials
Interior protection zone, therefore, the range of choice of plastic packaging layer 50b material expand significantly, and then can effectively evade specific plastic packaging material
The selection of material substantially widens plastic packaging making technology window and reduces cost.
In the present embodiment, encapsulating structure 100b further includes being set to base lower surface 12b and exposing external pin
The soldermask layer 60b of 121b.
Continue to join Fig. 9 and Figure 10, in the present embodiment, metal column structures 31b includes metal column 311b and conducting metal
The UBM layer 312b of column 311b and electrode 221b, electroplated layer structure 32b include being covered in through-hole 13b inner wall and extending on substrate
Surface 11b, base lower surface 12b plating seed layer 322b and be located at plating seed layer 322b it is outer and with plating seed layer 322b
The electroplated layer 321b being mutually matched, scolding tin 331b cladding metal column 311b simultaneously extend to through-hole 13b and through-hole 13b inner wall are connected
The lower section of electroplated layer 321b, electroplated layer 321b connect external pin 121b.
Plating seed layer 322b and the outer profile of electroplated layer 321b are mutually matched, and plating seed layer 322b is by through-hole 13b
Wall extends to upper surface of base plate 11b and base lower surface 12b respectively, electroplated layer 321b according to plating seed layer 322b laying area
Domain is also extended to upper surface of base plate 11b and base lower surface 12b from through-hole 13b inner wall respectively, and the lower surface of electroplated layer 321b is
Plane.
It should be noted that base lower surface 12b is also equipped with plating seed layer 322b, electricity far from the region of through-hole 13b
Coating 321b and external pin b.
Here, metal column 311b is copper post 311b, and electroplated layer 321b is layers of copper 321b, UBM layer 312b and plating seed layer
322b can be Ti/Cu layers, and but not limited to this.
UBM layer 312b as the transition zone between copper post 311b and electrode 221b, can be effectively reduced copper post 311b at
Type difficulty, improves molding, the fixed effect of copper post 311b, and the electrical transporting between copper post 311b and electrode 221b can be improved
Energy.
Likewise, plating seed layer 322b can effectively be dropped as the transition zone between layers of copper 321b and package substrate 10b
The molding difficulty of low layers of copper 321b improves molding, the fixed effect of layers of copper 321b.
Here, scolding tin 331b is coated on the outside of copper post 311b lower end area, and scolding tin 331b extends downward into through-hole 13b
It is interior, and contact with each other with the layers of copper 321b of through-hole 13b inner wall and realize electric connection, draw so as to conduction electrode 221b with outside
Foot 121b.
The advantage that copper post 311b, scolding tin 331b and through-hole 13b is arranged is: (1) scolding tin 331b is in reflow soldering process
Molten condition convenient for effectively filling through-hole 13b and in conjunction with copper post 311b, and combines effect preferable；(2) scolding tin 331b can be with
The layers of copper 321b of the entire internal perisporium of through-hole 13b contacts with each other, and contact area is big, and electrical transmission performance can be improved, also can be improved
Strong degree of the scolding tin 331b in conjunction with layers of copper 321b；(3) copper post 311b has already taken up a part of space through-hole 13b, at this time in
The raw material usage amount that scolding tin 331b can be reduced in the through-hole 13b when setting scolding tin 331b, reduces the Welder of scolding tin 331b
Skill difficulty shortens weld interval, and then improves welding production capacity；(4) copper post 311b appearance is significant, can be used as identification part with
Recognition efficiency is improved, and then convenient for the detection of automatic aspect and possible defect recognition.
In the present embodiment, the width that electroplated layer structure 32b extends to upper surface of base plate 11b is less than electroplated layer structure
32b extends to the width of base lower surface 12b.
Here, on the one hand, upper surface of base plate 11b and base lower surface 12b is provided with electroplated layer structure 32b, Ke Yiti
Strong degree of the high electroplated layer structure 32b in conjunction with package substrate 10b；On the other hand, the electroplated layer structure of base lower surface 12b
32b width is greater than the electroplated layer structure 32b width of upper surface of base plate 11b, can make the external pin of base lower surface 12b
121b be combined with each other consequently facilitating encapsulating structure 100b is subsequent with other chips or other substrates etc. far from through-hole 13b.
The outer collar region of the upper surface of scolding tin 331b is flushed with the upper surface of electroplated layer structure 32b, electroplated layer structure 32b's
With overlapping region and there is gap between upper surface and the lower surface of electrode 221b, the cross-sectional area of UBM layer 312b is less than
The surface area of electrode 221b, the cross-sectional area of copper post 311b are equal to the cross-sectional area of UBM layer 312b.
It can be seen that UBM layer 312b is laid in the intermediate region of electrode 221b, copper post 311b corresponds to UBM layer 312b setting,
At this point, having gap, the gap between the upper surface of layers of copper 321b and the lower surface of electrode 221b of upper surface of base plate 11b
And its plastic packaging layer 50b is filled in extended segment.
An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100b
Bright and Figure 11, Figure 12 a to Figure 12 w, production method comprising steps of
S1: ginseng Figure 12 a provides filter chip 20b, has the chip upper surface 21b being oppositely arranged and chip following table
Face 22b, chip lower surface 22b have several electrode 221b；
S2: ginseng Figure 12 b to Figure 12 g forms metal column structures 31b in the lower surface of electrode 221b；
It is specific as follows:
Join Figure 12 b, forms UBM layer 312b in chip lower surface 22b；
Join Figure 12 c, forms the first photoresist film 70b in the lower section of UBM layer 312b；
Join Figure 12 d, forms several first hole 71b, the first 71b pairs of hole in the first photoresist film 70b exposure and imaging
Electrode 221b is answered, and the first hole 71b exposes UBM layer 312b；
Join Figure 12 e, in forming several copper post 311b in several first hole 71b；
Join Figure 12 f, removes the first photoresist film 70b；
Join Figure 12 g, removal is exposed to outer UBM layer 312b.
S3: ginseng Figure 12 h provides package substrate 10b, has the upper surface of base plate 11b and base lower surface being oppositely arranged
12b；
S4: ginseng Figure 12 i, in forming several through-hole 13b on package substrate 10b；
S5: ginseng Figure 12 j to Figure 12 o, in through-hole 13b inner wall and upper surface of base plate 11b, the substrate of connection through-hole 13b inner wall
Lower surface 12b forms electroplated layer structure 32b；
It is specific as follows:
Join Figure 12 j, in through-hole 13b inner wall and connects under the part substrate upper surface 11b of through-hole 13b inner wall, whole substrates
Surface 12b forms plating seed layer 322b；
Join Figure 12 k, forms the second photoetching rubber moulding 90b in the lower section of the plating seed layer 322b of base lower surface 12b；
Join Figure 12 l, forms several second hole 91b in the second photoetching rubber moulding 90b exposure and imaging, the second hole 91b is sudden and violent
Expose through-hole 13b and plating seed layer 322b；
Join Figure 12 m, forms layers of copper 321b in being exposed on outer plating seed layer 322b；
Join Figure 12 n, removes the second photoetching rubber moulding 90b；
Join Figure 12 o, removal is exposed to outer plating seed layer 322b.
S6: ginseng Figure 12 p and Figure 12 q forms cofferdam 40b in upper surface of base plate 11b；
It is specific as follows:
Join Figure 12 p, lays photaesthesia insulating film 80b in upper surface of base plate 11b；
Join Figure 12 q, exposure and imaging forms cofferdam 40b, and cofferdam 40b is located at the inside of several through-hole 13b, and cofferdam 40b
There is gap between through-hole 13b.
It should be noted that being formed since independent package substrate 10b can be divided by the large substrates of wafer scale, molding is enclosed
When the 40b of weir, can on large substrates the multiple cofferdam 40b of straight forming, then carry out the segmentation of large substrates again and obtain having single
The single package substrate 10b of a cofferdam 40b, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40b is also plastic to be filtered
On device chip 20b.
Filter chip 20b is assembled to package substrate 10b, chip lower surface 22b and upper surface of base plate by S7: ginseng Figure 12 r
11b is arranged face-to-face, and cofferdam 40b is located at the inside of several through-hole 13b, and table on cofferdam 40b and chip lower surface 22b and substrate
Face 11b cooperates and encloses and set to form cavity S；
S8: ginseng Figure 12 s and Figure 12 t forms conducting metal column structures 31b and electroplated layer knot in the periphery metal column structures 31b
The scolding tin 331b of structure 32b；
It is specific as follows:
Join Figure 12 s, forms plastic packaging layer 50b far from the side of base lower surface 12b in package substrate 10b, plastic packaging layer 50b is same
When cladding cofferdam 40b lateral area and filter chip 20b, several copper post 311b extend towards several through-hole 13b；
Join Figure 12 t, forms scolding tin 331b in the periphery copper post 311b, scolding tin 331b extends to through-hole 13b and through-hole 13b is connected
The layers of copper 321b of inner wall.
S9: ginseng Figure 12 u to Figure 12 w forms external pin 121b below electroplated layer structure 32b.
It is specific as follows:
Join Figure 12 u, in base lower surface 12b formed soldermask layer 60b, soldermask layer 60b coat simultaneously base lower surface 12b,
Layers of copper 321b and scolding tin 331b；
Join Figure 12 v, forms several third hole 61b, third hole 61b exposure copper in soldermask layer 60b exposure and imaging
Layer 321b；
Join Figure 12 w, in formation ball grid array 121b in several third hole 31b.
Other explanations of the production method of the encapsulating structure 100b of present embodiment can refer to above-mentioned encapsulating structure 100b
Explanation, details are not described herein.
Cofferdam 40 (and 40a, 40b) of the invention is located at the inside of through-hole 13, in other embodiments, cofferdam 40
The inside of through-hole 13 and the outside of through-hole 13 can be located at, and the lateral border in cofferdam 40 can be with the lateral border of filter chip 20
It flushes, either, the lateral border in cofferdam 40 can be flushed with the lateral border of package substrate 10, or be the outside in cofferdam 40
Edge is located between the lateral border of filter chip 20 and the lateral border of package substrate 10 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process,
To improve the overall performance of encapsulating structure 100；In addition, there are many forms for the interconnection structure 30 of present embodiment, it can be effective
Electrical transmission performance is improved, the stability of entire encapsulating structure 100 can also be effectively improved.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of chip-packaging structure with single cofferdam and scolding tin characterized by comprising
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, if the side of the base lower surface has
Dry external pin；
Filter chip has the chip upper surface being oppositely arranged and chip lower surface, the chip lower surface and the substrate
Upper surface is arranged face-to-face, and the chip lower surface has several electrodes；
Several interconnection structures, for several electrodes and several external pins to be connected；
Cofferdam cooperates with the chip lower surface and the upper surface of base plate and encloses to set to form cavity；
Wherein, the package substrate has several through-holes passed through for several interconnection structures, and the cofferdam is located at several through-holes
Inside, the interconnection structure include the soldering structure and electroplated layer structure of mutual cooperation interconnection, described in the soldering structure conducting
The external pin is connected in electrode, the electroplated layer structure.
2. encapsulating structure according to claim 1, which is characterized in that the soldering structure includes scolding tin and the conducting weldering
The UBM layer of tin and the electrode, the electroplated layer structure include being covered in the through-hole wall and extending to table on the substrate
It face, the plating seed layer of the base lower surface and is mutually matched outside the plating seed layer and with the plating seed layer
Electroplated layer, the scolding tin extends to the through-hole and the electroplated layer of the through-hole wall is connected.
3. encapsulating structure according to claim 2, which is characterized in that the electroplated layer structure extends to table on the substrate
The width in face is less than the width that the electroplated layer structure extends to the base lower surface.
4. encapsulating structure according to claim 2, which is characterized in that the upper surface of the electroplated layer structure and the UBM
With overlapping region and with gap between the lower surface of layer.
5. encapsulating structure according to claim 2, which is characterized in that the cross-sectional area of the UBM layer is equal to the electricity
The surface area of pole, and the cross-sectional area of the scolding tin is less than the cross-sectional area of the UBM layer.
6. encapsulating structure according to claim 1, which is characterized in that have gap between the cofferdam and several through-holes.
7. encapsulating structure according to claim 1, which is characterized in that the encapsulating structure further includes being located at the encapsulation base
The plastic packaging layer of side of the plate far from the base lower surface, the plastic packaging layer coat the cofferdam lateral area and the filter simultaneously
Wave device chip, and the encapsulating structure further includes being set to the base lower surface and exposing the anti-welding of the external pin
Layer.
8. a kind of production method of the chip-packaging structure with single cofferdam and scolding tin, which is characterized in that comprising steps of
S1: providing filter chip, has the chip upper surface being oppositely arranged and chip lower surface, the chip following table mask
There are several electrodes；
S2: UBM layer is formed in the lower surface of the electrode；
S3: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S4: in forming several through-holes on the package substrate；
S5: electroplated layer structure is formed in the upper surface of base plate of the through-hole wall and the connection through-hole wall, base lower surface；
S6: cofferdam is formed in the upper surface of base plate；
S7: the filter chip is assembled to the package substrate, the chip lower surface is faced with the upper surface of base plate
Face setting, the cofferdam are located at the inside of several through-holes, and the cofferdam and the chip lower surface and the upper surface of base plate
Cooperate and encloses and set to form cavity；
S8: in the scolding tin for forming the conducting electrode and the electroplated layer structure on the UBM layer；
S9: external pin is formed below the electroplated layer structure.
9. the production method of encapsulating structure according to claim 8, which is characterized in that step S5 is specifically included:
Plating kind is formed in the part substrate upper surface of the through-hole wall and the connection through-hole wall, whole base lower surfaces
Sublayer；
The second photoresist film is formed in the lower section of the plating seed layer of the base lower surface, and in second photoresist
Film exposure and imaging forms several second holes, and second hole exposes the through-hole and plating seed layer；
Electroplated layer is formed in being exposed on outer plating seed layer；
Remove the second photoresist film；
Removal is exposed to outer plating seed layer.
10. the production method of encapsulating structure according to claim 9, which is characterized in that step S8, S9 is specifically included:
Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, is enclosed described in the plastic packaging layer while cladding
Weir lateral area and the filter chip, several UBM layers are aligned to several through-holes；
The plastic packaging layer is etched to expose the UBM layer；
In forming scolding tin on the UBM layer, the scolding tin extends to the through-hole and the electroplated layer of the through-hole wall is connected；
Soldermask layer is formed in base lower surface, the soldermask layer coats the base lower surface, the electroplated layer and described simultaneously
Scolding tin；
Several third holes are formed in the soldermask layer exposure and imaging, the third hole exposes the electroplated layer；
In forming ball grid array in several third holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810929729.5A CN109004083A (en) | 2018-08-10 | 2018-08-10 | Chip-packaging structure and preparation method thereof with single cofferdam and scolding tin |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810929729.5A CN109004083A (en) | 2018-08-10 | 2018-08-10 | Chip-packaging structure and preparation method thereof with single cofferdam and scolding tin |
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| CN109004083A true CN109004083A (en) | 2018-12-14 |
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| CN201810929729.5A Pending CN109004083A (en) | 2018-08-10 | 2018-08-10 | Chip-packaging structure and preparation method thereof with single cofferdam and scolding tin |
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