CN109037428A

CN109037428A - Chip-packaging structure and preparation method thereof with double cofferdam

Info

Publication number: CN109037428A
Application number: CN201810911155.9A
Authority: CN
Inventors: 付伟
Original assignee: 付伟
Current assignee: Zhejiang Rongcheng Semiconductor Co., Ltd
Priority date: 2018-08-10
Filing date: 2018-08-10
Publication date: 2018-12-18

Abstract

Present invention discloses a kind of chip-packaging structure and preparation method thereof with double cofferdam, encapsulating structure include: package substrate, and the side of package substrate has several external pins；Filter chip, chip lower surface are arranged face-to-face with upper surface of base plate, and chip lower surface has several electrodes；Several interconnection structures, for several electrodes and several external pins to be connected；Cofferdam, including being located at the first cofferdam on the inside of several electrodes and the second cofferdam on the outside of several electrodes, the first cofferdam and chip lower surface and upper surface of base plate cooperate and enclose to set to form cavity, and the lateral border in the second cofferdam is flushed with the lateral border of filter chip.The present invention forms cavity by setting cofferdam, it is possible to prevente effectively from external substance enters cavity inside and influences the normal use of filter chip in encapsulating structure manufacturing process or in encapsulating structure use process, to improve the overall performance of encapsulating structure.

Description

Chip-packaging structure and preparation method thereof with double cofferdam

Technical field

The present invention relates to field of semiconductor package more particularly to a kind of chip-packaging structures and its production with double cofferdam Method.

Background technique

RF IC (RFIC) is widely used in wireless device, for example, cellular telephone.

RFIC is on matrix the discrete of transmission line, matching network and inductance coil, resistance, capacitor and transistor etc Element is combined together the subsystem for providing and capable of transmitting and receive high-frequency signal, for example, in about 0.1 to 100 gigabits In the range of conspicuous (GHz), the encapsulation of RFIC differs markedly from the encapsulation of digital integrated electronic circuit, because the encapsulation is often radio frequency electrical The a part on road, moreover, because the rf electric field and/or magnetic field energy of RFIC complexity and any neighbouring insulator and conductor are mutual Effect, in order to meet wireless industrial increasing demand, RFIC encapsulation development is tried to provide more small and exquisite, more cheap, performance more High adapts to the device of more bare die radio-frequency modules, while providing higher reliability and using unleaded solder and other " greens " material.The one chip encapsulation that single or multiple bare die RFIC is encapsulated individually is to solve the small size and inexpensive demand of RFIC Direct solution, and be used for most of RFIC now.

Microelectromechanical systems (MEMS) permits the controlled conversion between miniature scale mechanical movement and specified electric signal, For example, consistent with specified frequency, MEMS is being widely used for RFIC.

Based on mechanical movement, RF MEMS is able to achieve fabulous signal quality for radio frequency band filter, and citing comes It says, SAW filter converts electrical signals into mechanical wave, and the latter propagates before its converted back into electric signals along piezo-electric crystal matrix When be delayed by；BAW filter realizes expected special resonance using volume mass motion；And in RF switch, electric signal For controlling the movement of microelectrode, switch is opened or closed.

Present MEMS technology grows up from semiconductor fabrication process, however, mechanical fortune associated with MEMS Dynamic packaging structure and the requirement for requiring to be totally different from traditional semiconductor integrated circuit, specifically, in all MEMS collection Inside circuit, some materials must be moved freely uninterruptedly, and therefore, MEMS integrated circuit must be shielded in movement material Small vacuum or air pocket are formed around material to allow them to move while to protect them.

And in the prior art, a closing and reliable cavity can not be formed to realize the protection of circuit or other structures.

Summary of the invention

The purpose of the present invention is to provide a kind of chip-packaging structure and preparation method thereof with double cofferdam.

One of for achieving the above object, an embodiment of the present invention provides a kind of chip package knot with double cofferdam Structure, comprising:

Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, and the side of the package substrate has Several external pins；

Filter chip, has the chip upper surface that is oppositely arranged and a chip lower surface, the chip lower surface with it is described Upper surface of base plate is arranged face-to-face, and the chip lower surface has several electrodes；

Several interconnection structures, for several electrodes and several external pins to be connected；

Cofferdam, it is described including being located at the first cofferdam on the inside of several electrodes and the second cofferdam on the outside of several electrodes First cofferdam and the chip lower surface and the upper surface of base plate cooperate and enclose to set to form cavity, the outside in second cofferdam Edge is flushed with the lateral border of the filter chip.

As the further improvement of an embodiment of the present invention, there are several outsides to draw for the side of the base lower surface Foot, the package substrate have several through-holes passed through for several interconnection structures.

As the further improvement of an embodiment of the present invention, the interconnection structure includes the metal column interconnected that cooperates The electrode is connected in structure and metal-layer structure, the metal column structures, and the external pin is connected in the metal-layer structure.

As the further improvement of an embodiment of the present invention, the metal column structures include metal column and the conducting gold Belong to the UBM layer of column and the electrode, the metal-layer structure includes metal layer and the conducting metal layer and the metal column Plating seed layer, the metal-layer structure fill the through-hole interior zone and extend to the base lower surface.

As the further improvement of an embodiment of the present invention, the upper surface of the metal-layer structure, which has, accommodates the gold Belong to the groove of rod structure.

As the further improvement of an embodiment of the present invention, the outer collar region of the upper surface of the metal-layer structure is contacted The lower surface of the electrode, and the metal-layer structure connects first cofferdam, the metal close to the side of the cavity Layer structure connects second cofferdam far from the side of the cavity.

As the further improvement of an embodiment of the present invention, several electrodes, which enclose, sets the Internal periphery to be formed connection described first Cofferdam, several electrodes, which enclose, sets the outer profile to be formed connection second cofferdam, and first cofferdam and second cofferdam are mutual Connection.

As the further improvement of an embodiment of the present invention, the encapsulating structure further includes remote positioned at the package substrate The plastic packaging layer of side from the base lower surface, the plastic packaging layer coat second cofferdam lateral border and the filtering simultaneously Device chip, and the encapsulating structure further includes the soldermask layer for being set to the base lower surface and exposing the external pin.

One of for achieving the above object, an embodiment of the present invention provides a kind of chip package knot with double cofferdam The production method of structure, which is characterized in that comprising steps of

S1: providing filter chip, has the chip upper surface being oppositely arranged and chip lower surface, the chip following table Face has several electrodes；

S2: several first interconnection structures are formed in the lower surface of several electrodes；

S3: cofferdam is formed in chip lower surface, the cofferdam includes the first cofferdam being located on the inside of several electrodes and is located at The second cofferdam on the outside of several electrodes；

S4: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；

S5: the filter chip is assembled to the package substrate, the chip lower surface and the upper surface of base plate Setting face-to-face, first cofferdam and the chip lower surface and the upper surface of base plate cooperate and enclose and set to form cavity；

S6: the second interconnection structure that first interconnection structure is connected is formed；

S7: external pin is formed at second interconnection structure.

As the further improvement of an embodiment of the present invention, step S2 is specifically included:

UBM layer and metal column are formed in the lower surface of the electrode；

Step S5 is specifically included:

In forming several through-holes on the package substrate；

The filter chip is assembled to the package substrate, the chip lower surface is faced with the upper surface of base plate Face setting, first cofferdam and the chip lower surface and the upper surface of base plate cooperate and enclose to set to form cavity, and described The lateral border in the second cofferdam is flushed with the lateral border of the filter chip；

Step S6, S7 is specifically included:

Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats institute simultaneously The lateral border and the filter chip in the second cofferdam are stated, several copper posts extend towards several through-holes；

Continuous plating seed layer is formed along the base lower surface, the through-hole wall and the copper post；

The second photoresist layer is formed in the lower section of the plating seed layer, and in the second photoresist layer exposure and imaging Several second holes are formed, second hole exposes the through-hole and plating seed layer；

In fill copper layer is electroplated in several second holes；

Remove the second photoresist layer；

Removal is exposed to outer plating seed layer；

Soldermask layer is formed in base lower surface, the soldermask layer coats the base lower surface and the layers of copper simultaneously；

Several third holes are formed in the soldermask layer exposure and imaging, the third hole exposes the layers of copper；

In forming ball grid array in several third holes.

Compared with prior art, the beneficial effects of the present invention are: present embodiments forms cavity by setting cofferdam, can With effectively avoid in encapsulating structure manufacturing process or in encapsulating structure use process external substance enter cavity inside and The normal use for influencing filter chip, to improve the overall performance of encapsulating structure.

Detailed description of the invention

Fig. 1 is the encapsulating structure cross-sectional view of first embodiment of the invention；

Fig. 2 is the birds-eye perspective of the encapsulating structure part-structure of first embodiment of the invention；

Fig. 3 is the production method block diagram of the encapsulating structure of first embodiment of the invention；

Fig. 4 a- Fig. 4 v is the production method flow chart of the encapsulating structure of first embodiment of the invention；

Fig. 5 is the encapsulating structure cross-sectional view of second embodiment of the invention；

Fig. 6 is the birds-eye perspective of the encapsulating structure part-structure of second embodiment of the invention；

Fig. 7 is the production method block diagram of the encapsulating structure of second embodiment of the invention；

Fig. 8 a- Fig. 8 v is the production method flow chart of the encapsulating structure of second embodiment of the invention；

Fig. 9 is the encapsulating structure cross-sectional view of third embodiment of the invention；

Figure 10 is the birds-eye perspective of the encapsulating structure part-structure of third embodiment of the invention；

Figure 11 is the production method block diagram of the encapsulating structure of third embodiment of the invention；

Figure 12 a- Figure 12 w is the production method flow chart of the encapsulating structure of third embodiment of the invention；

Figure 13 is the encapsulating structure cross-sectional view of four embodiment of the invention；

Figure 14 is the birds-eye perspective of the encapsulating structure part-structure of four embodiment of the invention；

Figure 15 is the production method block diagram of the encapsulating structure of four embodiment of the invention；

Figure 16 a- Figure 16 u is the production method flow chart of the encapsulating structure of four embodiment of the invention.

Specific embodiment

Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally Transformation is included within the scope of protection of the present invention.

In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.

In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty Between relevant description language.

Join Fig. 1, is the cross-sectional view of the chip-packaging structure 100 with double cofferdam of first embodiment of the invention.

Encapsulating structure 100 includes package substrate 10, filter chip 20, several interconnection structures 30 and cofferdam 40.

Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, if the side of substrate 12 has Dry external pin 121.

Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin Circuit board is also possible to glass substrate or ceramic substrate etc..

External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121 For, external pin 121 protrudes out the lower surface of encapsulating structure 100.

In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example Portion's pin 121 may be alternatively located at other regions.

Filter chip 20 has the chip upper surface 21 and chip lower surface 22, chip lower surface 22 and base being oppositely arranged Plate upper surface 11 is arranged face-to-face, and chip lower surface 22 has several electrodes 221.

Here, filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, 20 surface of filter chip Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs A cavity is formed in the lower section of filter chip 20 to protect the active region.

Electrode 221 protrudes out chip lower surface 22 towards the direction far from chip upper surface 21, and but not limited to this.

In general, the size of filter chip 20 is less than the size of package substrate 10.

Several interconnection structures 30 are for being connected several electrodes 221 and several external pins 121.

Cofferdam 40 includes positioned at the first cofferdam 41 of several 221 insides of electrode and positioned at the second of several 221 outsides of electrode Cofferdam 42, the first cofferdam 41 cooperate with chip lower surface 22 and upper surface of base plate 11 and enclose to set to form cavity S, and cavity S is corresponding The lateral border of the active region on 20 surface of filter chip, the second cofferdam 42 is flushed with the lateral border of filter chip 20.

Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus Improve the overall performance of encapsulating structure 100.

In addition, when the lower surface area when cofferdam 40 is too small, may can not be propped up since cofferdam 40 has certain height The cofferdam 40 of the height is supportted, collapsing phenomenon occurs so as to cause cofferdam 40, the cofferdam 40 of present embodiment includes being located at several lead to The first cofferdam 41 and the second cofferdam 42 on the outside of several through-holes 13, cofferdam 40 of 13 inside of hole have sufficiently large following table Face improves the stability in entire cofferdam 40；In addition 40 upper surface of cofferdam can be with the 20 lower surface region cavity S of filter chip Outer 20 lower surface whole region of filter chip combines, and further increases the forming stability of cavity S.

In the present embodiment, the side of base lower surface 12 has several external pins 121, and package substrate 10, which has, to be supplied Several through-holes 13 that several interconnection structures 30 pass through.

It should be noted that " package substrate 10 has several through-holes 13 passed through for several interconnection structures 30 " refers to interconnection At least partly structure of structure 30 passes through corresponding through-hole 13, to realize the interconnection of electrode 221 and external pin 121.

In conjunction with Fig. 2, several electrodes 221 in array distribution in chip lower surface 22, and between having between adjacent electrode 221 Every there is a space, the first cofferdam 41 is located in the space, i.e. the first cofferdam 41 is located at several electrodes between two column electrodes 221 221 inside, the second cofferdam 42 are located at outside the space, i.e. the second cofferdam 42 is located at the outside of several electrodes 221.

That is, several electrodes 221, which enclose, sets the first cofferdam 41 of the Internal periphery to be formed connection, several electrodes 221, which enclose, sets shape At outer profile connect the second cofferdam 42.

It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam 41 be the first cyclic structure, and the first cyclic structure connects the inside of several electrodes 221, and the second cofferdam 42 is the second cyclic structure, Second cyclic structure connects the outside of several electrodes 221.

Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and Between two cofferdam 42 by third cofferdam 43 realize interconnection, third cofferdam 43 positioned at adjacent electrode 221 between or other Region, that is to say, that cofferdam 40 at this time is covered with cavity S periphery, and cofferdam 40 is covered with 221 periphery of electrode.

In the present embodiment, chip lower surface 22 covers the upper surface in the first cofferdam 41 and the upper table in the second cofferdam 42 Face, upper surface of base plate 11 cover the lower surface in the first cofferdam 41 and the lower surface in the second cofferdam 42.

Cofferdam 40 is made of photaesthesia insulating materials, and but not limited to this.

In the present embodiment, encapsulating structure 100 further includes coating 42 lateral border of the second cofferdam and filter chip simultaneously 20 plastic packaging layer 50, and plastic packaging layer 50 is located at side of the package substrate 10 far from base lower surface 12.

That is, plastic packaging layer 50 coats open area all around filter chip 20 at this time.

Plastic packaging layer 50 can be EMC (Expoy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes Weir 40 can stop external substance to enter cavity S, without considering whether plastic packaging layer 50 can influence in cavity S because of problem of materials Protection zone, therefore, the range of choice of 50 material of plastic packaging layer expands significantly, and then can evade the choosing of specific capsulation material It selects, substantially widen plastic packaging making technology window and effectively reduce cost.

In the present embodiment, encapsulating structure 100 further includes being set to base lower surface 12 and exposing external pin 121 Soldermask layer 60.

Continue to join Fig. 1 and Fig. 2, in the present embodiment, interconnection structure 30 includes the metal column structures interconnected that cooperate 31 and metal-layer structure 32, external pin 121 is connected in 31 conduction electrode 221 of metal column structures, metal-layer structure 32.

Specifically, metal column structures 31 include metal column 311 and the UBM layer 312 that metal column 311 and electrode 221 is connected, gold Belonging to layer structure 32 includes metal layer 321 and the plating seed layer 322 that metal layer 321 and metal column 311 is connected, metal-layer structure 32 Filling 13 interior zone of through-hole simultaneously extends to base lower surface 12, and the lower section of metal layer 321 connects external pin 121.

Plating seed layer 322 and the outer profile of metal layer 321 are mutually matched, plating seed layer 322 along 13 inner wall of through-hole to Base lower surface 12 extends, and metal layer 321 is filled through-hole 13 and extended along base lower surface 12, and the lower surface of metal layer 321 is Plane.

It should be noted that base lower surface 12 is also equipped with plating seed layer 322, metal layer far from the region of through-hole 13 321 and external pin 121.

Here, metal column 311 is copper post 311, and metal layer 321 is layers of copper 321, and UBM layer 312 and plating seed layer 322 can Think Ti/Cu layers, but not limited to this.

For UBM layer 312 as the transition zone between copper post 311 and electrode 221, the molding that copper post 311 can be effectively reduced is difficult Degree, improves molding, the fixed effect of copper post 311, and the electrical transmission performance between copper post 311 and electrode 221 can be improved.

Likewise, plating seed layer 322 is as between copper post 311 and layers of copper 321, between layers of copper 321 and package substrate 10 Transition zone, can be effectively reduced the molding difficulty of layers of copper 321, improve molding, the fixed effect of layers of copper 321, and copper can be improved Electrical transmission performance between column 311 and layers of copper 321.

The cross-sectional area of UBM layer 312 is less than the surface area of electrode 221, and the cross-sectional area of copper post 311 is equal to The intermediate region that the cross-sectional area of UBM layer 312, i.e. UBM layer 312 are laid in 221 lower surface of electrode, the corresponding UBM layer of copper post 311 312 settings.

The upper surface of metal-layer structure 32 has the groove 323 for accommodating metal column structures 31, and in the present embodiment, recessed Slot 323 accommodates entire copper post 311 and UBM layer 312.

That is, the lower surface of the outer collar region contact electrode 221 of the upper surface of metal-layer structure 32, i.e., in addition to groove In outside indent form, the upper surface of plating seed layer 322 is contacted with electrode 221 in 323 regions.

Metal-layer structure 32 and electrode 221 enclose the chamber for setting and being formed and accommodating metal column structures 31, and chamber is around metal column knot The surrounding of structure 31.

Here, the advantage that copper post 311, groove 323 and through-hole 13 are equipped with is: (1) 311 phase of groove 323 and copper post Mutually contraposition, groove 323 play position-limiting action to copper post 311, improve aligning accuracy and final products yield in encapsulation process, The difficulty of packaging technology is reduced, and the problem of the position of filter chip 20 is fixed, is not in die drift at this time；(2) Copper post 311 has already taken up a part of space of through-hole 13, can reduce layers of copper when copper electroplating layer 321 in the through-hole 13 at this time 321 plating amount, reduces electroplating technique difficulty, shortens electroplating time, and then improves plating production capacity；(3) copper post 311 Appearance is significant, can be used as identification part to improve recognition efficiency, and then convenient for the detection of automatic aspect and possible defect recognition.

In the present embodiment, the outer profile of the outer profile with electrode 221 of the upper surface of metal-layer structure 32 is mutually matched.

That is, plating seed layer 322 and UBM layer 312 mutually splice and have been covered with the lower surface of electrode 221.

Metal-layer structure 32 connects the first cofferdam 41, side of the metal-layer structure 32 far from cavity S close to the side of cavity S Connect the second cofferdam 42, i.e., be between metal-layer structure 32 and cofferdam 40 at this time it is interconnected, 32 periphery of metal-layer structure does not have There is plastic packaging layer 50.

An embodiment of the present invention also provides a kind of production method of chip-packaging structure with double cofferdam, in conjunction with aforementioned The explanation and Fig. 3, Fig. 4 a to Fig. 4 v of chip-packaging structure 100 with double cofferdam, production method comprising steps of

S1: ginseng Fig. 4 a provides filter chip 20, has the chip upper surface 21 being oppositely arranged and chip lower surface 22, chip lower surface 22 has several electrodes 221；

S2: ginseng Fig. 4 b to Fig. 4 g forms several first interconnection structures in the lower surface of several electrodes 221；

It specifically includes:

Join Fig. 4 b, forms UBM layer 312 in chip lower surface 22；

Join Fig. 4 c, forms the first photoresist layer 70 in the lower section of UBM layer 312；

Join Fig. 4 d, forms several first holes 71, the corresponding electricity of the first hole 71 in 70 exposure and imaging of the first photoresist layer Pole 221, and the first hole 71 exposes UBM layer 312；

Join Fig. 4 e, in forming several copper posts 311 in several first holes 71；

Join Fig. 4 f, removes the first photoresist layer 70；

Join Fig. 4 g, removal is exposed to outer UBM layer 312.

S3: ginseng Fig. 4 h and Fig. 4 i, cofferdam 40 is formed in chip lower surface 22, cofferdam 40 includes being located in several electrodes 221 First cofferdam 41 of side and the second cofferdam 42 on the outside of several electrodes 221；

It specifically includes:

Join Fig. 4 h, lays photaesthesia insulating film 80 in chip lower surface 22；

Join Fig. 4 i, exposure and imaging forms cofferdam 40, and cofferdam 40 includes positioned at the first cofferdam 41 of several 221 insides of electrode And the second cofferdam 42 positioned at several 221 outsides of electrode.

It should be noted that the lateral border in the second cofferdam 42 is flushed with the lateral border of filter chip 20, that is to say, that this When the setting position in the second cofferdam 42 is controlled by the lateral border of filter chip 20, it is convenient and efficient, improve efficiency, and second The control precision of 42 position of cofferdam is high.

S4: ginseng Fig. 4 j provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；

S5: ginseng Fig. 4 k and Fig. 4 l, filter chip 20 is assembled to package substrate 10, table on chip lower surface 22 and substrate Face 11 is arranged face-to-face, and the first cofferdam 41 cooperates with chip lower surface 22 and upper surface of base plate 11 and encloses and set to form cavity S；

It specifically includes:

Join Fig. 4 k, in forming several through-holes 13 on package substrate 10；

Join Fig. 4 l, filter chip 20 is assembled to package substrate 10, chip lower surface 22 is faced with upper surface of base plate 11 Face setting, the first cofferdam 41 cooperates with chip lower surface 22 and upper surface of base plate 11 and encloses to set to form cavity S, and the second cofferdam 42 Lateral border flushed with the lateral border of filter chip 20；

S6: ginseng Fig. 4 m to Fig. 4 s forms the second interconnection structure of the first interconnection structure of conducting；

It specifically includes:

Join Fig. 4 m, forms plastic packaging layer 50 far from the side of base lower surface 12 in package substrate 10, plastic packaging layer 50 wraps simultaneously The lateral border and filter chip 20 in the second cofferdam 42 are covered, several copper posts 311 extend towards several through-holes 13；

Join Fig. 4 n, forms continuous plating seed layer 322 along base lower surface 12,13 inner wall of through-hole and copper post 311；

Join Fig. 4 o, forms the second photoresist layer 90 in the lower section of plating seed layer 322；

Join Fig. 4 p, forms several second holes 91 in 90 exposure and imaging of the second photoresist layer, the exposure of the second hole 91 is logical Hole 13 and plating seed layer 322；

Join Fig. 4 q, in plating fill copper layer 321 in several second holes 91；

Join Fig. 4 r, removes the second photoresist layer 90；

Join Fig. 4 s, removal is exposed to outer plating seed layer 322.

S7: ginseng Fig. 4 t to Fig. 4 v forms external pin 121 at the second interconnection structure.

It specifically includes:

Join Fig. 4 t, forms soldermask layer 60 in base lower surface 12, soldermask layer 60 coats base lower surface 12 and layers of copper simultaneously 321；

Join Fig. 4 u, forms several third holes 61 in 60 exposure and imaging of soldermask layer, third hole 61 exposes layers of copper 321；

Join Fig. 4 v, in formation ball grid array 121 in several third holes 61.

Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100 Bright, details are not described herein.

Join Fig. 5, is the cross-sectional view of the encapsulating structure 100a of second embodiment of the invention.

For ease of description, present embodiment is identical with first embodiment or similar structure uses similar label, Certainly, the structure of like numerals also can have different effects, depending on needing according to the actual situation, below other embodiments And in this way, subsequent repeat no more.

Encapsulating structure 100a includes package substrate 10a, filter chip 20a, several interconnection structure 30a and cofferdam 40a.

Package substrate 10a has the upper surface of base plate 11a and base lower surface 12a being oppositely arranged, base lower surface 12a's Side has several external pin 121a.

Here, package substrate 10a is the loading plate for carrying chip, and package substrate 10a can be print made of organic resin Printed circuit board is also possible to glass substrate or ceramic substrate etc..

External pin 121a can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100a It can be electrically connected with realizations such as other chips or substrates by external pin 121a, here, external pin 121a is with ball bar battle array For arranging 121a, external pin 121a protrudes out the lower surface of encapsulating structure 100a.

Filter chip 20a has the chip upper surface 21a and chip lower surface 22a being oppositely arranged, chip lower surface 22a It is arranged face-to-face with upper surface of base plate 11a, chip lower surface 22a has several electrode 221a.

Here, filter chip 20a can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20a Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs A cavity is formed in the lower section of filter chip 20a to protect the active region.

Electrode 221a protrudes out chip lower surface 22a towards the direction far from chip upper surface 21a, and but not limited to this.

In general, the size of filter chip 20a is less than the size of package substrate 10a.

Several interconnection structure 30a are for being connected several electrode 221a and several external pin 121a.

Cofferdam 40a includes positioned at the first cofferdam 41a of the inside of several electrode 221a and on the outside of several electrode 221a The second cofferdam 42a, the first cofferdam 41a and chip lower surface 22a and upper surface of base plate 11a cooperation and enclose to set to form cavity S, should The active region on the surface cavity S respective filter chip 20a, the lateral border of the second cofferdam 42a and the outside of filter chip 20a Edge flushes.

Here, package substrate 10a has several through-hole 13a passed through for several interconnection structure 30a, interconnection structure 30a packet Include the soldering structure 33a and electroplated layer structure 32a of the interconnection that cooperates, soldering structure 33a electric conduction 221a, electroplated layer structure External pin 121a is connected in 32a.

It should be noted that " package substrate 10a has several through-hole 13a passed through for several interconnection structure 30a " refers to At least partly structure of interconnection structure 30a passes through corresponding through-hole 13a, to realize that electrode 221a's and external pin 121a is mutual Even.

Present embodiment by setting cofferdam 40a formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or It is that external substance enters the normal use for inside cavity S and influencing filter chip 20a in encapsulating structure use process, thus Improve the overall performance of encapsulating structure 100a.

In addition, since cofferdam 40a has certain height, it, may can not when the lower surface area of cofferdam 40a is too small The cofferdam 40a of the height is supported, collapsing phenomenon occurs so as to cause cofferdam 40a, if the cofferdam 40a of present embodiment includes being located at The first cofferdam 41a on the inside of dry through-hole 13a and the second cofferdam 42a on the outside of several through-hole 13a, cofferdam 40a have enough Big lower surface improves the stability of entire cofferdam 40a；In addition the upper surface cofferdam 40a can be with filter chip 20a following table Filter chip 20a lower surface whole region outside the region cavity S of face combines, and further increases the forming stability of cavity S.

In conjunction with Fig. 6, several electrode 221a have in array distribution in chip lower surface 22a, and between adjacent electrode 221a It is spaced, there is a space between two column electrode 221a, the first cofferdam 41a is located in the space, i.e. the first cofferdam 41a is located at several The inside of electrode 221a, the second cofferdam 42a are located at outside the space, i.e. the second cofferdam 42a is located at the outside of several electrode 221a.

That is, several electrode 221a, which enclose, sets the Internal periphery to be formed the first cofferdam 41a of connection, several electrode 221a, which enclose, to be set The outer profile of formation connects the second cofferdam 42a.

It should be noted that can be independent from each other between the first cofferdam 41a and the second cofferdam 42a, such as first encloses Weir 41a is the first cyclic structure, and the first cyclic structure connects the inside of several electrode 221a, and the second cofferdam 42a is second cyclic annular Structure, the second cyclic structure connect the outside of several electrode 221a.

Certainly, be also possible between the first cofferdam 41a and the second cofferdam 42a it is interconnected, at this point, the first cofferdam 41a Between the second cofferdam 42a by third cofferdam 43a realize interconnection, third cofferdam 43a between adjacent electrode 221a or Person is other regions, that is to say, that cofferdam 40a at this time is covered with cavity S periphery, and cofferdam 40a is covered with electrode 221a periphery.

In the present embodiment, chip lower surface 22a cover the first cofferdam 41a upper surface and the second cofferdam 42a it is upper Surface, upper surface of base plate 11a cover the lower surface of the first cofferdam 41a and the lower surface of the second cofferdam 42a.

Cofferdam 40a is made of photaesthesia insulating materials, and but not limited to this.

In the present embodiment, encapsulating structure 100a further includes coating the second cofferdam 42a lateral border and filter core simultaneously The plastic packaging layer 50a of piece 20a, and plastic packaging layer 50a is located at side of the package substrate 10a far from base lower surface 12a.

That is, plastic packaging layer 50a coats open area all around filter chip 20a at this time.

Plastic packaging layer 50a can be EMC (Expoy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes Weir 40a can stop external substance to enter cavity S, without considering whether plastic packaging layer 50a can influence cavity S because of problem of materials Interior protection zone, therefore, the range of choice of plastic packaging layer 50a material expand significantly, and then can evade specific capsulation material Selection is substantially widened plastic packaging making technology window and is effectively reduced cost.

In the present embodiment, encapsulating structure 100a further includes being set to base lower surface 12a and exposing external pin The soldermask layer 60a of 121a.

Continue join Fig. 5 and Fig. 6, in the present embodiment, soldering structure 33a include scolding tin 331a and conducting scolding tin 331a and The UBM layer 312a of electrode 221a, electroplated layer structure 32a include be covered in through-hole 13a inner wall and extend to upper surface of base plate 11a, It the plating seed layer 322a of base lower surface 12a and is mutually matched outside plating seed layer 322a and with plating seed layer 322a Electroplated layer 321a, scolding tin 331a extends to through-hole 13a and the electroplated layer 321a of through-hole 13a inner wall is connected, electroplated layer 321a's Lower section connects external pin 121a.

Plating seed layer 322a and the outer profile of electroplated layer 321a are mutually matched, and plating seed layer 322a is by through-hole 13a Wall extends to upper surface of base plate 11a and base lower surface 12a respectively, electroplated layer 321a according to plating seed layer 322a laying area Domain is also extended to upper surface of base plate 11a and base lower surface 12a from through-hole 13a inner wall respectively, and the lower surface of electroplated layer 321a is Plane.

It should be noted that base lower surface 12a is also equipped with plating seed layer 322a, electricity far from the region of through-hole 13a Coating 321a and external pin 121a.

Here, it can be Ti/Cu layers that electroplated layer 321a, which is layers of copper 321a, UBM layer 312a and plating seed layer 322a, but not As limit.

UBM layer 312a as the transition zone between scolding tin 331a and electrode 221a, can be effectively reduced scolding tin 331a at Type difficulty, improves molding, the fixed effect of scolding tin 331a, and the electrical transporting between scolding tin 331a and electrode 221a can be improved Energy.

Likewise, plating seed layer 322a can effectively be dropped as the transition zone between layers of copper 321a and package substrate 10a The molding difficulty of low layers of copper 321a improves molding, the fixed effect of layers of copper 321a.

Here, scolding tin 331a is extended in through-hole 13a by UBM layer 312a, and mutual with the layers of copper 321a of through-hole 13a inner wall Contact, which is realized, to be electrically connected, so as to conduction electrode 221a and external pin 121a.

Scolding tin 331a is arranged, the advantage of through-hole 13a is: (1) scolding tin 331a is molten condition in reflow soldering process, just In effectively filling through-hole 13a and in conjunction with UBM layer 312a, and combine effect preferable；(2) scolding tin 331a can be whole with through-hole 13a The layers of copper 321a of a internal perisporium contacts with each other, and contact area is big, and electrical transmission performance can be improved, also can be improved scolding tin 331a with The strong degree that layers of copper 321a is combined；(3) reflow soldering process that scolding tin 331a is used is succinct, and high production efficiency can be greatly reduced into It produces cost and shortens the product delivery cycle.

In the present embodiment, the width that electroplated layer structure 32a extends to upper surface of base plate 11a is less than electroplated layer structure 32a extends to the width of base lower surface 12a.

Here, on the one hand, upper surface of base plate 11a and base lower surface 12a is provided with electroplated layer structure 32a, Ke Yiti Strong degree of the high electroplated layer structure 32a in conjunction with package substrate 10a；On the other hand, the electroplated layer structure of base lower surface 12a 32a width is greater than the electroplated layer structure 32a width of upper surface of base plate 11a, can make the external pin of base lower surface 12a 121a be combined with each other consequently facilitating encapsulating structure 100a is subsequent with other chips or other substrates etc. far from through-hole 13a.

It is connected between the upper surface and UBM layer 312a of electroplated layer structure 32a by scolding tin 331a.

Lateral border positioned at the electroplated layer structure 32a of upper surface of base plate 11a, the upper surface positioned at electroplated layer structure 32a with The lateral border of the lateral border of scolding tin 331a between UBM layer 312a, the lateral border of UBM layer 321a and electrode 221a is mutually flush.

It can be seen that connection UBM layer 312a scolding tin 331a extends not only toward the direction through-hole 13a, also towards electroplated layer knot Extend in gap between the upper surface and UBM layer 312a of structure 32a, and when the upper table of scolding tin 331a filling electroplated layer structure 32a When gap between face and UBM layer 312a, interconnection structure 30a between the first cofferdam 41a and the second cofferdam 42a (including Electroplated layer structure 32a positioned at upper surface of base plate 11a, the weldering between the upper surface and UBM layer 312a positioned at electroplated layer structure 32a Tin 331a and UBM layer 321a) four peripheries be plane, and any cross-sectional area of interconnection structure 30a be equal to electrode The surface area of 221a.

At this point, UBM layer 312a is covered with the lower surface area of electrode 221a, and the upper area of scolding tin 331a (is located at plating Scolding tin 331a between the upper surface and UBM layer 312a of layer structure 32a) it is covered with the lower surface area of UBM layer 312a.

Electroplated layer structure 32a, scolding tin 331a and UBM layer 312a connect the first cofferdam 41a, plating close to the side of cavity S Layer structure 32a, scolding tin 331a and UBM layer 312a connect the second cofferdam 42a far from the side of cavity S, at this point, electroplated layer structure 32a periphery does not have plastic packaging layer 50a.

An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100a Bright and Fig. 7, Fig. 8 a to Fig. 8 v, production method comprising steps of

S1: ginseng Fig. 8 a provides filter chip 20a, has the chip upper surface 21a being oppositely arranged and chip lower surface 22a, chip lower surface 22a have several electrode 221a；

S2: ginseng Fig. 8 b to Fig. 8 f forms UBM layer 312a in the lower surface of electrode 221a；

It specifically includes:

Join Fig. 8 b, forms UBM layer 312a in chip lower surface 22a；

Join Fig. 8 c, forms the first photoresist layer 70a in the lower section of UBM layer 312a；

Join Fig. 8 d, forms several first hole 71a in the first photoresist layer 70a exposure and imaging, the first hole 71a is corresponding Other regions of electrode 221a are removed, and the first hole 71a exposes UBM layer 312a；

Join Fig. 8 e, the UBM layer 312a that the first hole 71a of etching exposes；

Join Fig. 8 f, removes the first photoresist layer 70a.

S3: ginseng Fig. 8 g and Fig. 8 h, cofferdam 40a is formed in chip lower surface 22a, cofferdam 40a includes being located at several electrodes The first cofferdam 41a on the inside of 221a and the second cofferdam 42a on the outside of several electrode 221a；

It specifically includes:

Join Fig. 8 g, lays photaesthesia insulating film 80a in chip lower surface 22a；

Join Fig. 8 h, exposure and imaging forms cofferdam 40a, and cofferdam 40a includes first enclosing on the inside of several electrode 221a Weir 41a and the second cofferdam 42a on the outside of several electrode 221a.

It should be noted that the lateral border of the second cofferdam 42a is flushed with the lateral border of filter chip 20a, that is to say, that The setting position of the second cofferdam 42a is controlled by the lateral border of filter chip 20a at this time, it is convenient and efficient, it improves efficiency, and The control precision in the second cofferdam position 42a is high.

S4: ginseng Fig. 8 i provides package substrate 10a, has the upper surface of base plate 11a and base lower surface being oppositely arranged 12a；

S5: ginseng Fig. 8 j, in forming several through-hole 13a on package substrate 10a；

S6: ginseng Fig. 8 k to Fig. 8 p in through-hole 13a inner wall and connects under the upper surface of base plate 11a of through-hole 13a inner wall, substrate Surface 12a forms electroplated layer structure 32a；

It specifically includes:

Join Fig. 8 k, in the part substrate upper surface 11a of through-hole 13a inner wall and connection through-hole 13a inner wall, whole substrate following tables Face 12a forms plating seed layer 322a；

Join Fig. 8 l, forms the second photoresist layer 90a in the lower section of the plating seed layer 322a of base lower surface 12a；

Join Fig. 8 m, the second photoresist layer 90a exposure and imaging forms several second hole 91a, and the second hole 91a exposure is logical Hole 13a and plating seed layer 322a；

Join Fig. 8 n, forms layers of copper 321a in being exposed on outer plating seed layer 322a；

Join Fig. 8 o, removes the second photoresist layer 90a；

Join Fig. 8 p, removal is exposed to outer plating seed layer 322a.

Filter chip 20a is assembled to package substrate 10a, chip lower surface 22a and upper surface of base plate by S7: ginseng Fig. 8 q 11a is arranged face-to-face, and the first cofferdam 41a and chip lower surface 22a and upper surface of base plate 11a cooperate and enclose to set to form cavity S, and The lateral border of second cofferdam 42a is flushed with the lateral border of filter chip 20a；

S8: ginseng Fig. 8 r and Fig. 8 s, in the scolding tin for forming conduction electrode 221a and electroplated layer structure 32a on UBM layer 312a 331a；

It specifically includes:

Join Fig. 8 r, forms plastic packaging layer 50a far from the side of base lower surface 12a in package substrate 10a, plastic packaging layer 50a is same When coat the lateral border of the second cofferdam 42a and filter chip 20a, several UBM layer 312a are aligned to several through-hole 13a；

Join Fig. 8 s, in forming scolding tin 331a on UBM layer 312a, scolding tin 331a extends to through-hole 13a and is connected in through-hole 31a The layers of copper 321a of wall.

S9: ginseng Fig. 8 t to Fig. 8 v forms external pin 121a below electroplated layer structure 32a.

It specifically includes:

Join Fig. 8 t, forms soldermask layer 60a in base lower surface 12a, soldermask layer 60a coats base lower surface 12a, copper simultaneously Layer 321a and scolding tin 331a；

Join Fig. 8 u, forms several third hole 61a in soldermask layer 60a exposure and imaging, third hole 61a exposes layers of copper 321a；

Join Fig. 8 v, in formation ball grid array 121a in several third hole 61a.

Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100a Bright, details are not described herein.

Join Fig. 9, is the cross-sectional view of the encapsulating structure 100b of third embodiment of the invention.

Encapsulating structure 100b includes package substrate 10b, filter chip 20b, several interconnection structure 30b and cofferdam 40b.

Package substrate 10b has the upper surface of base plate 11b and base lower surface 12b being oppositely arranged, base lower surface 12b's Side has several external pin 121b.

Here, package substrate 10b is the loading plate for carrying chip, and package substrate 10b can be print made of organic resin Printed circuit board is also possible to glass substrate or ceramic substrate etc..

External pin 121b can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100b It can be electrically connected with realizations such as other chips or substrates by external pin 121b, here, external pin 121b is with ball bar battle array For arranging 121b, external pin 121b protrudes out the lower surface of encapsulating structure 100b.

Filter chip 20b has the chip upper surface 21b and chip lower surface 22b being oppositely arranged, chip lower surface 22b It is arranged face-to-face with upper surface of base plate 11b, chip lower surface 22b has several electrode 221b.

Here, filter chip 20b can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20b Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs A cavity is formed in the lower section of filter chip 20b to protect the active region.

Electrode 221b protrudes out chip lower surface 22b towards the direction far from chip upper surface 21b, and but not limited to this.

In general, the size of filter chip 20b is less than the size of package substrate 10b.

Several interconnection structure 30b are for being connected several electrode 221b and several external pin 121b.

Cofferdam 40b includes the first cofferdam 41b on the inside of several electrodes and the second cofferdam on the outside of several electrodes 42b, the first cofferdam 41b and chip lower surface 22b and upper surface of base plate 11b cooperate and enclose to set to form cavity S, and cavity S is corresponding The lateral border of the active region on the surface filter chip 20b, the second cofferdam 42b is flushed with the lateral border of filter chip 20b.

Here, package substrate 10b has several through-hole 13b passed through for several interconnection structure 30b, interconnection structure 30b packet Include metal column structures 31b, scolding tin 331b and electroplated layer structure 32b, metal column structures 31b conduction electrode 221b, electroplated layer structure External pin 121b is connected in 32b, and scolding tin 331b is for being connected metal column structures 31b and electroplated layer structure 32b.

It should be noted that " package substrate 10b has several through-hole 13b passed through for several interconnection structure 30b " refers to At least partly structure of interconnection structure 30b passes through corresponding through-hole 13b, to realize that electrode 221b's and external pin 121b is mutual Even.

Present embodiment by setting cofferdam 40b formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or It is that external substance enters the normal use for inside cavity S and influencing filter chip 20b in encapsulating structure use process, thus Improve the overall performance of encapsulating structure 100b.

In addition, since cofferdam 40b has certain height, it, may can not when the lower surface area of cofferdam 40b is too small The cofferdam 40b of the height is supported, collapsing phenomenon occurs so as to cause cofferdam 40b, if the cofferdam 40b of present embodiment includes being located at The first cofferdam 41b on the inside of dry through-hole 13b and the second cofferdam 42b on the outside of several through-hole 13b, cofferdam 40b have enough Big lower surface improves the stability of entire cofferdam 40b；In addition the upper surface cofferdam 40b can be with filter chip 20b following table Filter chip 20b lower surface whole region outside the region cavity S of face combines, and further increases the forming stability of cavity S.

In conjunction with Fig. 6, several electrode 221b have in array distribution in chip lower surface 22b, and between adjacent electrode 221b It is spaced, there is a space between two column electrode 221b, the first cofferdam 41b is located in the space, i.e. the first cofferdam 41b is located at several The inside of electrode 221b, the second cofferdam 42b are located at outside the space, i.e. the second cofferdam 42b is located at the outside of several electrode 221b.

That is, several electrode 221b, which enclose, sets the Internal periphery to be formed the first cofferdam 41b of connection, several electrode 221b, which enclose, to be set The outer profile of formation connects the second cofferdam 42b.

It should be noted that can be independent from each other between the first cofferdam 41b and the second cofferdam 42b, such as first encloses Weir 41b is the first cyclic structure, and the first cyclic structure connects the inside of several electrode 221b, and the second cofferdam 42b is second cyclic annular Structure, the second cyclic structure connect the outside of several electrode 221b.

Certainly, be also possible between the first cofferdam 41b and the second cofferdam 42b it is interconnected, at this point, the first cofferdam 41b Between the second cofferdam 42b by third cofferdam 43b realize interconnection, third cofferdam 43b between adjacent electrode 221b or Person is other regions, that is to say, that cofferdam 40b at this time is covered with cavity S periphery, and cofferdam 40b is covered with electrode 221b periphery.

In the present embodiment, chip lower surface 22b cover the first cofferdam 41b upper surface and the second cofferdam 42b it is upper Surface, upper surface of base plate 11b cover the lower surface of the first cofferdam 41b and the lower surface of the second cofferdam 42b.

Cofferdam 40b is made of photaesthesia insulating materials, and but not limited to this.

In the present embodiment, encapsulating structure 100b further includes coating the second cofferdam 42b lateral border and filter core simultaneously The plastic packaging layer 50b of piece 20b, and plastic packaging layer 50b is located at side of the package substrate 10b far from base lower surface 12b.

That is, plastic packaging layer 50b coats open area all around filter chip 20b at this time.

Plastic packaging layer 50b can be EMC (Expoy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes Weir 40b can stop external substance to enter cavity S, without considering whether plastic packaging layer 50b can influence cavity S because of problem of materials Interior protection zone, therefore, the range of choice of plastic packaging layer 50b material expand significantly, and then can evade specific capsulation material Selection is substantially widened plastic packaging making technology window and is effectively reduced cost.

In the present embodiment, encapsulating structure 100b further includes being set to base lower surface 12b and exposing external pin The soldermask layer 60b of 121b.

Continue to join Fig. 9 and Figure 10, in the present embodiment, metal column structures 31b includes metal column 311b and conducting metal The UBM layer 312b of column 311b and electrode 221b, electroplated layer structure 32b include being covered in through-hole 13b inner wall and extending on substrate Surface 11b, base lower surface 12b plating seed layer 322b and be located at plating seed layer 322b it is outer and with plating seed layer 322b The electroplated layer 321b being mutually matched, scolding tin 331b cladding metal column 311b simultaneously extend to through-hole 13b and through-hole 13b inner wall are connected The lower section of electroplated layer 321b, electroplated layer 321b connect external pin 121b.

Plating seed layer 322b and the outer profile of electroplated layer 321b are mutually matched, and plating seed layer 322b is by through-hole 13b Wall extends to upper surface of base plate 11b and base lower surface 12b respectively, electroplated layer 321b according to plating seed layer 322b laying area Domain is also extended to upper surface of base plate 11b and base lower surface 12b from through-hole 13b inner wall respectively, and the lower surface of electroplated layer 321b is Plane.

It should be noted that base lower surface 12b is also equipped with plating seed layer 322b and electricity far from the region of through-hole 13b Coating 321b.

Here, metal column 311b is copper post 311b, and electroplated layer 321b is layers of copper 321b, UBM layer 312b and plating seed layer 322b can be Ti/Cu layers, and but not limited to this.

UBM layer 312b as the transition zone between copper post 311b and electrode 221b, can be effectively reduced copper post 311b at Type difficulty, improves molding, the fixed effect of copper post 311b, and the electrical transporting between copper post 311b and electrode 221b can be improved Energy.

Likewise, plating seed layer 322b can effectively be dropped as the transition zone between layers of copper 321b and package substrate 10b The molding difficulty of low layers of copper 321b improves molding, the fixed effect of layers of copper 321b.

Here, scolding tin 331b is coated on the outside of copper post 311b lower end area, and scolding tin 331b extends downward into through-hole 13b It is interior, and contact with each other with the layers of copper 321b of through-hole 13b inner wall and realize electric connection, draw so as to conduction electrode 221b with outside Foot 121b.

The advantage that copper post 311b, scolding tin 331b and through-hole 13b is arranged is: (1) scolding tin 331b is in reflow soldering process Molten condition convenient for effectively filling through-hole 13b and in conjunction with copper post 311b, and combines effect preferable；(2) scolding tin 331b can be with The layers of copper 321b of the entire internal perisporium of through-hole 13b contacts with each other, and contact area is big, and electrical transmission performance can be improved, also can be improved Strong degree of the scolding tin 331b in conjunction with layers of copper 321b；(3) copper post 311b has already taken up a part of space through-hole 13b, at this time in The raw material usage amount that scolding tin 331b can be reduced in the through-hole 13b when setting scolding tin 331b, reduces the Welder of scolding tin 331b Skill difficulty shortens weld interval, and then improves welding production capacity；(4) copper post 311b appearance is significant, can be used as identification part with Recognition efficiency is improved, and then convenient for the detection of automatic aspect and possible defect recognition.

In the present embodiment, the width that electroplated layer structure 32b extends to upper surface of base plate 11b is less than electroplated layer structure 32b extends to the width of base lower surface 12b.

Here, on the one hand, upper surface of base plate 11b and base lower surface 12b is provided with electroplated layer structure 32b, Ke Yiti The strong degree that high electroplated layer structure 32b is combined with package substrate 10；On the other hand, the electroplated layer structure 32b of base lower surface 12b Width is greater than the electroplated layer structure 32b width of upper surface of base plate 11b, can make the external pin 121b of base lower surface 12b Far from through-hole 13b, it be combined with each other consequently facilitating encapsulating structure 100b is subsequent with other chips or other substrates etc..

It is connected between the upper surface and electrode 221b of electroplated layer structure 32b by scolding tin 331b.

Lateral border positioned at the electroplated layer structure 32b of upper surface of base plate 11b, the upper surface positioned at electroplated layer structure 32b with The lateral border of scolding tin 331b between electrode 221b and the lateral border of electrode 221b are mutually flush.

It can be seen that the lower surface of scolding tin 331b connection electrode 221b and coating UBM layer 312b and copper post 311b simultaneously, i.e., Scolding tin 331b connection is the region electrode 221b around UBM layer 312b.

The scolding tin 331b of connection electrode 221b extends not only toward the direction through-hole 13b, also towards the upper of electroplated layer structure 32b Extend in gap between surface and electrode 221b, and when the upper surface of scolding tin 331b filling electroplated layer structure 32b and electrode When gap between 221b, interconnection structure 30b between the first cofferdam 41b and the second cofferdam 42b (including be located on substrate The electroplated layer structure 32b of the surface 11b and scolding tin 331b between the upper surface and electrode 221b of electroplated layer structure 32b) Four peripheries be plane, and any cross-sectional area of interconnection structure 30b be equal to electrode 221b surface area.

At this point, UBM layer 312b is laid in the intermediate region of the lower surface electrode 221b, copper post 321b corresponds to UBM layer 312b and sets It sets, and the upper area of scolding tin 331b and UBM layer 312b mutually splice and the lower surface of discontented electrode 221b.

Electroplated layer structure 32b and scolding tin 331b close to cavity S side connect the first cofferdam 41b, electroplated layer structure 32b and Scolding tin 331b connects the second cofferdam 42b far from the side of cavity S, at this point, electroplated layer structure 32b periphery does not have plastic packaging layer 50a.

An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100b Bright and Figure 11, Figure 12 a to Figure 12 w, production method comprising steps of

S1: ginseng Figure 12 a provides filter chip 20b, has the chip upper surface 21b being oppositely arranged and chip following table Face 22b, chip lower surface 22b have several electrode 221b；

S2: ginseng Figure 12 b to Figure 12 g forms metal column structures 31b in the lower surface of electrode 221b；

It specifically includes:

Join Figure 12 b, forms UBM layer 312b in chip lower surface 22b；

Join Figure 12 c, forms the first photoresist layer 70b in the lower section of UBM layer 312b；

Join Figure 12 d, the first photoresist layer 70b exposure and imaging forms several first hole 71b, and the first hole 71b is corresponding Electrode 221b, and the first hole 71b exposes UBM layer 312b；

Join Figure 12 e, in forming several copper post 311b in several first hole 71b；

Join Figure 12 f, removes the first photoresist layer 70b；

Join Figure 12 g, removal is exposed to outer UBM layer 312b.

S3: ginseng Figure 12 h and Figure 12 i, cofferdam 40b is formed in chip lower surface 22b, cofferdam 40b includes being located at several electrodes The first cofferdam 41b on the inside of 221b and the second cofferdam 42b on the outside of several electrode 221b；

It specifically includes:

Join Figure 12 h, lays photaesthesia insulating film 80b in chip lower surface 22b；

Join Figure 12 i, exposure and imaging forms cofferdam 40b, and cofferdam 40b includes first enclosing on the inside of several electrode 221b Weir 41b and the second cofferdam 42b on the outside of several electrode 221b.

It should be noted that the lateral border of the second cofferdam 42b is flushed with the lateral border of filter chip 20b, that is to say, that The setting position of the second cofferdam 42b is controlled by the lateral border of filter chip 20b at this time, it is convenient and efficient, it improves efficiency, and The control precision in the second cofferdam position 42b is high.

S4: ginseng Figure 12 j provides package substrate 10b, has the upper surface of base plate 11b and base lower surface being oppositely arranged 12b；

S5: ginseng Figure 12 k, in forming several through-hole 13b on package substrate 10b；

S6: ginseng Figure 12 l to Figure 12 q, in through-hole 13b inner wall and upper surface of base plate 11b, the substrate of connection through-hole 13b inner wall Lower surface 12b forms electroplated layer structure 32b；

It specifically includes:

Join Figure 12 l, in through-hole 13b inner wall and connects under the part substrate upper surface 11b of through-hole 13b inner wall, whole substrates Surface 12b forms plating seed layer 322b；

Join Figure 12 m, forms the second photoresist layer 90b in the lower section of the plating seed layer 322b of base lower surface 12b；

Join Figure 12 n, forms several second hole 91b in the second photoresist layer 90b exposure and imaging, the second hole 91b is sudden and violent Expose through-hole 13b and plating seed layer 322b；

Join Figure 12 o, forms layers of copper 321b in being exposed on outer plating seed layer 322b；

Join Figure 12 p, removes the second photoresist layer 90b；

Join Figure 12 q, removal is exposed to outer plating seed layer 322b.

Filter chip 20b is assembled to package substrate 10b, chip lower surface 22b and upper surface of base plate by S7: ginseng Figure 12 r 11b is arranged face-to-face, and the first cofferdam 41b and chip lower surface 22b and upper surface of base plate 11b cooperate and enclose to set to form cavity S, and The lateral border of second cofferdam 42b is flushed with the lateral border of filter chip 20b；

S8: ginseng Figure 12 s and Figure 12 t forms conducting metal column structures 32b and electroplated layer knot in the periphery metal column structures 32b The scolding tin 331b of structure 32b；

It specifically includes:

Join Figure 12 s, forms plastic packaging layer 50b far from the side of base lower surface 12b in package substrate 10b, plastic packaging layer 50b is same When coat the lateral border and filter chip 20b of the second cofferdam 42b；

Join Figure 12 t, form scolding tin 331b, scolding tin 331b connection electrode 221b in the periphery of copper post 311b and UBM layer 312b, And scolding tin 331b extends to through-hole 13b and the layers of copper 321b of through-hole 13b inner wall is connected.

S9: ginseng Figure 12 u to Figure 12 w forms external pin 121b below electroplated layer structure 32b.

It specifically includes:

Join Figure 12 u, in base lower surface 12b formed soldermask layer 60b, soldermask layer 60b coat simultaneously base lower surface 12b, Layers of copper 321b and scolding tin 331b；

Join Figure 12 v, forms several third hole 61b, third hole 61b exposure copper in soldermask layer 60b exposure and imaging Layer 321b；

Join Figure 12 w, in formation ball grid array 121b in several third hole 61b.

Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100b Bright, details are not described herein.

Join Figure 13, is the cross-sectional view of the encapsulating structure 100c of four embodiment of the invention.

Encapsulating structure 100c includes package substrate 10c, filter chip 20c, several metal-layer structure 32c and cofferdam 40c.

Package substrate 10c has the upper surface of base plate 11c and base lower surface 12c being oppositely arranged, base lower surface 12c's There is several external pin 121c, package substrate 10c to have several through-hole 13c for side.

Here, package substrate 10c is the loading plate for carrying chip, and package substrate 10c can be print made of organic resin Printed circuit board is also possible to glass substrate or ceramic substrate etc..

External pin 121c can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100c It can be electrically connected with realizations such as other chips or substrates by external pin 121c, here, external pin 121c is with ball bar battle array For arranging 121c, external pin 121c protrudes out the lower surface of encapsulating structure 100c.

Filter chip 20c has the chip upper surface 21c and chip lower surface 22c being oppositely arranged, chip lower surface 22c It is arranged face-to-face with upper surface of base plate 11c, chip lower surface 22c has several electrode 221c.

Here, filter chip 20c can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20c Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs A cavity is formed in the lower section of filter chip 20c to protect the active region.

Electrode 221c protrudes out chip lower surface 22c towards the direction far from chip upper surface 21c, and but not limited to this.

In general, the size of filter chip 20c is less than the size of package substrate 10c.

Several metal-layer structure 32c pass through several through-hole 13c and several electrode 221c and several external pin 121c are connected.

It should be noted that " several metal-layer structure 32c pass through several through-hole 13c " refers to metal-layer structure 32c extremely Small part structure passes through corresponding through-hole 13c, to realize the interconnection of electrode 221c and external pin 121c.

Cofferdam 40c includes the first cofferdam 41c on the inside of several electrodes and the second cofferdam on the outside of several electrodes 42c, the first cofferdam 41c and chip lower surface 22c and upper surface of base plate 11c cooperate and enclose to set to form cavity S, and cavity S is corresponding The lateral border of the active region on the surface filter chip 20c, the second cofferdam 42c is flushed with the lateral border of filter chip 20c.

Present embodiment by setting cofferdam 40c formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or It is that external substance enters the normal use for inside cavity S and influencing filter chip 20c in encapsulating structure use process, thus Improve the overall performance of encapsulating structure 100c.

In addition, since cofferdam 40c has certain height, it, may can not when the lower surface area of cofferdam 40c is too small The cofferdam 40c of the height is supported, collapsing phenomenon occurs so as to cause cofferdam 40c, if the cofferdam 40c of present embodiment includes being located at The first cofferdam 41c on the inside of dry through-hole 13c and the second cofferdam 42c on the outside of several through-hole 13c, cofferdam 40c have enough Big lower surface improves the stability of entire cofferdam 40c；In addition the upper surface cofferdam 40c can be with filter chip 20c following table Filter chip 20c lower surface whole region outside the region cavity S of face combines, and further increases the forming stability of cavity S.

In conjunction with Figure 14, several electrode 221c have in array distribution in chip lower surface 22c, and between adjacent electrode 221c It is spaced, there is a space between two column electrode 221c, the first cofferdam 41c is located in the space, i.e. the first cofferdam 41c is located at several The inside of electrode 221c, the second cofferdam 42c are located at outside the space, i.e. the second cofferdam 42c is located at the outside of several electrode 221c.

That is, several electrode 221c, which enclose, sets the Internal periphery to be formed the first cofferdam 41c of connection, several electrode 221c, which enclose, to be set The outer profile of formation connects the second cofferdam 42c.

It should be noted that can be independent from each other between the first cofferdam 41c and the second cofferdam 42c, such as first encloses Weir 41c is the first cyclic structure, and the first cyclic structure connects the inside of several electrode 221c, and the second cofferdam 42c is second cyclic annular Structure, the second cyclic structure connect the outside of several electrode 221c.

Certainly, be also possible between the first cofferdam 41c and the second cofferdam 42c it is interconnected, at this point, the first cofferdam 41c Between the second cofferdam 42c by third cofferdam 43c realize interconnection, third cofferdam 43c between adjacent electrode 221c or Person is other regions, that is to say, that cofferdam 40c at this time is covered with cavity S periphery, and cofferdam 40c is covered with electrode 221c periphery.

In the present embodiment, chip lower surface 22c cover the first cofferdam 41c upper surface and the second cofferdam 42c it is upper Surface, upper surface of base plate 11c cover the lower surface of the first cofferdam 41c and the lower surface of the second cofferdam 42c.

Cofferdam 40c is made of photaesthesia insulating materials, and but not limited to this.

In the present embodiment, encapsulating structure 100c further includes coating the second cofferdam 42c lateral border and filter core simultaneously The plastic packaging layer 50c of piece 20c, and plastic packaging layer 50c is located at side of the package substrate 10c far from base lower surface 12c.

That is, plastic packaging layer 50c coats open area all around filter chip 20c at this time.

Plastic packaging layer 50c can be EMC (Expoy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes Weir 40c can stop external substance to enter cavity S, without considering whether plastic packaging layer 50c can influence cavity S because of problem of materials Interior protection zone, therefore, the range of choice of plastic packaging layer 50c material expand significantly, and then can evade specific capsulation material Selection is substantially widened plastic packaging making technology window and is effectively reduced cost.

In the present embodiment, encapsulating structure 100c further includes being set to base lower surface 12c and exposing external pin The soldermask layer 60c of 121c.

Continue to join Figure 13 and Figure 14, in the present embodiment, metal-layer structure 32c includes being located at below electrode 221c UBM layer 312c, metal layer 321c and the plating seed layer 322c between UBM layer 312c and metal layer 321c, metal layer 321c and plating seed layer 322c filling through-hole 13c interior zone simultaneously extends to base lower surface 12c, and under metal layer 321c Side's connection external pin 121c.

Plating seed layer 322c and the outer profile of metal layer 321c are mutually matched, and plating seed layer 322c is along through-hole 13c Wall extends to base lower surface 12c, and metal layer 321c fills through-hole 13c and extends along base lower surface 12c, metal layer 321c's Lower surface is plane.

It is Full connected, i.e. plating seed layer between the upper surface of plating seed layer 322c and the lower surface of UBM layer 312c The upper surface of 322c is in the same plane, and is face face Full connected between plating seed layer 322c and UBM layer 312c.

It should be noted that base lower surface 12c is also equipped with plating seed layer 322c and gold far from the region of through-hole 13c Belong to layer 321c.

Here, metal layer 321c is layers of copper 321c, and UBM layer 312c, plating seed layer 322c can be Ti/Cu layers, but not As limit.

Plating kind can be effectively reduced as the transition zone between plating seed layer 322c and electrode 221c in UBM layer 312c The molding difficulty of sublayer 322c improves the molding of plating seed layer 322c, fixed effect, and can be improved plating seed layer 322c with Electrical transmission performance between electrode 221c.

Plating seed layer 322c is as between UBM layer 312c and layers of copper 321c, between layers of copper 321c and package substrate 10c The molding difficulty of layers of copper 321c can be effectively reduced in transition zone, improves molding, the fixed effect of layers of copper 321c, and electricity can be improved Electrical transmission performance between pole 221c and layers of copper 321c.

Here, electrode 221c and external pin are directly realized by UBM layer 312c, plating seed layer 322c and layers of copper 321c The electric connection of 121c, it is advantageous that: electrode 221c and the connection structure of external pin 121c are simple, and envelope can be effectively reduced The difficulty for filling technique, improves efficiency.

In the present embodiment, the upper surface area of metal-layer structure 32c is equal to the cross-sectional area of UBM layer 312c, and UBM layer 312c iso-cross-section area is equal to the surface area of electrode 221b.

Metal-layer structure 32c connects the first cofferdam 41c close to the side of cavity S, and metal-layer structure 32c is far from cavity S's Side connects the second cofferdam 42c, at this point, metal-layer structure 32c periphery does not have plastic packaging layer 50c.

An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100c Bright and Figure 15, Figure 16 a to Figure 16 u, production method comprising steps of

S1: ginseng Figure 16 a provides filter chip 20c, has the chip upper surface 21c being oppositely arranged and chip following table Face 22c, chip lower surface 22c have several electrode 221c；

S2: ginseng Figure 16 b to Figure 16 f forms UBM layer 312c in the lower surface of electrode 221c；

It specifically includes:

Join Figure 16 b, forms UBM layer 312c in chip lower surface 22c；

Join Figure 16 c, forms the first photoresist layer 70c in the lower section of UBM layer 312c；

Join Figure 16 d, forms several first hole 71c, the first 71c pairs of hole in the first photoresist layer 70c exposure and imaging Other regions of electrode 221c should be removed, and the first hole 71c exposes UBM layer 312c；

Join Figure 16 e, the UBM layer 312c that the first hole 71c of etching exposes；

Join Figure 16 f, removes the first photoresist layer 70c.

S3: ginseng Figure 16 g and Figure 16 h, cofferdam 40c is formed in chip lower surface 22c, cofferdam 40c includes being located at several electrodes The first cofferdam 41c on the inside of 221c and the second cofferdam 42c on the outside of several electrode 221c；

It specifically includes:

Join Figure 16 g, lays photaesthesia insulating film 80c in chip lower surface 22c；

Join Figure 16 h, exposure and imaging forms cofferdam 40c, and cofferdam 40c includes first enclosing on the inside of several electrode 221c Weir 41c and the second cofferdam 42c on the outside of several electrode 221c.

It should be noted that the lateral border of the second cofferdam 42c is flushed with the lateral border of filter chip 20c, that is to say, that The setting position of the second cofferdam 42c is controlled by the lateral border of filter chip 20c at this time, it is convenient and efficient, it improves efficiency, and The control precision in the second cofferdam position 42c is high.

S4: ginseng Figure 16 i provides package substrate 10c, has the upper surface of base plate 11c and base lower surface being oppositely arranged 12c；

S5: ginseng Figure 16 j, in forming several through-hole 13c on package substrate 10c；

Filter chip 20c is assembled to package substrate 10c, chip lower surface 22c and upper surface of base plate by S6: ginseng Figure 16 k 11c is arranged face-to-face, and the first cofferdam 41c and chip lower surface 22c and upper surface of base plate 11c cooperate and enclose to set to form cavity S, and The lateral border of second cofferdam 42b is flushed with the lateral border of filter chip 20b；

S7: ginseng Figure 16 l to Figure 16 r forms the plating seed layer 322c and metal layer 321c of conducting UBM layer 312c, plating Seed layer 322c and metal layer 321c at least partially by through-hole 13c；

It specifically includes:

Join Figure 16 l, forms plastic packaging layer 50c far from the side of base lower surface 12c in package substrate 10c, plastic packaging layer 50c is same When coat the lateral border and filter chip 20c of the second cofferdam 42c, several electrode 221c are directed at several through-hole 13c；

Join Figure 16 m, forms continuous plating seed layer along base lower surface 12c, through-hole 13c inner wall and UBM layer 312c 322c；

Join Figure 16 n, forms the second photoresist layer 90c in the lower section of plating seed layer 322c；

Join Figure 16 o, forms several second hole 91c in the second photoresist layer 90c exposure and imaging, the second hole 91c is sudden and violent Reveal through-hole 13c and plating seed layer 322c；

Join Figure 16 p, in plating fill copper layer 321c in several second hole 91c；

Join Figure 16 q, removes the second photoresist layer 90c；

Join Figure 16 r, removal is exposed to outer plating seed layer 322c.

S8: ginseng Figure 16 s to Figure 16 u forms external pin 121c below metal-layer structure 32c.

It specifically includes:

Join Figure 16 s, in base lower surface 12c formed soldermask layer 60c, soldermask layer 60c coat simultaneously base lower surface 12c and Layers of copper 321c；

Join Figure 16 t, forms several third hole 61c, third hole 61c exposure copper in soldermask layer 60c exposure and imaging Layer 321c；

Join Figure 16 u, in formation ball grid array 121c in several third hole 61c.

Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100c Bright, details are not described herein.

Cofferdam 40 (and 40a, 40b) of the invention is located at the inside and outside of electrode 221, and the outside in the second cofferdam 42 Edge is flushed with the lateral border of filter chip 20, and in other embodiments, cofferdam 40 may be alternatively located at the inside of electrode 221, or The lateral border of person, the second cofferdam 42 can be flushed with the lateral border of package substrate 10, or be, the lateral border in the second cofferdam 42 Between the lateral border of filter chip 20 and the lateral border of package substrate 10 etc..

To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, To improve the overall performance of encapsulating structure 100；In addition, there are many forms for the interconnection structure 30 of present embodiment, it can be effective Electrical transmission performance is improved, the stability of entire encapsulating structure 100 can also be effectively improved.

It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book With the other embodiments of understanding.

The series of detailed descriptions listed above only for feasible embodiment of the invention specifically Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention Or change should all be included in the protection scope of the present invention.

Claims

1. a kind of chip-packaging structure with double cofferdam characterized by comprising

Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the side of the package substrate has several External pin；

Filter chip has the chip upper surface being oppositely arranged and chip lower surface, the chip lower surface and the substrate Upper surface is arranged face-to-face, and the chip lower surface has several electrodes；

Cofferdam, including be located at several electrodes on the inside of the first cofferdam and the second cofferdam on the outside of several electrodes, described first Cofferdam and the chip lower surface and upper surface of base plate cooperation and enclose to set to form cavity, the lateral border in second cofferdam with The lateral border of the filter chip flushes.

2. encapsulating structure according to claim 1, which is characterized in that the side of the base lower surface has several outsides Pin, the package substrate have several through-holes passed through for several interconnection structures.

3. encapsulating structure according to claim 2, which is characterized in that the interconnection structure includes the gold interconnected that cooperates Belong to rod structure and metal-layer structure, the electrode is connected in the metal column structures, and the metal-layer structure is connected the outside and draws Foot.

4. encapsulating structure according to claim 3, which is characterized in that the metal column structures include metal column and conducting institute The UBM layer of metal column and the electrode is stated, the metal-layer structure includes metal layer and the conducting metal layer and the metal The plating seed layer of column, the metal-layer structure fill the through-hole interior zone and extend to the base lower surface.

5. encapsulating structure according to claim 4, which is characterized in that the upper surface of the metal-layer structure, which has, accommodates institute State the groove of metal column structures.

6. encapsulating structure according to claim 4, which is characterized in that the outer collar region of the upper surface of the metal-layer structure The lower surface of the electrode is contacted, and the metal-layer structure connects first cofferdam close to the side of the cavity, it is described Metal-layer structure connects second cofferdam far from the side of the cavity.

7. encapsulating structure according to claim 1, which is characterized in that several electrodes, which enclose, to be set described in the Internal periphery to be formed connection First cofferdam, several electrodes, which enclose, sets the outer profile to be formed connection second cofferdam, first cofferdam and second cofferdam It is interconnected.

8. encapsulating structure according to claim 1, which is characterized in that the encapsulating structure further includes being located at the encapsulation base The plastic packaging layer of side of the plate far from the base lower surface, the plastic packaging layer coat second cofferdam lateral border and described simultaneously Filter chip, and the encapsulating structure further includes being set to the base lower surface and exposing the anti-welding of the external pin Layer.

9. a kind of production method of the chip-packaging structure with double cofferdam, which is characterized in that comprising steps of

S1: providing filter chip, has the chip upper surface being oppositely arranged and chip lower surface, the chip following table mask There are several electrodes；

S3: cofferdam is formed in chip lower surface, the cofferdam includes the first cofferdam being located on the inside of several electrodes and is located at several The second cofferdam on the outside of electrode；

S5: the filter chip is assembled to the package substrate, the chip lower surface is faced with the upper surface of base plate Face setting, first cofferdam and the chip lower surface and the upper surface of base plate cooperate and enclose and set to form cavity；

S7: external pin is formed at second interconnection structure.

10. the production method of encapsulating structure according to claim 9, which is characterized in that

Step S2 is specifically included:

UBM layer and metal column are formed in the lower surface of the electrode；

Step S5 is specifically included:

In forming several through-holes on the package substrate；

The filter chip is assembled to the package substrate, the chip lower surface is set face-to-face with the upper surface of base plate It sets, first cofferdam and the chip lower surface and the upper surface of base plate cooperate and enclose to set to form cavity, and described second The lateral border in cofferdam is flushed with the lateral border of the filter chip；

Step S6, S7 is specifically included:

Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats described the simultaneously The lateral border in two cofferdam and the filter chip, several copper posts extend towards several through-holes；

The second photoresist layer is formed in the lower section of the plating seed layer, and is formed in the second photoresist layer exposure and imaging Several second holes, second hole expose the through-hole and plating seed layer；

In fill copper layer is electroplated in several second holes；

Remove the second photoresist layer；

Removal is exposed to outer plating seed layer；

In forming ball grid array in several third holes.