CN107331625A - Encapsulating structure of semiconductor devices and preparation method thereof - Google Patents
Encapsulating structure of semiconductor devices and preparation method thereof Download PDFInfo
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- CN107331625A CN107331625A CN201710416795.8A CN201710416795A CN107331625A CN 107331625 A CN107331625 A CN 107331625A CN 201710416795 A CN201710416795 A CN 201710416795A CN 107331625 A CN107331625 A CN 107331625A
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- chip
- weld pad
- cofferdam
- cover plate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 230000008707 rearrangement Effects 0.000 claims description 8
- 238000010897 surface acoustic wave method Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052710 silicon Inorganic materials 0.000 abstract description 21
- 239000010703 silicon Substances 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000001125 extrusion Methods 0.000 description 4
- 238000001914 filtration Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 235000008434 ginseng Nutrition 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- -1 lamination Plate Polymers 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a kind of encapsulating structure of semiconductor devices and preparation method thereof, the encapsulating structure includes the chip in non-functional face containing functional surfaces and corresponding thereto, the functional surfaces of chip contain the functional areas positioned at middle part and some weld pads positioned at surrounding, also include one can photoetching cover plate, it is bonded together between cover plate front and the functional surfaces of chip by cofferdam, cofferdam is around functional areas.Wherein, cofferdam is covered on the weld pad on functional areas periphery, and the cover plate back side is formed through cover plate and cofferdam and the conductive structure electrically connected with the weld pad of chip.Or, cofferdam is between functional areas and weld pad, and weld pad is electrically connected by metal lead wire or soldered ball with the external world.Cover plate of the present invention bonds together to form cavity by being lithographically formed with cofferdam, replaces existing silicon cover plate or High Resistivity Si cover plate, can save the TSV process costs of Silicon Wafer, can reduce by more than 30% CT Cycle Time, reduces by more than 30% expense.
Description
Technical field
The present invention relates to semiconductor package, especially a kind of functional areas need the semiconductor devices of cavity working environment
Encapsulating structure and preparation method thereof.
Background technology
Some semiconductor devices, function element needs cavity as working environment, so being needed in encapsulation process plus a lid
Plate, and form cavity in function element area.By taking sound surface filtering equipment as an example, because of properties of product and design function demand, it is necessary to
Ensure that filtering chip functional area does not contact any material, i.e. chip functions area and needs to provide the working environment of cavity.Sound surface
Wave filter does substrate, its size is smaller for current chip wafer using lithium tantalate as substrate with special material, only 4 cun
Or 6 cun of wafer outputs.For matching encapsulation ability, yield is improved, package dimension is reduced, chip is typically reassembled into large-sized crystalline substance
Circle, using wafer-level packaging.
Patent 201610158823.6 discloses a kind of restructuring wafer, and is filtered with silicon or high resistant Silicon Wafer as surface acoustic wave
The cover plate of ripple device (Saw Filter), then silicon hole TSV is on silicon cover plate, the weld pad of exposed chip uses metallic circuit afterwards
Weld pad is electrically guided into surface by silicon hole.High Resistivity Si cost is higher, and making silicon hole processing procedure is complicated on silicon cover plate, and into
This height.Silicon is semiconductor material, and its upper berth circuit must also do insulating Design.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of reduction encapsulation procedure, reduction production cost, improves product
Encapsulating structure of semiconductor devices of reliability and preparation method thereof.
The technical proposal of the invention is realized in this way：
A kind of encapsulating structure of semiconductor devices, includes the chip in non-functional face containing functional surfaces and corresponding thereto, institute
The functional surfaces for stating chip contain the functional areas positioned at middle part and some weld pads positioned at surrounding, it is characterised in that：Also include one to gather
The cover plate of compound material, the cover plate is positive to be bonded together between the functional surfaces of the chip by cofferdam, the cofferdam
On the weld pad for being covered in the functional areas periphery, the cover plate back side be formed through cover plate and cofferdam and with the chip
The conductive structure of weld pad electrical connection；
Or, the cofferdam is between the functional areas and the weld pad, and the weld pad passes through metal lead wire or soldered ball
Electrically connected with the external world.
Further, the cover plate of polymeric material is dry film material, the dielectric constant of the dry film material higher than 2,
Resistivity is higher than 1000 Ω cm, rigid>4GPa.
Further, the cofferdam is dry film material or photoresist, and the height in the cofferdam is 5 μm -15 μm.
Further, the cover sheet thickness is 30~60um.
Further, the chip is surface acoustic wave filtering chip.
A kind of preparation method of the encapsulating structure of semiconductor devices, comprises the following steps：
A., semiconductor chip die is provided, the wafer some single chips are cut into, the chip has function
Face and non-functional face corresponding thereto, the functional surfaces of the chip have the functional areas positioned at middle part and some welderings positioned at periphery
Pad；
B., one wafer support plate is provided, by each chip rearrangement on the wafer support plate, restructuring wafer is formed, wherein,
The non-functional face of each chip is bonded on the wafer support plate by Heraeus, faces outwardly the function of each chip, adjacent chips
Between have gap；
C. each chip outer surface after bonding lays one layer of first dry film or photoresist, to first dry film or photoresist
Perform etching or photoetching, form the functional areas around each chip and expose the cofferdam of the weld pad of its corresponding chip；
D. one layer of second dry film is pasted in the cofferdam upper surface of each chip, second dry film is performed etching or photoetching, shape
Into the cover plate for the weld pad for covering on each chip and exposing chip；
E. the weld pad for exposing chip it is electrical cover plate outer surface is led to by conductive structure after, by the chip with
The wafer support plate solution bonding；Or, after the chip is bonded with the wafer support plate solution, the electricity for the weld pad that chip is exposed
Property leads to external circuit by metal lead wire or soldered ball.
Further, between the cofferdam of each chip formed in step c is included on the inside of the functional areas of chip and weld pad
Weld pad in cofferdam and extend out to chip edge from cofferdam in the weld pad and only expose cofferdam outside the weld pad of weld pad；And step d
The cover plate of middle formation includes being bonded in the weld pad inner cover plate in covering function area on cofferdam in the weld pad and from the weld pad inner cover plate
Extend out to the weld pad outer cover plate that chip edge only exposes weld pad；Shape in the opening of the cover plate of each chip and cofferdam exposure weld pad
Into the conductive structure for having electrical connection weld pad, the conductive structure is electrically led to weld pad on the outer surface of cover plate.
Further, the cofferdam of each chip formed in step c is only included between the functional areas of chip and weld pad inner side
Between weld pad in cofferdam；And the cover plate formed in step d the only weldering including being bonded in covering function area on cofferdam in the weld pad
Pad inner cover plate；The weld pad of each chip exposure is electrically connected by metal lead wire or soldered ball with the external world.
The beneficial effects of the invention are as follows：The invention provides a kind of encapsulating structure of semiconductor devices and preparation method thereof,
Using can the polymeric material cover plate of photoetching replace existing silicon cover plate or High Resistivity Si cover plate, bond together to form cavity with cofferdam, such as,
Using can the dry film material (one kind of polymeric material) of photoetching make cover plate, the TSV process costs of silicon wafer closing disk can be saved；
Using the dry film of high-k high resistivity, the insulating materials between cavity and metallic circuit can be saved, and for radio frequency
For product, it can shield because of the signal interference that silicon chip is brought；Dry film material has special rigid in itself, it is possible to reduce can
In being tested by property, the product failure risk brought by the rigid extrusion stretching that thermal coefficient of expansion different band is come.The present invention is from product
Encapsulation procedure angle, can reduce by more than 30% CT Cycle Time；From product cost angle, it can reduce by more than 30% expense；From production
Quality measuring angle, improves reliability.
Brief description of the drawings
Fig. 1 recombinates the signal of wafer to form each chip rearrangement on wafer support plate in one embodiment of the invention
Figure；
Fig. 2 is that the schematic diagram of the first dry film is laid on each chip of restructuring wafer in one embodiment of the invention；
Fig. 3 is the first dry film on each chip to be performed etching or is lithographically formed the signal in cofferdam in one embodiment of the invention
Figure；
Fig. 4 is that the schematic diagram of the second dry film is laid on cofferdam in one embodiment of the invention；
Fig. 5 is the second dry film to be performed etching or is lithographically formed the schematic diagram of cover plate in one embodiment of the invention；
Fig. 6 is the conductive structure that electrical connection weld pad is formed with the cover plate outer surface of each chip in one embodiment of the invention
Schematic diagram；
Fig. 7 is that one embodiment of the invention middle berth is set up defences and layer and makes the schematic diagram of solder bump；
Fig. 8 be one embodiment of the invention in separate the semiconductor devices formed after each chip encapsulating structure schematic diagram；
Fig. 9 be another embodiment of the present invention in restructuring wafer each chip on lay the first dry film and etching or photoetching shape
Into the schematic diagram in cofferdam；
Figure 10 is that the schematic diagram of the second dry film is laid on cofferdam in another embodiment of the present invention；
Figure 11 is the second dry film to be performed etching or is lithographically formed the schematic diagram of cover plate in another embodiment of the present invention；
Figure 12 be another embodiment of the present invention in separate each chip and the schematic diagram fitted with circuit board；
Figure 13 be another embodiment of the present invention in by the weld pad of chip and circuit board progress play the schematic diagram that metal wire is connected；
100-chip, 110- functional surfaces, the non-functional faces of 120-, 101-weld pad, 200- wafer support plates, 300- first is dry
Outside film, 301- cofferdam, the dry films of 400- second, 401- cover plates, 500- conductive structures, 600- welding resisting layers, 700- solder bumps, 280-
Portion's circuit, 800- metal wires
Embodiment
More obvious understandable to enable the invention to, the embodiment to the present invention does detailed below in conjunction with the accompanying drawings
Explanation.For convenience of description, each part is not scaled by normal rates in the structure of embodiment accompanying drawing, therefore is not represented in embodiment
The actual relative size of each structure.
Embodiment one
Referring to Fig. 8, a kind of encapsulating structure of semiconductor devices, including containing functional surfaces 110 and corresponding thereto non-functional
The chip 100 in face 120, the functional surfaces of the chip contain the functional areas positioned at middle part and some weld pads 101 positioned at surrounding, also
Including one can photoetching polymeric material cover plate 401, the cover plate front the functional surfaces of chip between lead to cofferdam 301 is bonded in
Together, cofferdam surrounds functional areas, and covers weld pad, is formed through cover plate and cofferdam at the cover plate back side, and with the weld pad of chip
The conductive structure 500 of electrical connection.The conductive structure directly contacts cover plate and cofferdam.So, cover plate is by being lithographically formed, with cofferdam
Cavity is bonded together to form, replaces existing silicon cover plate or High Resistivity Si cover plate, the TSV process costs of Silicon Wafer can be saved, from product envelope
Processing procedure angle is filled, can reduce by more than 30% CT Cycle Time, from product cost angle, can reduce by more than 30% expense.
It is preferred that, the cover plate of polymeric material is dry film material, and the dielectric constant of the dry film material is higher than 2, such as
3,4,5, resistivity is higher than 1000 Ω cm, such as 1000~2000 Ω cm, rigid>4GPa.Dry film material insulation property
Well.The dry film of high-k high resistivity is selected, the insulating materials between cavity and metallic circuit can be saved, and for
For radio frequency products, it can shield because of the signal interference that silicon chip is brought；Dry film material has special rigid in itself, can subtract
In few reliability testing, the product failure risk brought by the rigid extrusion stretching that thermal coefficient of expansion different band is come, that is to say, that
From product quality angle, reliability is improved.
It is preferred that, the cofferdam is dry film material or photoresist, in other embodiment, and cofferdam can also be plastics, lamination
Plate, thermosetting resin.5 μm to 15 μm, preferably 10 to 12 μm of cofferdam height.In other embodiment, chip can be that image is passed
Sensor chip, MEMS, fingerprint recognition chip etc., cofferdam height can be between 5 μm to 600 μm.
It is preferred that, the cover sheet thickness is 30~60um.
As a kind of preferred embodiment, the preparation method of the encapsulating structure of the semiconductor devices is as follows：
A., semiconductor chip die is provided, the wafer some single chips 100 are cut into, the chip has work(
Can face 110 and non-functional face 120 corresponding thereto, the functional surfaces of the chip have the functional areas that are located at middle part and positioned at periphery
Some weld pads 101；
B. referring to Fig. 1 there is provided a wafer support plate 200, by each chip rearrangement on the wafer support plate, restructuring is formed
Wafer, wherein, the non-functional face of each chip is bonded on the wafer support plate by Heraeus, makes the functional surfaces court of each chip
Outside, there is gap between adjacent chips；When it is implemented, can be by each chip rearrangement on 8 inch or 12 inch wafer support plates, core
There are about 5 μm~5000 μm wide gaps between piece.The wafer support plate is used to support each chip to carry out wafer-level packaging, such as, can
Support the wafer-level packaging of 15000 chips.
C. referring to Fig. 2, each chip outer surface after bonding lays one layer of first dry film or photoresist 300, to this first
Dry film or photoresist are performed etching or photoetching, are formed the functional areas around each chip and are exposed enclosing for the weld pad of its corresponding chip
Weir 301, referring to Fig. 3；The cofferdam of each chip is including cofferdam in the weld pad between the functional areas of chip and weld pad inner side and certainly
Cofferdam extends out to the outer cofferdam of weld pad that chip edge only exposes weld pad in the weld pad；Here, between chip above gap
First dry film can retain, and also can remove.Preferably 5 μm to 15 μm of the thickness of first dry film.
D. referring to Fig. 4, one layer of second dry film 400 is pasted in the cofferdam upper surface of each chip, the second thickness of dry film about 30~
60um.Second dry film is performed etching or photoetching, the cover plate 401 for the weld pad for covering on each chip and exposing chip, ginseng is formed
See Fig. 5；Cover plate include be bonded in covering function area on cofferdam in the weld pad weld pad inner cover plate and from the weld pad inner cover plate to
Extend to the weld pad outer cover plate that chip edge only exposes weld pad outside；The cover plate insulating properties being lithographically formed by dry film are good, and it is situated between
Electric constant is higher than 2.Resistivity is higher than 1000 Ω cm.Photoetching cover plate rigid is higher than 4GPa.So, can save cavity with
Insulating materials between metallic circuit, and for radio frequency products, can shield because of the signal interference that silicon chip is brought；Dry film material
Material has special rigid in itself, it is possible to reduce in reliability testing, because the rigidity extruding that thermal coefficient of expansion different band is come is drawn
Stretch the product failure risk brought, that is to say, that from product quality angle, improve reliability.
E. the weld pad for exposing chip it is electrical cover plate outer surface is led to by conductive structure 500 after, by chip with
Wafer support plate solution is bonded；
It particularly may be divided into following steps：
Referring to Fig. 6, the conductive structure of electrical connection weld pad is formed with the opening of the cover plate of each chip and cofferdam exposure weld pad
500, the conductive structure is electrically led to weld pad on the outer surface of cover plate, passes through the metallic circuit rearrangement chip at the back side
Electrical exit.
Referring to Fig. 7, welding resisting layer 600 is equipped with the metallic circuit at the cover plate back side, it is electrical that welding resisting layer exposes metallic circuit
The position of exit, makes solder bump 700 at the position.
Referring to Fig. 8, separation forms single encapsulation chip.Can be dry by etching or the dry film of photoetching first in preceding step and second
During film, while removing the first dry film and the second dry film above chip gap, it is directly separated.Or after the completion of above-mentioned steps, it is single
Solely single chip is separated into using blade cutting；Remove the wafer support plate of bonding.
Embodiment two
Referring to Figure 13, a kind of encapsulating structure of semiconductor devices, including containing functional surfaces 110 and corresponding thereto non-functional
The chip 100 in face 120, the functional surfaces of the chip contain the functional areas positioned at middle part and some weld pads 101 positioned at surrounding, also
Including one can photoetching cover plate 401, the cover plate front the functional surfaces of chip between lead to cofferdam 301 is bonded together, cofferdam is enclosed
Around functional areas, and positioned between functional areas and weld pad, weld pad is connected by metal lead wire with external circuit (circuit board).At other
In embodiment, weld pad can be also connected by soldered ball with the external world.So, cover plate bonds together to form cavity by being lithographically formed with cofferdam,
Replace existing silicon cover plate or High Resistivity Si cover plate, the TSV process costs of Silicon Wafer can be saved, can from product encapsulation procedure angle
The CT Cycle Time of reduction more than 30%, from product cost angle, can reduce by more than 30% expense.
It is preferred that, the cover plate is dry film material, and the dielectric constant of the dry film material is higher than 2, such as 3,4,5, resistivity
Higher than 1000 Ω cm, such as 1000~2000 Ω cm, rigid>4GPa.Dry film material insulation property is good.Select Gao Jie
The dry film of electric constant high resistivity, can save the insulating materials between cavity and metallic circuit, and for radio frequency products,
It can shield because of the signal interference that silicon chip is brought；Dry film material has special rigid in itself, it is possible to reduce reliability testing
In, the product failure risk brought by the rigid extrusion stretching that thermal coefficient of expansion different band is come, that is to say, that from product quality angle
Degree, improves reliability.
It is preferred that, the cofferdam is dry film material or photoresist, in other embodiment, and cofferdam can also be plastics, lamination
Plate, thermosetting resin.5 μm to 15 μm, preferably 10 to 12 μm of cofferdam height.In other embodiment, chip can be that image is passed
Sensor chip, MEMS, fingerprint recognition chip etc., cofferdam height can be between 5 μm to 600 μm.
It is preferred that, the cover sheet thickness is 30~60um.
As a kind of preferred embodiment, the chip in the encapsulating structure is surface acoustic wave filtering chip, and so its application is not limited
In this, in other embodiment, the encapsulating structure, which can be applied to various chip functions areas, to be needed to provide partly leading for cavity working environment
Body device, for example, relate to photoelectric cell (opto-electronic devices), MEMS (Micro Electro
Mechanical System；MEMS), microfluid system (micro fluidic systems) or utilization heat, light and pressure
Physics sensor (Physical Sensor) measured Deng physical quantity variation etc..
As a kind of preferred embodiment, the preparation method of the encapsulating structure of the semiconductor devices is as follows：
A., semiconductor chip die is provided, the wafer some single chips 100 are cut into, the chip has work(
Can face 110 and non-functional face 120 corresponding thereto, the functional surfaces of the chip have the functional areas that are located at middle part and positioned at periphery
Some weld pads 101；
B. referring to Fig. 9 there is provided a wafer support plate 200, by each chip rearrangement on the wafer support plate, restructuring is formed
Wafer, wherein, the non-functional face of each chip is bonded on the wafer support plate by Heraeus, makes the functional surfaces court of each chip
Outside, there is gap between adjacent chips；When it is implemented, can be by each chip rearrangement on 8 inch or 12 inch wafer support plates, core
There are about 5 μm~5000 μm wide gaps between piece.The wafer support plate is used to support each chip to carry out wafer-level packaging, such as, can
Support the wafer-level packaging of 15000 chips.
C. referring to Fig. 9, each chip outer surface after bonding lays one layer of first dry film or photoresist, to first dry film
Or photoresist is performed etching or photoetching, form the functional areas around each chip and expose the cofferdam of the weld pad of its corresponding chip
301；The cofferdam of each chip is only including cofferdam in the weld pad between the functional areas of chip and weld pad inner side；Here, chip it
Between the first dry film above gap removed, separated each chip.Preferably 5 μm to 15 μm of the thickness of first dry film.
D. referring to Figure 10, one layer of second dry film 400 is pasted in the cofferdam upper surface of each chip, the second thickness of dry film about 30~
60um.Second dry film is performed etching or photoetching, the cover plate 401 for the weld pad for covering on each chip and exposing chip, ginseng is formed
See Figure 11；The cover plate only includes the weld pad inner cover plate for being bonded in covering function area on cofferdam in the weld pad；By dry film photoetching shape
Into cover plate insulating properties it is good, its dielectric constant is higher than 2.Resistivity is higher than 1000 Ω cm.Photoetching cover plate rigid is high
In 4GPa.So, the insulating materials between cavity and metallic circuit can be saved, and for radio frequency products, can be shielded
The signal interference brought by silicon chip；Dry film material has special rigid in itself, it is possible to reduce in reliability testing, because heat is swollen
The product failure risk that the rigid extrusion stretching that swollen coefficient different band is come is brought, that is to say, that from product quality angle, improve
Reliability.
E. after the chip is bonded with the wafer support plate solution, the weld pad that chip is exposed it is electrical by metal lead wire
Or soldered ball leads to external circuit.
Specifically include following steps：
Referring to Figure 12, the wafer support plate of bonding is removed, because the first dry film between chip above gap has been removed, point
From single pre-packaged chip of formation；
The weld pad of pre-packaged chip exposure is electrically connected by metal lead wire or soldered ball with the external world.Such as, first by pre-packaged core
Piece attachment is on a circuit board, referring to Figure 12, and the weld pad for then exposing pre-packaged chip is connected to circuit by breaking metal wire
Default tie point on plate, referring to Figure 13.
Above example is referring to the drawings, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art
Member by above-described embodiment carry out various forms on modification or change, but without departing substantially from the present invention essence in the case of, all
Fall within the scope and spirit of the invention.
Claims (8)
1. a kind of encapsulating structure of semiconductor devices, it is characterised in that including non-functional face containing functional surfaces and corresponding thereto
Chip, the functional surfaces of the chip contain the functional areas positioned at middle part and some weld pads positioned at surrounding, it is characterised in that：Also
Include the cover plate of a polymeric material, the cover plate is positive to be bonded together between the functional surfaces of the chip by cofferdam,
The cofferdam is covered on the weld pad on the functional areas periphery, the cover plate back side be formed through cover plate and cofferdam and with institute
State the conductive structure of the weld pad electrical connection of chip；
Or, the cofferdam is between the functional areas and the weld pad, and the weld pad is by metal lead wire or soldered ball and outside
Boundary is electrically connected.
2. the encapsulating structure of semiconductor devices according to claim 1, it is characterised in that the cover plate of polymeric material
For dry film material, the dielectric constant of the dry film material is higher than 1000 Ω cm, rigid higher than 2, resistivity>4GPa.
3. the encapsulating structure of semiconductor devices according to claim 1, it is characterised in that the cofferdam be dry film material or
Photoresist, the height in the cofferdam is 5 μm -15 μm.
4. the encapsulating structure of semiconductor devices according to claim 1, it is characterised in that the cover sheet thickness is 30~
60um。
5. the encapsulating structure of semiconductor devices according to claim 1, it is characterised in that the chip is filtered for surface acoustic wave
Ripple chip.
6. a kind of preparation method of the encapsulating structure of semiconductor devices, it is characterised in that comprise the following steps：
A., semiconductor chip die is provided, the wafer is cut into some single chips, the chip have functional surfaces and
Non-functional face corresponding thereto, the functional surfaces of the chip have the functional areas positioned at middle part and some weld pads positioned at periphery；
B., one wafer support plate is provided, by each chip rearrangement on the wafer support plate, restructuring wafer is formed, wherein, each core
The non-functional face of piece is bonded on the wafer support plate by Heraeus, faces outwardly the function of each chip, between adjacent chips
With gap；
C. each chip outer surface after bonding lays one layer of first dry film or photoresist, and first dry film or photoresist are carried out
Etching or photoetching, form the functional areas around each chip and expose the cofferdam of the weld pad of its corresponding chip；
D. one layer of second dry film is pasted in the cofferdam upper surface of each chip, second dry film is performed etching or photoetching, form lid
On each chip and exposure chip weld pad cover plate；
E. the weld pad for exposing chip it is electrical cover plate outer surface is led to by conductive structure after, by the chip with it is described
Wafer support plate solution is bonded；Or, after the chip is bonded with the wafer support plate solution, the electrical of the weld pad that chip is exposed is led to
Cross metal lead wire or soldered ball leads to external circuit.
7. the preparation method of the encapsulating structure of semiconductor devices according to claim 6, it is characterised in that shape in step c
Into the cofferdam of each chip include in weld pad between on the inside of the functional areas of chip and weld pad cofferdam and enclosed from the weld pad
Weir extends out to the outer cofferdam of weld pad that chip edge only exposes weld pad；And the cover plate formed in step d is described including being bonded in
The weld pad inner cover plate in covering function area and extend out to chip edge on cofferdam in weld pad from the weld pad inner cover plate and only expose weldering
The weld pad outer cover plate of pad；The conductive structure of electrical connection weld pad is formed with the opening of the cover plate of each chip and cofferdam exposure weld pad,
The conductive structure is electrically led to weld pad on the outer surface of cover plate.
8. the preparation method of the encapsulating structure of semiconductor devices according to claim 6, it is characterised in that shape in step c
Into the cofferdam of each chip only include cofferdam in weld pad between on the inside of the functional areas of chip and weld pad；And shape in step d
Into cover plate only include being bonded in the weld pad inner cover plate in covering function area on cofferdam in the weld pad；The weld pad of each chip exposure leads to
Metal lead wire or soldered ball is crossed to electrically connect with the external world.
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| CN201710416795.8A CN107331625A (en) | 2017-06-06 | 2017-06-06 | Encapsulating structure of semiconductor devices and preparation method thereof |
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| CN201710416795.8A CN107331625A (en) | 2017-06-06 | 2017-06-06 | Encapsulating structure of semiconductor devices and preparation method thereof |
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| CN109037428A (en) * | 2018-08-10 | 2018-12-18 | 付伟 | Chip-packaging structure and preparation method thereof with double cofferdam |
| CN109037430A (en) * | 2018-08-10 | 2018-12-18 | 付伟 | Chip-packaging structure and preparation method thereof with double cofferdam and outer Mobile Communication hole |
| CN109037426A (en) * | 2018-08-10 | 2018-12-18 | 付伟 | Chip-packaging structure and preparation method thereof with double cofferdam and metal layer |
| CN109037427A (en) * | 2018-08-10 | 2018-12-18 | 付伟 | Chip-packaging structure and preparation method thereof with single cofferdam |
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| CN109037427B (en) * | 2018-08-10 | 2024-07-23 | 浙江熔城半导体有限公司 | Chip packaging structure with single cofferdam and manufacturing method thereof |
| CN109037425B (en) * | 2018-08-10 | 2024-08-06 | 浙江熔城半导体有限公司 | Chip packaging structure with extending double cofferdams and metal layers and manufacturing method thereof |
| CN109004082A (en) * | 2018-08-10 | 2018-12-14 | 付伟 | With the chip-packaging structure and preparation method thereof for extending double cofferdam |
| CN109037428B (en) * | 2018-08-10 | 2024-08-02 | 浙江熔城半导体有限公司 | Chip packaging structure with double cofferdams and manufacturing method thereof |
| CN109037426B (en) * | 2018-08-10 | 2024-06-14 | 浙江熔城半导体有限公司 | Chip packaging structure with double cofferdams and metal layers and manufacturing method thereof |
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| CN110877892B (en) * | 2019-10-25 | 2023-07-21 | 厦门云天半导体科技有限公司 | Device packaging structure and method with cavity |
| CN110993571A (en) * | 2019-12-20 | 2020-04-10 | 苏州科阳光电科技有限公司 | Wafer level packaging structure and packaging method |
| CN110993570A (en) * | 2019-12-20 | 2020-04-10 | 苏州科阳光电科技有限公司 | Wafer level packaging structure and packaging method |
| CN114684771A (en) * | 2020-12-25 | 2022-07-01 | 中芯集成电路（宁波）有限公司上海分公司 | Packaging structure and manufacturing method thereof |
| CN112670192A (en) * | 2020-12-25 | 2021-04-16 | 苏州科阳半导体有限公司 | Wafer level packaging process and wafer level packaging structure |
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Application publication date: 20171107 |