CN112017974A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN112017974A CN112017974A CN201910454084.9A CN201910454084A CN112017974A CN 112017974 A CN112017974 A CN 112017974A CN 201910454084 A CN201910454084 A CN 201910454084A CN 112017974 A CN112017974 A CN 112017974A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 260
- 229910052751 metal Inorganic materials 0.000 claims abstract description 260
- 239000004033 plastic Substances 0.000 claims abstract description 119
- 239000012785 packaging film Substances 0.000 claims abstract description 65
- 229920006280 packaging film Polymers 0.000 claims abstract description 65
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 238000005476 soldering Methods 0.000 claims abstract description 5
- 229920006255 plastic film Polymers 0.000 claims description 20
- 239000002985 plastic film Substances 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 15
- 230000001939 inductive effect Effects 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 94
- 230000008569 process Effects 0.000 description 24
- 239000010410 layer Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010897 surface acoustic wave method Methods 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
A chip packaging structure and a packaging method are provided, the structure comprises: the wafer (1), wherein a groove (2) is arranged in the wafer (1); the first metal wire (3) is arranged on the surfaces of the groove (2) and the wafer (1); metal solder balls (4) arranged on the first metal lines (3) or the metal pads of the chip for soldering the metal pads of the chip to the first metal lines (3) to flip the chip into the grooves (2); the first plastic packaging film (5) covers the upper surfaces of the wafer (1), the chip and the first metal wire (3) and enters gaps between the periphery of the chip functional area and the first metal wire (3) so as to form a closed cavity among the wafer (1), the groove (2) and the chip; the inductor structure (6) is arranged on the upper surface of the first plastic packaging film (5) and/or the lower surface of the wafer (1) and is connected to the chip through a first metal wire (3); and the bonding pad (7) is arranged on the inductance structure (6).
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip package structure and a chip package method.
Background
Filters in communication are mainly divided into Surface Acoustic Wave (SAW) filters and Bulk Acoustic Wave (BAW) filters, and the BAW and the SAW need to ensure that a chip functional region cannot be contacted with any impurities, namely, a cavity structure needs to be formed on the upper Surface of the filter in a packaging mode. Traditional SAW usually grows metal salient points on a bare wafer, and the metal salient points are inversely welded on a ceramic substrate, and then a metal cap, a top sealing or an envelope process is used for sealing a module to form a cavity structure, but the ceramic substrate causes high welding cost, large packaging volume and inconsistent device performance due to instability of device installation. In addition, the SAW may be covered on the upper surface of a Printed Circuit Board (PCB) substrate with the front surface facing downward, the SAW is electrically connected to the PCB substrate through gold balls, and an epoxy resin encapsulation film is covered on the upper portions of the SAW and the PCB substrate to form a cavity structure, but the epoxy resin film may be thermally compressed into the metal bumps of the chip, and the coverage area of the epoxy resin film may affect the package size and the package strength, and has an extremely high requirement on the SAW thermal compression pressure. Wafer-level packaging (WLP) is generally adopted for Wafer packaging of BAW chips, but WLP is complex in process, requires bonding of two wafers, is extremely high in cost, involves complex processes such as through-silicon-via etching and gold bonding, is prone to chip failure due to process problems, and cannot directly perform multi-chip integrated packaging.
In order to meet the increasingly complex system functions of products, the development of a multi-chip interconnection integrated packaging technology is fast, and the current mainstream scheme is as follows: a plurality of chips are horizontally distributed side by side and welded to the substrate through the bumps, signal interconnection among the chips is achieved through internal circuits of the substrate, plastic package protection is conducted on the chips, and the modules are integrally welded to the PCB, so that interconnection integration of products is achieved. The method needs to realize interconnection among chips through multi-layer wiring switching, and the problems of signal transmission delay, thick packaging thickness, high packaging cost and the like are caused by the fact that the metal layer and the dielectric layer of the substrate are thick.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a chip package structure and a chip package method, which at least solve the above technical problems.
(II) technical scheme
The present disclosure provides a chip packaging structure, including: the wafer is provided with a groove; the first metal wire is arranged on the side surface of the groove, two sides of the bottom surface of the groove and the upper surface of the wafer; the metal solder balls are arranged on the first metal wires or the metal pads of the chip and used for welding the metal pads of the chip to the first metal wires so as to flip the chip into the grooves; the first plastic packaging film covers the upper surfaces of the wafer, the chip and the first metal wire and enters gaps between the periphery of the chip functional area and the first metal wire so as to form a closed cavity among the wafer, the groove and the chip; the inductor structure is arranged on the upper surface of the first plastic packaging film and/or the lower surface of the wafer and is connected to the chip through the first metal wire; a pad disposed on the inductor structure.
Optionally, the inductance structure comprises a set of and more than second plastic envelope membrane, a second metal wire and a third metal wire, the third metal wire is arranged on the first surface of the second plastic envelope membrane according to a preset shape, and the second metal wire penetrates through a hollow window of the second plastic envelope membrane to sequentially connect each set of the third metal wire.
Optionally, the inductance structure is disposed on an upper surface of the first plastic package film, the first surface is the upper surface, and the second metal wire penetrates through a hollow window of the first plastic package film to connect the first group of the third metal wires to the first metal wire.
Optionally, a first metal line outgoing line passes through the empty window of the wafer and is connected to the first metal line, the inductance structure is disposed on the lower surface of the wafer and is located on the lower surface of the first metal line outgoing line, the first surface is the lower surface, and the second metal line of the first group is connected to the first metal line outgoing line (3') so as to connect the third metal line of the first group to the first metal line.
Optionally, the chip corresponds to the two inductance structures and is respectively arranged on the upper surface of the first plastic package film and the lower surface of the wafer; the first surface corresponding to the inductance structure arranged on the upper surface of the first plastic packaging film is an upper surface, and the second metal wires of the first group penetrate through the hollow window of the first plastic packaging film so as to connect the third metal wires of the first group to the first metal wires; the first surface corresponding to the inductance structure arranged on the lower surface of the wafer is the lower surface, a first metal wire outgoing line penetrates through the empty window of the wafer and is connected to the first metal wire, the inductance structure is located on the lower surface of the first metal wire outgoing line, and the second metal wire of the first group of the inductance structure is connected with the first metal wire outgoing line so as to connect the third metal wire of the first group of the inductance structure to the first metal wire.
Optionally, the thickness of the first plastic film on the upper surface of the first metal wire is 20-50 μm.
The present disclosure also provides a chip packaging method, including: s1, preparing a groove in the wafer; s2, preparing first metal wires on the side surface and the two sides of the bottom surface of the groove and the upper surface of the wafer; s3, preparing a metal solder ball on the first metal wire or the metal pad of the chip, and soldering the metal pad of the chip to the first metal wire through the metal solder ball to flip the chip into the groove; s4, preparing a first plastic packaging film on the upper surfaces of the wafer, the chip and the first metal wire, and enabling the first plastic packaging film to enter gaps between the periphery of the chip functional area and the first metal wire so as to form a closed cavity among the wafer, the groove and the chip; s5, preparing an inductance structure on the upper surface of the first plastic package film and/or the lower surface of the wafer, and connecting the inductance structure to the first metal wire; and S6, preparing a bonding pad on the inductance structure.
Optionally, the inductance structure is disposed on an upper surface of the first plastic package film, and the step S5 includes: s51, preparing a second plastic packaging film on the upper surface of the first plastic packaging film; s52, windowing the second plastic packaging film; s53, windowing the first plastic package film to expose the first metal wire; s54, preparing a second metal wire in the hollow window after windowing, and preparing a third metal wire on the upper surface of the second plastic package film according to a preset shape; s55, repeating the steps S51, S52, S54 by a preset number of times.
Optionally, the inductance structure is disposed on the lower surface of the wafer, and the step S5 includes: s51, windowing the lower surface of the wafer to expose the first metal wire, and preparing a first metal outgoing line in the empty window of the wafer; s52, preparing a second plastic packaging film on the lower surface of the first metal outgoing line; s53, windowing the second plastic packaging film; s54, preparing a second metal wire in the hollow window of the second plastic package film, and preparing a third metal wire on the lower surface of the second plastic package film according to a preset shape; s55, repeating the steps S52, S53, S54 by a preset number of times.
Optionally, the chips correspond to the two inductance structures and are respectively disposed on the upper surface of the first plastic package film and the lower surface of the wafer, and the step S5 includes: s51, windowing the lower surface of the wafer to expose the first metal wire, and preparing a first metal outgoing line in the empty window of the wafer; s52, preparing second plastic packaging films on the upper surface of the first plastic packaging film and the lower surface of the first metal outgoing line respectively; s53, windowing the second plastic packaging film; s54, windowing the first plastic packaging film; s55, preparing a second metal wire in the hollow window after windowing, and preparing a third metal wire on the second plastic package films on the upper surface and the lower surface respectively according to a preset shape; s56, repeating the steps S52, S53, S55 by a preset number of times.
(III) advantageous effects
The chip packaging structure and the packaging method provided by the disclosure have the following beneficial effects at least:
(1) the flip-chip welded chip is sealed and cured at high temperature in a film covering mode, so that a plastic packaging film can be prevented from entering a chip functional area, a high-reliability cavity structure is formed, the chip can be fixed by using a groove structure, and the mechanical impact resistance and the packaging air tightness of the chip are improved;
(2) the wafer coated with the film is thinned by CMP, so that the sheet operation risk of the main chip wafer in the manufacturing process can be eliminated, and the process difficulty is reduced;
(3) the inductor circuit integration can be realized through metal wiring on the surface of the wafer after plastic packaging, the cost is reduced, and various radio frequency chip comprehensive impedance matching requirements can be realized through multilayer metal wiring, so that integrated manufacturing is realized.
Drawings
Fig. 1 schematically illustrates a schematic diagram of a chip package structure provided by an embodiment of the present disclosure.
Fig. 2 schematically shows a flowchart of a chip packaging method provided by an embodiment of the present disclosure.
Fig. 3 schematically illustrates a distribution diagram of the groove units on the wafer according to the embodiment of the disclosure.
Fig. 4 schematically shows a cross-sectional view along H-H' of fig. 3.
Fig. 5 is a schematic diagram of the step S2 of preparing the first metal line 3 in the packaging method.
Fig. 6 is a schematic diagram of the step S3 of preparing metal solder balls and flip chips in the packaging method.
Fig. 7A and 7B are schematic views of preparing the first plastic film and thinning the first plastic film in step S4 in the packaging method, respectively.
Fig. 8A, 8B, 8C and 8D are schematic diagrams of steps S5 and S6 of the packaging method for preparing the inductor structure and the bonding pads.
Fig. 9 is a schematic diagram of another chip package structure.
Fig. 10 is a schematic diagram of another chip package structure.
Description of reference numerals:
1-a wafer; 2-a groove; 3-a first metal line; 3' -a first metal wire outlet; 4-a metal solder ball; 5-a first plastic packaging film; 6-an inductor structure; 7-a pad; 8-a second plastic packaging film; 9' -blank window; 9-a second metal line; 10-a third metal line; 20-chip a recess; 21-chip B groove; 22-chip C recess; 23-a multi-chip groove unit; 24-chip A; 25-chip B; 26-cavity.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
A first embodiment of the present disclosure shows a chip package structure, which is described in detail with reference to fig. 1, 3, 9 and 10.
The chip packaging structure comprises a wafer 1, a groove 2, a first metal wire 3, a metal solder ball 4, a first plastic packaging film 5, an inductance structure 6 and a bonding pad 7.
The material of the wafer 1 is one of silicon, glass, sapphire, ceramic or a mixed material mainly containing silicon, glass, sapphire and ceramic. The grooves 2 are disposed in the wafer 1, and further, as shown in fig. 3, there may be a plurality of sets of multi-chip groove units 23 in the wafer 1, and a plurality of grooves may be disposed in each set of multi-chip groove units 23, and are respectively used for integrally packaging different chips a1、A2、……AnIn the present embodiment, only each group of the groove units includes the chip a groove 20, the chip B groove 21, and the chip C groove 22, and it is understood that the multi-chip groove unit 23 may include other sizes and numbers of chip grooves. The depth of the recess 2 is not greater than the height of its corresponding chip.
The first metal lines 3 are disposed on the side surfaces of the grooves 2, on both sides of the bottom surface, and on the upper surface of the wafer 1. The metal solder balls 4 are disposed on the first metal lines 3 or on the metal pads of the chip, specifically, on the first metal lines 3 on both sides of the bottom surface of the groove 2 or on the metal pads of the chip, and the metal solder balls 4 should be aligned with the pins (pads) of the metal silicon chip of the chip, or the metal solder balls 4 should be aligned with the first metal lines 3 on both sides of the bottom surface of the groove 2, so that the metal pads of the chip can be aligned and soldered to the first metal lines 3 on both sides of the bottom surface of the groove 2 through the metal solder balls 4 to flip the chip into the groove 2.
The first plastic packaging film 5 covers the upper surfaces of the wafer 1, the chip and the first metal wire 3, and enters gaps between the periphery of the chip functional region and the first metal wire 3 to form a closed cavity among the wafer 1, the groove 2 and the chip. The thickness of the first plastic film 5 on the upper surface of the first metal line 3 is 20-50 μm to prevent the first metal line 3 from being exposed.
The inductance structure 6 is disposed on the upper surface of the first plastic package film 5 and/or the lower surface of the wafer 1, and is connected to the chip through the first metal line 3. The inductance structure 6 is composed of one or more groups of second plastic package films 8, second metal wires 9 and third metal wires 10, and the shapes of the third metal wires 10 of each group can be distinguished to realize corresponding filtering effects. The inductive structure 6 comprises three structures, as shown in fig. 1, 9 and 10, respectively.
Referring to fig. 1, an inductance structure 6 is disposed on an upper surface of a first plastic film 5. Specifically, the second plastic packaging film 8 is provided with a window passing therethrough, which can expose the third metal wire 10, and the first plastic packaging film 5 is also provided with a window passing therethrough, which can expose the first metal wire 3 on the upper surface of the wafer 1; the third metal wire 10 is arranged on the upper surface of the second plastic package film 8 according to a preset shape; the second metal lines 9 pass through the empty windows of the second plastic encapsulation film 8 to connect the third metal lines 10 of each group in turn, and the second metal lines 9 of the first group also pass through the empty windows of the first plastic encapsulation film 5 to connect the third metal lines 10 of the first group to the first metal lines 3, thereby connecting the inductance structure 6 to the chip.
Referring to fig. 9, the inductor structure 6 is disposed on the lower surface of the wafer 1. Specifically, the second plastic package film 8 is provided therein with a window penetrating therethrough, which may expose the third metal line 10, and the wafer 1 is also provided therein with a window penetrating therethrough, which may expose the first metal lines 3 on both sides of the bottom surface of the groove 2; the third metal wire 10 is arranged on the lower surface of the second plastic package film 8 according to a preset shape; the second metal lines 9 pass through the empty windows of the second plastic encapsulation film 8 to sequentially connect the third metal lines 10 of each group, and there are also provided first metal line outgoing lines 3 ', the first metal line outgoing lines 3' pass through the empty windows of the wafer 1, the second metal lines 9 of the first group are connected with the first metal line outgoing lines 3 'to connect the third metal lines 10 of the first group to the first metal lines 3 through the first metal line outgoing lines 3' and the second metal lines 9, thereby connecting the inductance structure 6 to the chip. It is understood that, in this structure, the first metal lines 3 may not be disposed on the upper surface of the wafer 1, i.e., the first metal lines 3 are disposed only on two sides of the bottom surface of the groove 2.
Referring to fig. 10, in order to meet the requirement of more complicated circuit connection, an inductance structure 6 may be disposed on both the upper surface of the first plastic film 5 and the lower surface of the wafer 1. Specifically, a first metal wire leading-out wire 3' is arranged on the lower surface of the wafer 1, and a hollow window penetrating through the lower surface of the wafer 1 is arranged on the lower surface of the wafer 1 and can expose the first metal wires 3 on two sides of the bottom surface of the groove 2; a hollow window penetrating through the second plastic packaging film 8 on the lower surface of the wafer 1 is arranged in the second plastic packaging film 8, and the hollow window can expose the third metal wire 10 on the lower surface of the wafer 1 and also expose the first metal wire leading-out wire 3' on the lower surface of the wafer 1; a hollow window penetrating through the second plastic packaging film 8 on the upper surface of the wafer 1 (specifically, on the upper surface of the first plastic packaging film 5) is also arranged in the first plastic packaging film 5 on the upper surface of the wafer 1, and the hollow window can expose the first metal wire 3 on the upper surface of the wafer 1; the third metal wire 10 in the inductance structure 6 arranged on the upper surface of the first plastic package film 5 is arranged on the upper surface of the second plastic package film 8 according to a preset shape, and the third metal wire 10 in the inductance structure 6 arranged on the lower surface of the wafer 1 is arranged on the lower surface of the second plastic package film 8 according to the preset shape; the second metal wires 9 pass through the empty windows of the second plastic packaging film 8 to sequentially connect the third metal wires 10 of each group, and the second metal wires 9 of the first group of the two inductor structures 6 also respectively pass through the empty windows of the first plastic packaging film 5 and the empty windows of the second plastic packaging film 8 to respectively connect the third metal wires 10 of the first group thereof to the first metal wires 3 and the first metal wire outgoing lines 3', so that the two inductor structures 6 are connected to the chip.
The pads 7 are arranged on the inductive structure 6, in particular on the third metal lines 10 of the last group of the inductive structure 6.
A second embodiment of the present disclosure shows a chip packaging method, which is described in detail with reference to fig. 3 to 10 as shown in fig. 2, and mainly includes the following operations:
s1, preparing a groove 2 in the wafer 1.
The material of the wafer 1 is one of silicon, glass, sapphire, ceramic or a mixed material mainly containing silicon, glass, sapphire and ceramic. In the embodiment, the glass wafer is used as the chip carrier and the packaging material, so that the material cost is greatly reduced compared with a gold-bonded wafer-level packaging structure using a ceramic substrate, a plastic substrate and a silicon wafer.
Preparing grooves 2 in a wafer 1, referring to fig. 3, a plurality of groups of groove units may be arranged in the wafer 1, and a plurality of grooves may be arranged in each group of groove units, and are respectively used for integrated packaging of different chips a1、A2、……、AnIn this embodiment, only one group of the groove units includes A, B, C chip grooves, and it is understood that the groove units may include other sizes and numbers of chip grooves. The depth of the recess 2 is not greater than the height of its corresponding chip.
In this embodiment, only each group of groove units includes A, B, C chips, and a cross section along the direction H-H' in fig. 3 is taken as an example, which is schematically shown in fig. 4, where fig. 4 includes a plurality of groups of groove units, and each group of groove units includes two grooves, namely, a groove 20 of a chip a and a groove 21 of a chip B.
S2, first metal lines 3 are formed on the side surfaces and both sides of the bottom surface of the recess 2 and the top surface of the wafer 1.
Referring to fig. 5, the first metal line 3 is fabricated using a metal sputtering, photolithography, etching or LIFF-OFF process.
S3, preparing a metal solder ball 4 on the first metal line 3 or the metal pad of the chip, and soldering the metal pad of the chip to the first metal line 3 through the metal solder ball 4 to flip the chip into the recess 2.
Referring to fig. 6, metal solder balls 4 are prepared on the first metal lines 3 on both sides of the bottom surface of the recess 2. And flip-chip A and chip B to the corresponding chip A groove 20 and chip B groove 21 respectively by adopting ultrasonic thermocompression bonding or thermocompression bonding, so that the metal pads of the chip A and chip B are aligned and welded with the metal solder balls 4 in the grooves 2.
In addition, it is also possible to form metal solder balls 4 on the chip a and the chip B, and then solder the chip a and the chip B onto the metal pads in the recess 2 through the metal solder balls 4.
It is understood that all the chips a to be packaged may be processed according to the operation S31、A2、……、AnFlip-chip into the recess 2.
S4, preparing a first plastic film 5 on the upper surfaces of the wafer 1, the chip and the first metal line 3, and making the first plastic film enter the gap between the periphery of the chip functional region and the first metal line 3, so as to form a sealed cavity 26 between the wafer 1, the groove 2 and the chip.
First, a hot pressing method is adopted to attach an encapsulation film (i.e., a first plastic encapsulation film 5) to the wafer 1, the chip, and the upper surface of the first metal line 3, where the first plastic encapsulation film 5 may be a single layer film or a multilayer film. In this embodiment, the grooves 2 suitable for various chips are formed in advance on the wafer 1, and the flip-chip bonded chips are sealed in a film-coating manner, and simultaneously, a cavity structure of a chip functional region is formed. By controlling the depth and width of the groove of the wafer 1 and controlling the accurate alignment flip-chip, a relatively narrow gap can be reserved between the periphery of the chip and the groove 2, the pressure and temperature of the laminating film of the operation S4 are controlled, the depth of the plastic packaging film entering the gap can be accurately controlled, the plastic packaging film is completely prevented from entering the functional area of the chip, and a high-reliability cavity structure is formed.
Next, high temperature curing is performed to form a closed cavity structure between the surface of the recess 2 and the functional region of the chip in the wafer 1, as shown in fig. 7A. High-temperature curing is performed in operation S4, the plastic package film is subjected to plastic package curing, and the chip can be fixed in the package structure, so that the chip is not easy to move in the package structure, the mechanical impact resistance and the package airtightness of the chip are greatly improved, and the reliability of the chip is improved.
Then, the CMP thinning is performed on the plastic cover (i.e., the first plastic film 5) of the wafer 1, and the thinned thickness is controlled so that the thinning stops on the first metal lines 3 on the upper surface of the wafer 1, and preferably, the first plastic film 5 with a thickness of 20-50 μm is reserved on the first metal lines 3, as shown in fig. 7B. After each chip is inversely packaged to the groove 2 of the wafer 1, the plastic packaging surface of the wafer 1 is subjected to CMP thinning, so that the thinning process of the main chip wafer in the manufacturing process can be omitted, the sheet operation risk of the main chip wafer in the manufacturing process is eliminated, and the process difficulty is reduced; and because the depth of the groove is limited, the chip is embedded into the groove during thinning, and therefore ultrathin packaging can be achieved.
S5, forming an inductance structure 6 on the upper surface of the first plastic film 5 and/or the lower surface of the wafer 1, and connecting the inductance structure 6 to the first metal line 3.
The packaging method in this embodiment is directed to the three chip package structures shown in the first embodiment, and thus operation S5 is divided into three cases:
(1) the inductance structure 6 is prepared on the upper surface of the first plastic encapsulation film 5, and operation S5 includes the following sub-operations:
s51, covering a layer of the second plastic film 8 on the upper surface of the thinned first plastic film 5, and performing high temperature curing, as shown in fig. 8A.
And S52, performing windowing on the second plastic packaging film 8 by adopting a photoetching process.
S53, performing a window opening on the first plastic film 5 by using a photolithography etching process to expose the first metal line 3 on the upper surface of the wafer 1, as shown in fig. 8B.
S54, forming a metal layer (namely, a second metal wire 9) in the hollow window 9' after windowing by adopting a metal sputtering, electroplating or evaporation process so as to lead out the metal wire below the window; then, metal rewiring is performed on the upper surface of the second plastic encapsulation film 8 by using a photolithography etching process or a LIFT-OFF process to prepare a third metal line 10 on the upper surface of the second plastic encapsulation film 8 in a preset shape, as shown in fig. 8C.
S55, repeating the operations S51, S52, S54 by a preset number of times to form a multi-layered metal wiring for manufacturing an inductance structure required for the filter circuit. In addition, a dielectric layer may be deposited instead of covering the second plastic film 8 in operation S51 in this operation, as shown in fig. 8D.
(2) An inductor structure 6 is prepared on the lower surface of the wafer 1, and the formed chip package structure is as shown in fig. 9. Operation S5 includes the following sub-operations:
s51, the lower surface of the wafer 1 is windowed to expose the first metal lines 3, and the first metal line lead-out lines 3' are prepared in the empty windows of the wafer 1.
And S52, covering a layer of second plastic package film 8 on the upper surface and the lower surface of the wafer 1, and carrying out high-temperature curing.
S53, performing windowing on the second plastic packaging film 8 on the lower surface of the wafer 1 by adopting a photoetching process, and exposing the first metal wire outgoing line 3' on the lower surface of the wafer 1.
S54, forming a metal layer (namely, a second metal wire 9) in the hollow window after the window is opened by adopting a metal sputtering, electroplating or evaporation process so as to lead out the metal wire on the window; and then, metal rewiring is performed on the lower surface of the second plastic package film 8 by using a photolithography etching process or a LIFT-OFF process to prepare a third metal wire 10 on the lower surface of the second plastic package film 8 according to a preset shape.
S55, repeating the operations S52, S53, S54 by a preset number of times to form a multi-layered metal wiring for manufacturing an inductance structure required for the filter circuit. In addition, instead of covering the second plastic film 8 in operation S51, a dielectric layer may be deposited in this operation.
(3) Inductor structures 6 are respectively prepared on the upper surface of the first plastic package film 5 and the lower surface of the wafer 1, and the formed chip package structure is shown in fig. 10. Operation S5 includes the following sub-operations:
s51, the lower surface of the wafer 1 is windowed to expose the first metal lines 3, and the first metal line lead-out lines 3' are prepared in the empty windows of the wafer 1.
And S52, respectively covering a layer of second plastic packaging film 8 on the upper surface of the thinned first plastic packaging film 5 and the lower surface of the first metal wire leading-out wire 3' of the wafer 1, and performing high-temperature curing.
S53, the second plastic package films 8 on the upper surface and the lower surface are respectively windowed by adopting the photoetching process, and at the moment, the first metal wire leading-out wire 3' on the lower surface of the wafer 1 is exposed.
And S54, windowing the first plastic packaging film 5 on the upper surface by adopting a photoetching process to expose the first metal wire 3 on the upper surface of the wafer 1.
S55, forming a metal layer (namely, a second metal wire 9) in the hollow window after the window is opened by adopting a metal sputtering, electroplating or evaporation process so as to respectively lead out the metal wires on the upper surface and the lower surface of the window; then, metal rewiring is performed on the upper surface of a second plastic packaging film 8 (the second plastic packaging film 8 is positioned on the first plastic packaging film 5) and the lower surface of the second plastic packaging film 8 (the second plastic packaging film 8 is positioned below the first metal wire outgoing line 3 'below the wafer 1) by using a photoetching process or a LIFT-OFF process, so that a third metal wire 10 is prepared on the upper surface of the second plastic packaging film 8 (the second plastic packaging film 8 is positioned below the wafer 1) and the lower surface of the second plastic packaging film 8 (the second plastic packaging film 8 is positioned below the first metal wire outgoing line 3' below the wafer 1) according to a preset shape.
S56, repeating the operations S52, S53, S55 by a preset number of times to form a multi-layered metal wiring for manufacturing an inductance structure required for the filter circuit. In addition, instead of covering the second plastic film 8 in operation S51, a dielectric layer may be deposited in this operation.
In operation S5, metal wiring is performed again on the surface of the plastic-encapsulated wafer, so that the inductor circuit integration can be achieved, thereby eliminating the substrate manufacturing process with high cost and complex process. In this embodiment, prepared the multicore piece recess, behind the multicore piece plastic envelope, carried out metal wiring again on the wafer surface, can satisfy the integrated encapsulation demand of all kinds of different chips to can realize the ultra-thin encapsulation of minimum size through reasonable planning with very big reduction encapsulation area.
In addition, after various different chips are integrally packaged, multilayer metal wiring is carried out, the comprehensive impedance matching requirements of various radio frequency chips can be met, the modularization and integration manufacturing of radio frequency front-end chips are achieved, and the debugging work used by users is reduced.
It should be noted that the second plastic film 8 in this embodiment may be replaced by an epoxy black glue or a glass film.
S6, a pad 7 is prepared on the inductance structure 6.
And preparing a metal bump or bonding pad 7 on the last layer of metal wiring, and carrying out scribing cutting, testing and finished product packaging on the multi-chip module on the wafer 1.
Therefore, the chip package structure and the package method provided by the present disclosure have been described in detail, and are mainly applicable to multi-chip fan-out System-in-package, and can form a cavity package structure with reliable performance, especially to Micro-Electro-Mechanical System (MEMS) device packages that require a cavity structure to be formed on the surface, such as an acoustic wave filter and a microphone. The packaging structure and the packaging method can also realize the rewiring of multiple chips and can realize the wiring function of the integrated inductor of a multi-chip system; in addition, the multi-chip thinning function can be realized after cutting and inversion, the process abnormity caused by chip slice processing risks is avoided, and finally ultra-thin packaging is realized.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A chip package structure, comprising:
the wafer (1), wherein a groove (2) is formed in the wafer (1);
the first metal wire (3) is arranged on the side surface and two sides of the bottom surface of the groove (2) and the upper surface of the wafer (1);
metal solder balls (4) disposed on the first metal lines (3) or the metal pads of the chip for soldering the metal pads of the chip to the first metal lines (3) to flip-chip the chip into the grooves (2);
the first plastic packaging film (5) covers the upper surfaces of the wafer (1), the chip and the first metal wire (3) and enters gaps between the periphery of the chip functional area and the first metal wire (3) so as to form a closed cavity among the wafer (1), the groove (2) and the chip;
the inductance structure (6) is arranged on the upper surface of the first plastic packaging film (5) and/or the lower surface of the wafer (1) and is connected to the chip through the first metal wire (3);
a pad (7) disposed on the inductive structure (6).
2. The chip packaging structure according to claim 1, wherein the inductor structure (6) is composed of one or more groups of second plastic packaging films (8), second metal wires (9) and third metal wires (10), the third metal wires (10) are disposed on the first surface of the second plastic packaging film (8) according to a preset shape, and the second metal wires (9) penetrate through the hollow windows of the second plastic packaging film (8) to sequentially connect the third metal wires (10) of each group.
3. The chip packaging structure according to claim 2, wherein the inductance structure (6) is arranged on an upper surface of the first plastic encapsulation film (5), the first surface being the upper surface, and the second metal line (9) passes through a hollow window of the first plastic encapsulation film (5) to connect the third metal line (10) of the first group to the first metal line (3).
4. The chip package structure according to claim 2, wherein a first metal line outlet (3 ') penetrates through the opening of the wafer (1) and is connected to the first metal line (3), the inductance structure (6) is disposed on a lower surface of the wafer (1) and is located on a lower surface of the first metal line outlet (3 '), the first surface being the lower surface, and the second metal line (9) of the first group is connected to the first metal line outlet (3 ') to connect the third metal line (10) of the first group to the first metal line (3).
5. The chip packaging structure according to claim 2, wherein the chip corresponds to two of the inductance structures (6) and is respectively disposed on an upper surface of the first plastic packaging film (5) and a lower surface of the wafer (1);
the first surface corresponding to the inductance structure (6) arranged on the upper surface of the first plastic package film (5) is an upper surface, and the second metal wire (9) of the first group of the second metal wire penetrates through the hollow window of the first plastic package film (5) so as to connect the third metal wire (10) of the first group of the third metal wire to the first metal wire (3);
the first surface corresponding to the inductance structure (6) arranged on the lower surface of the wafer (1) is the lower surface, a first metal wire outgoing line (3 ') penetrates through the hollow window of the wafer (1) and is connected to the first metal wire (3), the inductance structure (6) is arranged on the lower surface of the first metal wire outgoing line (3 '), and the second metal wire (9) of the first group is connected with the first metal wire outgoing line (3 ') so as to connect the third metal wire (10) of the first group to the first metal wire (3).
6. The chip packaging structure according to claim 1, wherein the thickness of the first plastic film (5) on the upper surface of the first metal line (3) is 20-50 μm.
7. A chip packaging method, comprising:
s1, preparing a groove (2) in the wafer (1);
s2, preparing first metal wires (3) on the side surfaces and two sides of the bottom surface of the groove (2) and the upper surface of the wafer (1);
s3, preparing a metal solder ball (4) on the first metal line (3) or the metal pad of the chip, and soldering the metal pad of the chip to the first metal line (3) through the metal solder ball (4) to flip the chip into the groove (2);
s4, preparing a first plastic packaging film (5) on the upper surfaces of the wafer (1), the chip and the first metal wire (3), and enabling the first plastic packaging film to enter gaps between the periphery of the chip functional area and the first metal wire (3) so as to form a closed cavity among the wafer (1), the groove (2) and the chip;
s5, preparing an inductance structure (6) on the upper surface of the first plastic package film (5) and/or the lower surface of the wafer (1), and connecting the inductance structure (6) to the first metal wire (3);
s6, preparing a pad (7) on the inductance structure (6).
8. The chip packaging method according to claim 7, wherein the inductance structure (6) is disposed on an upper surface of the first plastic film (5), and the step S5 comprises:
s51, preparing a second plastic packaging film (8) on the upper surface of the first plastic packaging film (5);
s52, windowing the second plastic packaging film (8);
s53, windowing the first plastic packaging film (5) to expose the first metal wire (3);
s54, preparing a second metal wire (9) in the hollow window after windowing, and preparing a third metal wire (10) on the upper surface of the second plastic packaging film (8) according to a preset shape;
s55, repeating the steps S51, S52, S54 by a preset number of times.
9. The chip packaging method according to claim 7, wherein the inductor structure (6) is disposed on the lower surface of the wafer (1), and the step S5 comprises:
s51, windowing the lower surface of the wafer (1) to expose the first metal wire (3), and preparing a first metal lead-out wire (3') in the hollow window of the wafer (1);
s52, preparing a second plastic packaging film (8) on the lower surface of the first metal lead-out wire (3');
s53, windowing the second plastic packaging film (8);
s54, preparing a second metal wire (9) in a hollow window of the second plastic package film (8), and preparing a third metal wire (10) on the lower surface of the second plastic package film (8) according to a preset shape;
s55, repeating the steps S52, S53, S54 by a preset number of times.
10. The chip packaging method according to claim 7, wherein the chips correspond to the two inductance structures (6) and are respectively disposed on the upper surface of the first plastic package film (5) and the lower surface of the wafer (1), and the step S5 includes:
s51, windowing the lower surface of the wafer (1) to expose the first metal wire (3), and preparing a first metal lead-out wire (3') in the hollow window of the wafer (1);
s52, preparing second plastic package films (8) on the upper surface of the first plastic package film (5) and the lower surface of the first metal lead-out wire (3') respectively;
s53, windowing the second plastic packaging film (8);
s54, windowing the first plastic packaging film (5);
s55, preparing a second metal wire (9) in the hollow window after windowing, and preparing a third metal wire (10) on the second plastic package films (8) on the upper surface and the lower surface respectively according to a preset shape;
s56, repeating the steps S52, S53, S55 by a preset number of times.
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