CN109004018A - 肖特基二极管及制备方法 - Google Patents

肖特基二极管及制备方法 Download PDF

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CN109004018A
CN109004018A CN201810810551.2A CN201810810551A CN109004018A CN 109004018 A CN109004018 A CN 109004018A CN 201810810551 A CN201810810551 A CN 201810810551A CN 109004018 A CN109004018 A CN 109004018A
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schottky diode
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heavy doping
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冉军学
魏同波
王军喜
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes

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Abstract

本发明一种肖特基二极管,包含:一重掺杂的N型SiC衬底;一轻掺杂的N型SiC层,其生长在重掺杂的N型SiC衬底上;一非掺杂的SiC层,其生长在轻掺杂的N型SiC层上;一石墨烯层,其是在非掺杂的SiC层上高温热解生成的;一欧姆接触电极,其制作在重掺杂的N型SiC衬底的背面,形成阴极电极;一肖特基接触电极,其制作在石墨烯层上,形成阳极电极。本发明可以降低肖特基二极管正向开启电压,减小反向漏电流。

Description

肖特基二极管及制备方法
技术领域
本发明涉及半导体材料与器件技术领域,尤其涉及碳化硅肖特基二极管及制备方法。
背景技术
肖特基二极管是一种利用热电子发射的二极管,结构和工艺相对比较简单,并且由于反向恢复时间极短,正向导通压降相对较低,因此在高频、低压、大电流等领域广泛应用。目前Si和GaAs等传统的肖特基二极管,由于材料特性的限制,难以满足对击穿电压和电流等器件性能的更高要求,SiC作为第三代半导体材料禁带宽度大,电子饱和速度高、临界击穿电场高、热导性能好、高温等特性,非常适合制造高频大功率肖特基二极管,目前性能优良的SiC肖特基二极管已经商业化应用。
但SiC肖特基二极管在性能上还存在较多问题,由于肖特基电极与半导体SiC的接触电阻较大,导致其导通电压比较高,同时由于受到n型碳化硅表面态的影响,肖特基接触势垒降低,增大了碳化硅肖特基二极管的反向漏电流。另外SiC基的肖特基二极管的反向击穿电压还有较大提高空间。
发明内容
本发明解决的技术问题是克服现有技术的不足,提供一种肖特基二极管及制备方法,可以降低肖特基二极管正向开启电压,减小反向漏电流。
本发明提供一种肖特基二极管,包含:
一重掺杂的N型SiC衬底;
一轻掺杂的N型SiC层,其生长在重掺杂的N型SiC衬底上;
一非掺杂的SiC层,其生长在轻掺杂的N型SiC层上;
一石墨烯层,其是在非掺杂的SiC层上高温热解生成的;
一欧姆接触电极,其制作在重掺杂的N型SiC衬底的背面,形成阴极电极;
一肖特基接触电极,其制作在石墨烯层上,形成阳极电极。
本发明还提供一种肖特基二极管的制备方法,包括如下步骤:
步骤1:在重掺杂的N型SiC衬底上外延轻掺杂的N型SiC层;
步骤2:在轻掺杂的N型SiC层上外延非掺杂的SiC层;
步骤3:将非掺杂的SiC层进行表面处理,在非掺杂的SiC层的表面进行高温热解生成石墨烯层;
步骤4:在重掺杂的N型SiC衬底的背面沉积Ti、Ni或Pt金属,制作欧姆接触电极,形成阴极电极;
步骤5:在热解生成的石墨烯层上沉积Ti、Ni或Al金属,制作肖特基接触电极,形成阳极电极。
本发明的上述技术方案具有如下优点和有益效果:在碳化硅半导体和肖特基金属之间加入一层石墨烯,有利于减小肖特基电极的接触电阻,减小了肖特基二极管的正向开启电压,使得在正向电压下,可以通过更大的电流。石墨烯插入层采用外延生长的非掺杂SiC经过高温热解原位生成石墨烯,避免了石墨烯的中间转移过程,不存在中间转移过程对石墨烯性能的损坏。原位生成的石墨烯有效降低碳化硅表面态,并对表面费米能级具有钉扎效应,提高肖特基二极管的势垒高度,减小反向漏电流,提高反向击穿电压。
附图说明
为使本发明的目的、技术方案和优点更加清楚明白,下面结合实施例及附图详细说明如后,其中:
图1示出了本发明提供的一种SiC肖特基二极管的剖视图;
图2示出根据本公开的实施例的制备方法的制作工艺流程图。
具体实施例
请参阅图1、图2所示,本发明提供一种肖特基二极管和制备方法,所述的肖特基二极管包含:
一重掺杂的N型SiC衬底10;其中所述重掺杂的N型SiC衬底10的净掺杂浓度大于1×1018cm3,其晶型为4H或者6H型单晶SiC。
一轻掺杂的N型SiC层20,其生长在重掺杂的N型SiC衬底10上;所述轻掺杂的N型SiC层20的净掺杂浓度为1×1015cm3至1×1017cm3,外延层厚度为1-20μm。该轻掺杂的N型SiC层20外延生长时延续了衬底的晶型结构。
一非掺杂的SiC层30,其生长在轻掺杂的N型SiC层20上;该非掺杂的SiC层30是用来制备石墨烯的,所以要求晶型为六方相单晶SiC,并且需要很高单晶晶体质量和表面平整度,厚度为2个碳-硅双原子层到30nm。
一石墨烯层301,其是在非掺杂的SiC层30上高温热解生成的;
一欧姆接触电极40,其制作在重掺杂的N型SiC衬底10的背面,形成阴极电极;
一肖特基接触电极5(),其制作在石墨烯层301上,形成阳极电极。
请再参阅图2及图1所示,本发明还提供的肖特基二极管制备方法包含以下步骤:
步骤1:在重掺杂的N型SiC衬底10上外延轻掺杂的N型SiC层20;其中所述重掺杂的N型SiC衬底10的净掺杂浓度大于1×1018cm3;所述轻掺杂的N型SiC层20的净掺杂浓度为1×1015cm3至1×1017cm3
步骤2:在轻掺杂的N型SiC层20上外延非掺杂的SiC层30,厚度为2个碳-硅双原子层到30nm;
步骤3:将非掺杂的SiC层30进行表面处理,通过化学清洗、高温氢刻蚀以及去氧化等工艺,去除表面污染物和表面划痕,形成光滑平整的原子台阶。然后在真空或惰性气氛的低压下,对非掺杂的SiC层30的表面进行高温热解,蒸发掉Si原子,形成石墨烯层301,优选的生成的石墨烯层301不超过两层。
步骤4:在重掺杂的N型SiC衬底10的背面,采用电子束蒸发沉积Ti、Ni或Pt金属,然后在800℃-1100℃温度范围内,在真空或惰性气体氛围中进行快速退火,制作欧姆接触电极40,形成阴极电极;
步骤5:在热解生成的石墨烯层301上,采用电子束蒸发沉积Ti、Ni、Al或Mo金属,制作肖特基接触电极50,形成阳极电极。
其中所述的在重掺杂的N型SiC衬底10上外延轻掺杂的N型SiC层20,以及轻掺杂的N型SiC层20外延非掺杂的SiC层30,均是采用CVD法外延。
以下结合具体实施例,并参照附图,对本发明进一步详细说明。
实施例一:
采用图2工艺流程制作出图1结构的SiC肖特基二极管:
(1)选取重掺杂的N型SiC衬底10,其净掺杂浓度为8×1018cm3,其晶型为6H型单晶SiC。通过CVD方法,在所述重掺杂的N型SiC衬底10上外延生长轻掺杂的SiC层20,该轻掺杂的N型SiC层20的净掺杂浓度为1×1016cm3,厚度为10μm。
(2)在所述轻掺杂的N型SiC层20上,继续CVD外延生长非掺杂的SiC层30,该非掺杂的SiC层30外延延续了衬底的六方结构,并且具有很高的单晶晶体质量和表面平整度,厚度为5nm。
(3)对所述的非掺杂的SiC层30进行高温热解制备石墨烯。在高温热解前,首先将外延层进行表面预处理,通过化学清洗、高温氢刻蚀以及去氧化等工艺,去除表面污染物和表面划痕,形成光滑平整的原子台阶。在真空下高温热解蒸发掉Si原子,形成单层的石墨烯层301。
(4)在所述的重掺杂的N型SiC衬底10的背面沉积欧姆接触电极40,采用电子束蒸发沉积Ni金属200nm,然后在900℃惰性气体N2保护下进行快速退火,形成欧姆接触电极40,作为该肖特基二极管的阴极电极。
(5)利用电子束蒸发,在所述的石墨烯层301上沉积Al金属200nm,制作肖特基接触电极50,作为该肖特基二极管的阳极电极。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (10)

1.一种肖特基二极管,包含:
一重掺杂的N型SiC衬底;
一轻掺杂的N型SiC层,其生长在重掺杂的N型SiC衬底上;
一非掺杂的SiC层,其生长在轻掺杂的N型SiC层上;
一石墨烯层,其是在非掺杂的SiC层上高温热解生成的;
一欧姆接触电极,其制作在重掺杂的N型SiC衬底的背面,形成阴极电极;
一肖特基接触电极,其制作在石墨烯层上,形成阳极电极。
2.根据权利要求1所述的肖特基二极管,其中所述非掺杂的SiC层的晶型为六方相单晶SiC。
3.根据权利要求1所述的肖特基二极管,其中所述重掺杂的N型SiC衬底的净掺杂浓度大于1×1018cm-3
4.根据权利要求1所述的肖特基二极管,其中所述轻掺杂的N型SiC层的净掺杂浓度为1×1015cm-3至1×1017cm-3
5.一种肖特基二极管的制备方法,包括如下步骤:
步骤1:在重掺杂的N型SiC衬底上外延轻掺杂的N型SiC层;
步骤2:在轻掺杂的N型SiC层上外延非掺杂的SiC层;
步骤3:将非掺杂的SiC层进行表面处理,在非掺杂的SiC层的表面进行高温热解生成石墨烯层;
步骤4:在重掺杂的N型SiC衬底的背面沉积Ti、Ni或Pt金属,制作欧姆接触电极,形成阴极电极;
步骤5:在热解生成的石墨烯层上沉积Ti、Ni或Al金属,制作肖特基接触电极,形成阳极电极。
6.根据权利要求5所述的肖特基二极管的制备方法,其中所述重掺杂的N型SiC衬底的净掺杂浓度大于1×1018cm-3;所述轻掺杂的N型SiC层的净掺杂浓度为1×1015cm-3至1×1017cm-3
7.根据权利要求5所述的肖特基二极管的制备方法,其中在重掺杂的N型SiC衬底上外延轻掺杂的N型SiC层,以及在轻掺杂的N型SiC层上外延非掺杂的SiC层,均是采用化学气相沉积即CVD法外延。
8.根据权利要求5所述的肖特基二极管的制备方法,其中非掺杂的SiC层表面处理后达到原子级平整度,高温热解是在高温真空或惰性气体氛围中Si原子蒸发形成石墨烯。
9.根据权利要求5所述的肖特基二极管的制备方法,其中在所述重掺杂的N型SiC衬底上采用电子束蒸发沉积Ti、Ni或Pt金属,然后在800℃-1100℃温度范围内,在真空或惰性气体氛围中进行快速退火,形成欧姆接触电极。
10.根据权利要求5所述的肖特基二极管的制备方法,其中在所述石墨烯层上采用电子束蒸发沉积Ti、Ni、Al或Mo金属,形成肖特基接触电极。
CN201810810551.2A 2018-07-23 2018-07-23 肖特基二极管及制备方法 Pending CN109004018A (zh)

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TWI782785B (zh) * 2020-11-11 2022-11-01 中國商蘇州晶湛半導體有限公司 二極體及其製造方法
CN113555497A (zh) * 2021-06-09 2021-10-26 浙江芯国半导体有限公司 一种高迁移率的SiC基石墨烯器件及其制备方法
CN113555497B (zh) * 2021-06-09 2023-12-29 浙江芯科半导体有限公司 一种高迁移率的SiC基石墨烯器件及其制备方法

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