CN108990318A - A kind of method for manufacturing circuit board of loophole lamination mistake proofing - Google Patents
A kind of method for manufacturing circuit board of loophole lamination mistake proofing Download PDFInfo
- Publication number
- CN108990318A CN108990318A CN201810833029.6A CN201810833029A CN108990318A CN 108990318 A CN108990318 A CN 108990318A CN 201810833029 A CN201810833029 A CN 201810833029A CN 108990318 A CN108990318 A CN 108990318A
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- China
- Prior art keywords
- core plate
- loophole
- lamination
- board
- internal layer
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a kind of method for manufacturing circuit board of loophole lamination mistake proofing, including the internal layer daughter board being made of at least two core plates, and two different PP are equipped between adjacent core plate, comprising the following steps: bore registration holes in the corresponding position of each core plate and PP；Unthreaded hole is drilled through in the corresponding angular position of each core plate and PP respectively, and by the lamination of internal layer daughter board sequence, successively reduces one by the loophole on the core plate of undermost core plate to top layer；Then internal layer circuit is made on different core plates respectively；Core plate and PP are superimposed together and are aligned by the sequence of loophole successively reduction, forms internal layer daughter board；Multi-layer board is pressed into after internal layer daughter board and outer copper foil are superimposed together by prepreg；Multi-layer board is processed into route board finished product by process after then carrying out.It can be reduced using the method for the present invention and the problem of lamination sequence error occur, effectively prevented plate caused by lamination mistake and scrap, and can effective improving production efficiency and reduction production cost.
Description
Technical field
The present invention relates to printed wiring board manufacture technology fields, and in particular to a kind of wiring board system of loophole lamination mistake proofing
Make method.
Background technique
For the fusion riveted pressing mode of PCB, it is divided into following steps:
S1, pre- plate-laying: being stacked core material and PP and aligned by design sequence, the rear side for using fusion or riveted
Formula is combined together；
S2, plate-laying: pre- plate-laying is added into outer copper foil and PP, builds up state to be laminated in order；
S3, pressing: above-mentioned superimposed sheet is pressed into multi-layer board.
During above-mentioned pre- plate-laying, manual type is generallyd use at present and stacks core material and PP, when adopting
PP includes at least two when being difficult to the variety classes differentiated, and is manually mixed up different types of PP during lamination, people
Work is also easy to obscure the core plate of different levels, and lamination sequence is easy to appear mistake, once error, pressing working procedure is difficult to screen bad
Product will continue to production to last electrical testing and scrap, and waste resources of production and increase production cost.
Summary of the invention
It is an object of the invention to provide a kind of wiring board system of loophole lamination mistake proofing to overcome existing technological deficiency
Make method, can be reduced using this method and the problem of lamination sequence error occur, effectively prevents plate caused by lamination mistake and scrap,
And it can effective improving production efficiency and reduction production cost.
In order to solve the above-mentioned technical problems, the present invention provides a kind of method for manufacturing circuit board of loophole lamination mistake proofing,
Including the internal layer daughter board being made of at least two core plates, and two different PP are equipped between adjacent core plate, comprising the following steps:
S1, registration holes are bored in the corresponding position of each core plate and PP；
S2, in the corresponding angular position of each core plate and PP unthreaded hole is drilled through respectively, and by the lamination of internal layer daughter board sequence,
One is successively reduced by the loophole on the core plate of undermost core plate to top layer；
S3, internal layer circuit then is made on different core plates respectively；
S4, core plate and PP are superimposed together and are aligned by the sequence of loophole successively reduction, then with fusion or riveting
The mode of conjunction is fixed, and internal layer daughter board is formed；
S5, internal layer daughter board and outer copper foil are superimposed together by prepreg, then pressing forms multi-layer board；
S6, first drill on multilayer boards, bored hole metallization then made by heavy copper and electric plating of whole board process, then according to
It is secondary to pass through production outer-layer circuit, production solder mask, surface treatment and molding, multi-layer board is processed into route board finished product.
Preferably, in step S1, four registration holes are bored in the corresponding position of each core plate and PP.
Preferably, in step S2, the light transmission number of perforations on lowest level core plate is identical as the lamination number of plies of internal layer daughter board.
Preferably, two different kinds of PP mono- and PP bis- is equipped between adjacent core plate, the PP mono- and PP bis- include
Two panels, and PP bis- described in two panels is placed between PP mono- described in two panels.
Preferably, the internal layer daughter board includes core plate one and core plate two, and the lamination sequence of internal layer daughter board is from top to bottom successively
For core plate one, PP mono-, PP bis-, PP bis-, PP mono-, core plate two；Before internal layer daughter board overlapping, in six light transmissions of upper right angular bit of core plate two
Hole, in five loopholes of upper right angular bit of first PP mono-, in four loopholes of upper right angular bit of first PP bis-, at second
Three loopholes of upper right angular bit of PP bis-, in two loopholes of upper right angular bit of second PP mono-, in the upper right angular bit of core plate one
One loophole；And when being overlapped into internal layer daughter board, per up folded one layer of loophole that will be covered in next layer.
Preferably, in step S5, the prepreg for pressing is with PP first is that identical.
Preferably, in step S4, whether just the rule of loophole reduction is detected by optical detection apparatus during lamination
Really, it detects and is fixed by way of fusion or riveted after lamination sequence is errorless.
Compared with prior art, the invention has the following beneficial effects:
The method of the present invention presses the lamination of internal layer daughter board by drilling through unthreaded hole on the PP in core plate and between core plate
The loophole that sequence is bored at every layer from lower to upper successively reduces one, i.e., will cover in next layer per up folded one layer one
A loophole manually carries out lamination by the rule of loophole successively reduction, can correctly distinguish the variety classes for being difficult to differentiate
PP, and then can reduce and the problem of lamination sequence error occur, and lamination sequence can be detected automatically by optical detection apparatus whether
Correctly, prevent the fault of artificial lamination, automatic detection can effective improving production efficiency, give up caused by effectively reducing because of lamination mistake
Product rate detects the lamination that re-starts of lamination sequence error, reduces the waste of material and resources of production, effectively reduces life
Produce cost.
Detailed description of the invention
Fig. 1 is the schematic diagram of internal layer daughter board lamination sequence in embodiment.
Specific embodiment
In order to more fully understand technology contents of the invention, below in conjunction with specific embodiment to technical side of the invention
Case is described further and illustrates.
Embodiment
As shown in figure, the present embodiment provides a kind of production methods of six sandwich circuit boards of loophole lamination mistake proofing, specifically
Technique is as follows:
(1), core plate 1, core plate 22 and two different kinds of sawing sheet: are outputed by jigsaw size 520mm × 620mm
The plate thickness of PP 1 and PP 24, core plate one and core plate two is 0.4mm, and outer copper foil is with a thickness of 0.5OZ.
(2), four punching: are bored in array distribution in the corresponding position of core plate 1, core plate 22, PP 1 and PP 24
Registration holes 5 (and rivet hole), then in six loopholes 6 of the upper right angular bit of core plate 22, in the upper right angular bit one of core plate 1
A loophole 6, in five loopholes 6 of upper right angular bit of a wherein PP 1, two light transmissions of upper right angular bit of another PP 1
Hole 6, in four loopholes 6 of upper right angular bit of a wherein PP 24, three loopholes 6 of upper right angular bit of another PP 24.
(3), internal layer circuit production (negative film technique): inner figure transfer, with vertical application machine respectively in core plate one and core
Light-sensitive surface, 8 μm of the film thickness monitoring of light-sensitive surface are coated on plate two；Using Full-automatic exposure machine, with (the 21 lattice exposure of 5-6 lattice exposure guide rule
Ruler) internal layer circuit exposure is completed on core plate one and core plate two respectively, it is developed, respectively on core plate one and core plate two in formation
Sandwich circuit figure；Internal layer etching, copper exposed after exposure development on core plate one and core plate two is removed by etching, is formed after moving back film
Internal layer circuit, it is 3mil that internal layer line width, which measures,；Internal layer AOI, then check internal layer circuit opens short circuit, route notch, route needle
The defects of hole, defective to scrap processing, flawless product goes out to downstream.
(4) pre- plate-laying: by lamination sequence, successively contraposition overlaps core plate 1, PP 1, PP 24, PP 21, PP from top to bottom
One 3, core plate 22 forms superimposed sheet；After overlapping, there are four light transmissions with core plate two and brill respectively there are five the PP mono- of loophole for brill
The PP bis- in hole is contacted, and being drilled with the PP mono- of two loopholes, with core plate one and there are three boring, the PP bis- of loophole is contacted respectively；On and
In stating, per one layer of loophole that will be covered in next layer is up folded by bottom core plate two, until remaining and core plate
The corresponding loophole of loophole on one is visible.
Among the above, optical detection apparatus is cooperated by light source during lamination whether just to detect lamination sequence automatically
Really；If detecting, the loophole of lamination process each layer from lower to upper is successively reduced by 6,5,4,3,2,1 order, correctly to arrange
Plate program, otherwise false alarm, is then overlapped the plate of lamination sequence error.
(5) riveted: detect that lamination sequence is correct, by registration holes rivet by superimposed sheet stake-fastening, in formation
Straton plate.
(6), press: (sequence generally overlapped is outer after being overlapped internal layer daughter board and outer copper foil in advance by prepreg
Layer copper foil, prepreg, internal layer daughter board, prepreg, outer copper foil), lamination appropriate is then selected according to plate Tg
Above-mentioned superimposed sheet is press-fitted together as one, six layers of multi-layer board is formed.
(7), outer layer drills: being drilled on multilayer boards according to borehole data using the mode of machine drilling.
(8), heavy copper: one layer of thin copper is deposited by way of chemical reaction on hole wall, is provided for subsequent electric plating of whole board
Basis, backlight test 10 grades, and the heavy copper thickness in hole is 0.5 μm.
(9), electric plating of whole board: according to the mechanism of electrochemical reaction, upper one layer of copper is electroplated on the basis of heavy copper, guarantees hole copper
Thickness reaches product requirement, sets electroplating parameter according to hole copper thickness is completed.
(10), outer-layer circuit (positive blade technolgy) is made: outer graphics transfer, it is luxuriant and rich with fragrance using Full-automatic exposure machine and positive route
Woods completes outer-layer circuit exposure with 5-7 lattice exposure guide rule (21 lattice exposure guide rule), developed, forms outer-layer circuit figure on multilayer boards
Shape；Outer graphics plating, then distinguishes copper facing and tin plating on multilayer boards, sets electroplating parameter according to desired completion copper thickness,
Copper facing is the current density electric plating of whole board 60min with 1.8ASD, and tin plating is that 10min is electroplated with the current density of 1.2ASD, and tin is thick
3-5μm；Then film is successively moved back again, etches and move back tin, etches outer-layer circuit on multilayer boards；Outer layer AOI, uses automated optical
Detection system detects whether outer-layer circuit has the defects of open circuit, notch, not clean, short-circuit etching by the comparison with CAM data.
(11), welding resistance, silk-screen character: by making green oil layer and silk-screen character in multi-layer board outer layer.
(12), surface treatment (heavy nickel gold): principle is learned in pad copper face Tonghua of welding resistance windowing position, and uniform deposition centainly requires
The nickel layer and layer gold of thickness, nickel layer thickness are as follows: 3-5 μm；Layer gold thickness are as follows: 0.05-0.1 μm.
(13), it forms: according to the prior art and pressing design requirement gong shape, six layer lines are made in the +/- 0.05mm of external form tolerance
Road plate.
(14), electrical testing: testing the electrically conducting performance of production board, this plate uses test method are as follows: flying probe.
(15), FQC: appearance, hole copper thickness, thickness of dielectric layers, green oil thickness, internal layer copper thickness of production board etc. are checked whether
Meet the requirement of client.
(16), it packs: according to the manner of packing and packaging quantity of customer requirement, packaging being sealed to production board, and
It is allowed to dry drying prescription and humidity card, then shipment.
It is provided for the embodiments of the invention technical solution above to be described in detail, specific case used herein
The principle and embodiment of the embodiment of the present invention are expounded, the explanation of above embodiments is only applicable to help to understand this
The principle of inventive embodiments；At the same time, for those skilled in the art, according to an embodiment of the present invention, in specific embodiment party
There will be changes in formula and application range, in conclusion the contents of this specification are not to be construed as limiting the invention.
Claims (7)
1. a kind of method for manufacturing circuit board of loophole lamination mistake proofing, including the internal layer daughter board being made of at least two core plates, and
Two different PP are equipped between adjacent core plate, which comprises the following steps:
S1, registration holes are bored in the corresponding position of each core plate and PP；
S2, in the corresponding angular position of each core plate and PP unthreaded hole is drilled through respectively, and by the lamination of internal layer daughter board sequence, by most
Loophole on the core plate of lower layer to the core plate of top layer successively reduces one；
S3, internal layer circuit then is made on different core plates respectively；
S4, core plate and PP are superimposed together and are aligned by the sequence of loophole successively reduction, then with fusion or riveted
Mode is fixed, and internal layer daughter board is formed；
S5, internal layer daughter board and outer copper foil are superimposed together by prepreg, then pressing forms multi-layer board；
S6, it first drills on multilayer boards, bored hole metallization is then made by heavy copper and electric plating of whole board process, is then successively passed through
Production outer-layer circuit, production solder mask, surface treatment and molding are crossed, multi-layer board is processed into route board finished product.
2. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 1, which is characterized in that in step S1,
Four registration holes are bored in the corresponding position of each core plate and PP.
3. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 1, which is characterized in that in step S2,
Light transmission number of perforations on lowest level core plate is identical as the lamination number of plies of internal layer daughter board.
4. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 3, which is characterized in that adjacent core plate it
Between to be equipped with two different kinds of PP mono- and PP bis-, the PP mono- and PP bis- include two panels, and PP bis- described in two panels is placed in two
Between PP mono- described in piece.
5. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 4, which is characterized in that the inner- electron
Plate includes core plate one and core plate two, and the lamination sequence of internal layer daughter board is followed successively by core plate one, PP mono-, PP bis-, PP bis-, PP from top to bottom
One, core plate two；Before internal layer daughter board overlapping, in six loopholes of upper right angular bit of core plate two, in the upper right angular bit of first PP mono-
Five loopholes, in four loopholes of upper right angular bit of first PP bis-, in three loopholes of upper right angular bit of second PP bis-,
In two loopholes of upper right angular bit of second PP mono-, in one loophole of upper right angular bit of core plate one.
6. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 5, which is characterized in that in step S5,
Prepreg for pressing is with PP first is that identical.
7. the method for manufacturing circuit board of loophole lamination mistake proofing according to claim 1, which is characterized in that in step S4,
Whether the rule for detecting loophole reduction by optical detection apparatus during lamination is correct, detects logical after lamination sequence is errorless
The mode for crossing fusion or riveted is fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810833029.6A CN108990318A (en) | 2018-07-26 | 2018-07-26 | A kind of method for manufacturing circuit board of loophole lamination mistake proofing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810833029.6A CN108990318A (en) | 2018-07-26 | 2018-07-26 | A kind of method for manufacturing circuit board of loophole lamination mistake proofing |
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| CN108990318A true CN108990318A (en) | 2018-12-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810833029.6A Pending CN108990318A (en) | 2018-07-26 | 2018-07-26 | A kind of method for manufacturing circuit board of loophole lamination mistake proofing |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109862703A (en) * | 2019-03-30 | 2019-06-07 | 奥士康科技股份有限公司 | A kind of localization method of mixed-compression board production |
| CN111148352A (en) * | 2019-12-25 | 2020-05-12 | 安徽中瑞通信科技股份有限公司 | Manufacturing process of PCB for 5G antenna |
| CN111148376A (en) * | 2019-12-24 | 2020-05-12 | 江门崇达电路技术有限公司 | Laminating method of thick dielectric layer PCB |
| CN111757613A (en) * | 2020-05-22 | 2020-10-09 | 东莞联桥电子有限公司 | Circuit board manufacturing method |
| CN112033294A (en) * | 2020-08-17 | 2020-12-04 | 胜宏科技（惠州）股份有限公司 | Method for identifying whether PP (polypropylene) sheets are correctly stacked |
| CN112272454A (en) * | 2020-09-28 | 2021-01-26 | 江门崇达电路技术有限公司 | Method for preventing PCB (printed circuit board) from laminating, fusing and glue flowing |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203040033U (en) * | 2013-01-29 | 2013-07-03 | 北大方正集团有限公司 | Riveting operating platform and riveting device |
| CN104519681A (en) * | 2014-11-19 | 2015-04-15 | 沪士电子股份有限公司 | Manufacturing method of ultralarge line-card type printed circuit boards with large layer number and high alignment degree |
| CN105208789A (en) * | 2015-09-18 | 2015-12-30 | 深圳诚和电子实业有限公司 | Manufacturing method of battery circuit board |
| US20160087325A1 (en) * | 2012-12-20 | 2016-03-24 | Telekom Malaysia Berhad | Processes For Forming Waveguides Using LTCC Substrates |
-
2018
- 2018-07-26 CN CN201810833029.6A patent/CN108990318A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160087325A1 (en) * | 2012-12-20 | 2016-03-24 | Telekom Malaysia Berhad | Processes For Forming Waveguides Using LTCC Substrates |
| CN203040033U (en) * | 2013-01-29 | 2013-07-03 | 北大方正集团有限公司 | Riveting operating platform and riveting device |
| CN104519681A (en) * | 2014-11-19 | 2015-04-15 | 沪士电子股份有限公司 | Manufacturing method of ultralarge line-card type printed circuit boards with large layer number and high alignment degree |
| CN105208789A (en) * | 2015-09-18 | 2015-12-30 | 深圳诚和电子实业有限公司 | Manufacturing method of battery circuit board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109862703A (en) * | 2019-03-30 | 2019-06-07 | 奥士康科技股份有限公司 | A kind of localization method of mixed-compression board production |
| CN111148376A (en) * | 2019-12-24 | 2020-05-12 | 江门崇达电路技术有限公司 | Laminating method of thick dielectric layer PCB |
| CN111148352A (en) * | 2019-12-25 | 2020-05-12 | 安徽中瑞通信科技股份有限公司 | Manufacturing process of PCB for 5G antenna |
| CN111757613A (en) * | 2020-05-22 | 2020-10-09 | 东莞联桥电子有限公司 | Circuit board manufacturing method |
| CN112033294A (en) * | 2020-08-17 | 2020-12-04 | 胜宏科技（惠州）股份有限公司 | Method for identifying whether PP (polypropylene) sheets are correctly stacked |
| CN112272454A (en) * | 2020-09-28 | 2021-01-26 | 江门崇达电路技术有限公司 | Method for preventing PCB (printed circuit board) from laminating, fusing and glue flowing |
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Application publication date: 20181211 |