CN108962845A - Integrated antenna package, its manufacturing method and the wearable device including the encapsulation - Google Patents

Integrated antenna package, its manufacturing method and the wearable device including the encapsulation Download PDF

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Publication number
CN108962845A
CN108962845A CN201810808732.1A CN201810808732A CN108962845A CN 108962845 A CN108962845 A CN 108962845A CN 201810808732 A CN201810808732 A CN 201810808732A CN 108962845 A CN108962845 A CN 108962845A
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China
Prior art keywords
chip
printed circuit
circuit board
moulding unit
integrated antenna
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Granted
Application number
CN201810808732.1A
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Chinese (zh)
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CN108962845B (en
Inventor
郑灿憙
朴寿财
金荣勋
姜仁九
金希烈
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN108962845A publication Critical patent/CN108962845A/en
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Publication of CN108962845B publication Critical patent/CN108962845B/en
Expired - Fee Related legal-status Critical Current
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    • HELECTRICITY
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    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

A kind of integrated antenna package includes: at least one first chip, is mounted in the firstth area of the mounting surface of printed circuit board;Moulding unit, covering implement mounting surface and surround at least one described first chip;Electromagnetic shielding film covers the surface of the moulding unit and surrounds at least one described first chip;And second chip, it is mounted in the secondth area of the mounting surface.Second chip is exposed to outside the electromagnetic shielding film and is spaced apart with the printed circuit board, wherein the moulding unit is between the second chip and the printed circuit board.

Description

Integrated antenna package, its manufacturing method and the wearable device including the encapsulation
The application be submit on June 13rd, 2017, application No. is 201710445270.7, entitled " integrated electricity The divisional application of the patent application of road encapsulation, its manufacturing method and the wearable device including the encapsulation ".
Cross reference to related applications
It is submitted in Korean Intellectual Property Office on September 23rd, 2016 entitled: " Integrated Circuit Package, Method of Fabricating the Same, and Wearable Device Including Integrated The South Korea patent application No.10-2016-0122379 of Circuit Package " is incorporated herein in its entirety by reference.
Technical field
Embodiment is related to a kind of integrated antenna package, its manufacturing method and wearable including the integrated antenna package and sets It is standby, more particularly, to a kind of integrated antenna package comprising semiconductor including multiple chips and electromagnetic shielding film Encapsulation, its manufacturing method and the wearable device including the integrated antenna package.
Background technique
Recently, the electronic equipment of such as smart phone rapid proliferation, system in package (SiP) module and utilizes these The exploitation of the wearable device of SiP module and popularize more and more, wherein SiP module passes through multiple independent semiconductor chip collection It is obtained as an encapsulation, the multiple independent semiconductor chip executes various function and with electronic equipment interworking Energy.SiP module, especially high-frequency semiconductor package module need electromagnetic armouring structure ensuring to electromagnetic interference (EMI) and/or The resistance of radio frequency interference (RFI).However, some chips needs for constituting SiP module are separated and are exposed with electromagnetic armouring structure.
Summary of the invention
Embodiment is related to claim language to be added (CLAIM LANGUAGE TO BE ADDED)
One or more embodiments provide integrated antenna package, comprising: printed circuit board;At least one first chip, peace It is attached to the firstth area of the mounting surface of printed circuit board;Moulding unit covers at least one described in the mounting surface and encirclement First chip;Electromagnetic shielding film covers the surface of the moulding unit and surrounds at least one described first chip;With the second core Piece is mounted to the secondth area of the mounting surface to be exposed to outside the electromagnetic shielding film and between the printed circuit board It separates, wherein the moulding unit is between second chip and the printed circuit board, wherein the moulding unit packet Include: chip protects moulding unit, covers at least one described first chip above firstth area;It is moulded with substrate protective single Member has the thickness smaller than chip protection moulding unit, extends between the printed circuit board and second chip, And there is step and concave surface on the top surface of the substrate protective moulding unit, the concave surface is limited by the step.
One or more embodiments provide integrated antenna packages, comprising: printed circuit board, including mounting surface and be exposed to Multiple conductive welding disks in the mounting surface, the mounting surface have the firstth area and adjacent with firstth area second Area;At least one first chip is mounted on above firstth area;Moulding unit is included in above firstth area and covers institute State the chip protection moulding unit and substrate protective moulding unit of at least one the first chip, the substrate protective moulding unit tool There is the thickness smaller than chip protection moulding unit, extends in secondth area, and mould list in the substrate protective There is step and concave surface, the concave surface is limited by the step on the top surface of member;Electromagnetic shielding film extends described first The moulding unit is covered in area and secondth area, and has expose the concave surface above secondth area to open Mouthful;With the second chip, it is connected to and penetrating the connecting elements of the substrate protective moulding unit in secondth area from described At least one conductive welding disk selected in multiple conductive welding disks, and the electromagnetism is at least partially exposed to by the opening The outside of screened film.
One or more embodiments provide a kind of wearable device comprising main body and for dressing the master by user The wearable unit of body, wherein the main body includes at least one collection of the IDE for the embodiment conceived according to the present invention At circuit arrangement.
One or more embodiments provide the method for manufacture integrated antenna package, this method comprises: preparing includes installation Surface and the printed circuit board being exposed to including multiple conductive welding disks in the mounting surface, the mounting surface have first Area and secondth area adjacent with firstth area;At least one first chip is installed above firstth area;It is single to form molding Member, the moulding unit cover firstth area and secondth area and surround at least one described first chip;Form electricity Magnetic shield film, the electromagnetic shielding film cover the moulding unit in firstth area and secondth area;By second Remove the electromagnetic shielding film area's upper section to form opening, the opening penetrates the electromagnetic shielding film;Pass through part Ground removal forms step on the top surface in secondth area in the moulding unit by the moulding unit of the opening exposure The concave surface and;Form at least one connecting hole for penetrating the moulding unit in secondth area;In at least one described connection Connecting elements is formed in hole;With the second chip is installed above secondth area, second chip passes through the connecting elements At least one conductive welding disk being connected in the multiple conductive welding disk.
Detailed description of the invention
Exemplary embodiment is described in detail by reference to attached drawing, feature will become aobvious and easy for those skilled in the art See, in the accompanying drawings:
Fig. 1 shows the cross-sectional view of integrated antenna package according to the embodiment;
Fig. 2 shows the cross-sectional views according to the integrated antenna packages of other embodiments;
Fig. 3 shows the cross-sectional view of the integrated antenna package according to other embodiment;
Fig. 4 shows the cross-sectional view of the integrated antenna package according to another embodiment;
Fig. 5 A to Fig. 5 G shows the cross section in each stage in the method for manufacture integrated antenna package according to the embodiment Figure;
Fig. 6 A to Fig. 6 E shows the cross in each stage in the method according to the manufacture integrated antenna package of other embodiments Sectional view;
Fig. 7 A to Fig. 7 E shows each stage in the method according to the manufacture integrated antenna package of other embodiment Cross-sectional view;
Fig. 8 A and Fig. 8 B show the figure of wearable device according to the embodiment;And
Fig. 9 shows the block diagram of wearable device according to the embodiment.
Specific embodiment
Hereinafter, embodiment will be described in detail with reference to the accompanying drawings.Throughout the specification, identical component will be by identical Appended drawing reference indicates, and will omit its repetitive description.
Fig. 1 is the cross-sectional view of integrated antenna package according to the embodiment.With reference to Fig. 1, integrated antenna package 100 be can wrap Printed circuit board 110, the multiple chips 130 for being installed to printed circuit board 110 are included, only covers and selects from multiple chips 130 The moulding unit 140 and electromagnetic shielding film 150 of some chips, the surface of the Overmolded unit 140 of electromagnetic shielding film 150, but At least one chip in multiple chips 130 is not covered is exposed to the region outside electromagnetic shielding film 150.
Printed circuit board 110 may include printed circuit board, flexible printed circuit board, rigid and flexible printed circuit board Or combinations thereof.Printed circuit board 110 may include: substrate body 112, have the mounting surface for being mounted with multiple chips 130 The 112A and rear surface 112B opposite with mounting surface 112A;Multiple conductive welding disk 114A, 114B, 114C and 114D, exposure On the mounting surface 112A or rear surface 112B of substrate body 112;With insulating protective layer 118, the multiple conductive welding disks of exposure 114A, 114B, 114C and 114D and the mounting surface 112A and rear surface 112B for covering substrate body 112.Insulating protective layer 118 Multiple hole 118H including exposure multiple conductive welding disk 114A, 114B, 114C and 114D.
In some embodiments, substrate body 112 can have the single base substrate including multiple circuit patterns Single layer structure.In some other embodiments, substrate body 112 can have the multilayer knot for wherein stacking multiple base substrates Structure, and can shape between two in each multiple base substrates of leisure for multiple circuit patterns of the electrical connection between layer At.Multiple circuit patterns may be coupled to be exposed to it is multiple on the mounting surface 112A or rear surface 112B of substrate body 112 Conductive welding disk 114A, 114B, 114C and 114D, so that multiple circuit patterns, which are electrically connected to, is installed to the more of printed circuit board 110 A chip 130 simultaneously provides path for transmitting electric signal.In some embodiments, multiple circuit patterns may include multiple pass through Energization pole and/or multiple wiring layers, each wiring layer extend between two in multiple base substrates, and multiple through electrodes are worn Saturating base substrate.Multiple through electrodes and multiple wiring layers may include copper (Cu), aluminium (Al), nickel (Ni), stainless steel or its group It closes, but embodiment is without being limited thereto.
The mounting surface 112A of printed circuit board 110 has the first area I and second area II adjacent with the first area I.One In a little embodiments, the first area I can have the ring structure for surrounding the second area II.Ring structure can have various planar shapeds Shape, such as polygon, circle, ellipse etc..In some other embodiments, the second area II can be arranged in the side of the first area I At edge, so that the first area I partly surrounds the second area II.The flat shape of first area I and the second area II are not particularly limited, root According to needs, each of the first area I and the second area II can have various flat shapes.
In the embodiment in figure 1, multiple conductive welding disk 114A, 114B and 114C are exposed to the installation table of substrate body 112 On the 112A of face, and multiple conductive welding disk 114D are exposed on the rear surface 112B of substrate body 112.Multiple conductive welding disks 114A, 114B, 114C and 114D may include and constitute the identical material of multiple wiring layers of substrate body 112, or can be with Metal including such as copper (Cu).In some embodiments, the multiple conductive welding disk 114A, 114Bs opposite with substrate body 112, The surface of 114C and 114D can be coated with organic solderability preservative (OSP) surface-treated layer.OSP surface-treated layer can wrap Include Ni, Au, palladium (Pd), silver-colored (Ag) or its alloy and imidazolium compounds or azole compounds.
Insulating protective layer 118 can protect including the circuit pattern in printed circuit board 110, and prevent circuit pattern Between solder bridging generation.Insulating protective layer 118 may include insulating coating film, such as solder resist.Solder resist may include light Resist, epoxy resin, polyimides, polyester etc. are caused, but not limited to this.
The first of mounting surface 112A can be formed in as the first some chips 132 and 134 in multiple chips 130 Above area I.First chip 132 and 134 can be connected to by the first connecting elements 122 multiple conductive welding disk 114A, 114B, Multiple conductive welding disk 114A in 114C and 114D, multiple conductive welding disk 114A are formed on the first area I of mounting surface 112A. Although the example that the first chip of two of them 132 and 134 is mounted on above the first area I is shown in FIG. 1, embodiment is unlimited In example shown in FIG. 1.One the first chip or three or more first chips may be mounted above the first area I.
The second chip 136 as one of multiple chips 130 can be formed in above the second area II of mounting surface 112A. Second chip 136 can be connected in multiple conductive welding disk 114A, 114B, 114C and 114D by the second connecting elements 126 Multiple conductive welding disk 114B, multiple conductive welding disk 114B are formed on the second area II of mounting surface 112A.Second connecting elements 126 can have the double-layer structure including lower connecting elements 126L and upper connecting elements 126U, according to the order in conduction On pad 114B.Lower connecting elements 126L and upper connecting elements 126U may include identical material.Although being shown in FIG. 1 One of them second chip 136 is mounted on the example above the second area II, but embodiment is without being limited thereto.For example, as needed, using It may be mounted on the second area II in multiple second chips for executing different function.
Each of first connecting elements 122 and the second connecting elements 126 may include electrically conductive paste.Electrically conductive paste can To include the mixture of solder powder and solder flux or the formula of solder powder and epoxy resin.In some embodiments, solder powder End may include tin (Sn), Sn- lead (Pb), Sn-Ag-Cu, Sn-Ag, Sn-Cu, Sn- bismuth (Bi), Sn- zinc (Zn)-Bi, Sn-Ag- Bi, Sn-Ag-Zn, indium (In)-Sn, In-Ag, Sn-Pb-Ag, In-Pb, Sn-Pb-Bi, Sn-Pb-Bi-Ag etc., but embodiment is not It is limited to this.
First chip 132 and 134 and the second chip 136 can be the chip for executing different function.In some embodiments In, each of the first chip 132 and 134 and the second chip 136 can be controller chip, nonvolatile memory core Piece, volatile memory chip, illusory chip or passive device.Nonvolatile memory chip may include that such as NAND dodges It deposits, resistive ram (RRAM), magnetic resistance RAM (MRAM), phase transformation RAM (PRAM) or ferroelectric RAM (FRAM).First core Piece 132 and 134 and the second chip 136 may include various multiple independent devices.Multiple independent devices may include Various microelectronic components, such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET), system lsi (be Unite LSI), it is the imaging sensor of such as cmos imaging sensor (CIS) etc, MEMS (MEMS), active device, passive Device etc..In some embodiments, the second chip 136 for being mounted on above the second area II may include controller, non-volatile Memory, volatile memory, sensor module, display, camera model or audio-frequency module.In some embodiments, second Chip 136 may include at least one sensor, such as bio signal sensing sensor, GPS sensor (GPS) etc..Example Such as, the second chip 136 may include bio signal sensing sensor, for detecting blood pressure, heart rate variability (HRV), heart rate prison Survey (HRM), photo-plethysmographic (PPG), sleep interval, skin temperature, heart rate, blood flow, blood glucose, oxygen saturation, pulse wave and At least one of electrocardiogram (ECG), but embodiment is without being limited thereto.
In multiple chips 130, moulding unit 140 can cover 132 He of the first chip being mounted on above the first area I 134, and the second chip 136 being mounted on above the second area II can not be covered.Moulding unit 140 may include covering first The first chip 132 and 134 above area I chip protection moulding unit 142 and on the second area II extend and have than The substrate protective moulding unit 144 for the thickness that chip protects moulding unit 142 small.
Chip protection moulding unit 142 can protect the first chip 132 and 134 being mounted on above the first area I.Especially Ground, the first chip 132 and 134 can be completely covered in chip protection moulding unit 142, in addition to these chips and the first connecting elements Except contact, for example, chip protection moulding unit 142 can be in the upper surface, side surface and bottom table of the first chip 132 and 134 On face.
Substrate protective moulding unit 144 can protect the insulating protective layer 118 on the second area II from light, moisture, outside Impact etc..Moulding unit 140 can have wherein chip protection moulding unit 142 and substrate protective moulding unit 144 and connect each other It is connected in integrated structure.
Second connecting elements 126 can penetrate substrate protective moulding unit 144.Second connecting elements 126 can be by second Chip 136 is connected to conductive welding disk 114B, and substrate protective moulding unit 144 is in the second chip 136 and conductive welding disk 114B Between.
In the second area II, the top surface of substrate protective moulding unit 144 can have step ST and be limited by step ST Concave surface RS1.Substrate protective moulding unit 144 may include: marginal portion 144E, surround concave surface RS1 and its top surface It is electromagnetically shielded by the grounding wire the covering of film 150;And central part 144C, it is surrounded by marginal portion 144E and there is concave surface RS1.Edge part The thickness for dividing the thickness of 144E that can be less than chip protection moulding unit 142, and the thickness of central part 144C can be less than The thickness of marginal portion 144E.As it is used herein, term " thickness " can refer to along the extension side with printed circuit board 110 To the size in vertical direction (Z-direction).
In printed circuit board 110, such as in X-Y plane, the area that is occupied by substrate protective moulding unit 144 can be with Greater than the area occupied by the second chip 136.The height of the top surface of substrate protective moulding unit 144 can be less than the second chip The height of 136 bottom surface.As it is used herein, term " height " can refer to along the extension side with printed circuit board 110 To the vertical distance of direction (Z-direction) away from printed circuit board 110.Second chip 136 can be with substrate protective moulding unit 144 It is vertically spaced.Second chip 136 can be arranged in above the RS1 of concave surface be stacked on the RS1 of concave surface in the vertical direction, such as It is stacked in Z-direction on entire concave surface RS1.Second chip 136 can extend in X-direction and/or Y-direction, in z-direction extremely It is partially stacked on the 144E of marginal portion, while spaced away in z-direction.
In some embodiments, moulding unit 140 may include epoxy resin mould produced compounds (EMC).In some implementations In example, moulding unit 140 may include Si sill, thermosetting material, thermoplastic material, UV curable material etc..Work as molding When unit 140 includes thermosetting material, moulding unit 140 may include curing agent and acrylic polymer additive.Curing agent It may include phenolic, acid anhydrides type or amine type material.In some embodiments, moulding unit 140 may include resin, and can be with It further comprise as needed silica filler.In some embodiments, it is located at the first chip 132 and 134 and printed circuit A part of moulding unit 140 between plate 110 can be the Underfill layer formed by capillary underfilling methods.
Electromagnetic shielding film 150 can conformally cover the surface of the first area I and the moulding unit 140 in the second area II.Electricity Magnetic shield film 150 can be connected in multiple conductive welding disk 114A, 114B, 114C and 114D by third connecting elements 128 Conductive welding disk 114C, conductive welding disk 114C are formed in the first area I of mounting surface 112A.Conductive welding disk 114C can formed It is formed at the highest distance position away from the second area II in multiple conductive welding disk 114A and 114C in the first area I.Conductive welding disk 114C can be ground electrode.
Opening 150H is formed in electromagnetic shielding film 150, so that the second chip 136 exposure being mounted on above the second area II In the outside of electromagnetic shielding film 150.Opening 150H can make the concave surface RS1 of the substrate protective moulding unit 144 in the second area II (such as its entire concave surface) exposure, and can not extend in z-direction along the side of step ST.Second chip 136 can be with It is aligned and is arranged in above the concave surface RS1 of substrate protective moulding unit 144 with the opening 150H of electromagnetic shielding film 150.Second Chip 136 can along the Z direction with chip protection moulding unit 142 be spaced apart, wherein electromagnetic shielding film 150 with concave surface RS1 Adjacent edge is located between the second chip 136 and chip protection moulding unit 142.
The step ST of substrate protective moulding unit 144 can be with the inner sidewall pair of the opening 150H in electromagnetic shielding film 150 Standard, so that step ST has the surface of the vertical extension line for the inner sidewall for being continuously attached to opening 150H.As shown in Figure 1, opening The width W1 of mouth 150H can be less than the second chip 136 in the horizontal direction (X parallel with the extending direction of printed circuit board 110 Direction) on width W2.However, this is only example, and the width W1 for the 150H that is open can be equal to or more than the second chip 136 Width W2.When the width W1 for the 150H that is open is greater than the width W2 of the second chip 136, the inner sidewall for the 150H that is open and the second core Maximum separation distance between piece 136 can be about 50 μm or less.Pass through the inner sidewall and the second chip 136 of the 150H that will be open Between separation distance be minimised as about 50 μm or less, make the separation distance between electromagnetic shielding film 150 and the second chip 136 It minimizes, to improve the electromagnetic shielding capability of encapsulation, and the size of the encapsulation due to caused by separation distance is inhibited to increase.
In some embodiments, the flat shape of the concave surface RS1 in substrate protective moulding unit 144 can be by being electromagnetically shielded The opening 150H of film 150 is limited, and the 150H and concave surface RS1 that is open can have identical flat shape.
Electromagnetic shielding film 150 includes: the first shielded segment 150A, conformally covers the chip protection mould on the first area I The top surface and side wall of unit 142 processed;And secondary shielding part 150B, it is covered on the secondth area around the second chip 136 The top surface of substrate protective moulding unit 144 on II.Secondary shielding part 150B can be from the first shielded segment 150A towards Two chips 136 are horizontally extended with the extending direction for being parallel to printed circuit board 110.The top surface of secondary shielding part 150B Height can be less than the height of the bottom surface towards secondary shielding part 150B of the second chip 136.In addition, the first shielded segment The height of the top surface of 150A can be less than the height of the top surface of the second chip 136, so that the second chip is in electromagnetic shielding film 150 tops are prominent, while being partly stacked on electromagnetic shielding film 150 in three directions.
Second chip 136 can be connected to leading in the second area II of mounting surface 112A by the second connecting elements 126 Electrical bonding pads 114B.Second connecting elements 126 can be and penetrating substrate protective moulding unit 144 from the top of moulding unit 140 Side extends to conductive welding disk 114B.
In some embodiments, electromagnetic shielding film 150 may include can by absorbing laser beam (such as wavelength is Infrared (IR) laser beam or wavelength of 1064nm is the green laser beam of 532nm) come the material that reacts.In some embodiments, Electromagnetic shielding film 150 may include the conductive material containing polymer.For example, electromagnetic shielding film 150 may include metal, conductive gold Category-polymer complex or metal paste.For example, electromagnetic shielding film 150 can be conductive metal-polymer complex, such as have There is the polyurethane of Ag particle.In some other embodiments, electromagnetic shielding film 150 may include single-layer or multi-layer.For example, electromagnetism Screened film 150 can have the multilayered structure that bonding layer, conductive material layer and protective layer are laminated in the following order.Bonding layer can wrap Include Ni, Cu, titanium (Ti), chromium (Cr), stainless steel or combinations thereof.Conductive material layer may include Cu, Ag or their combination.Protection Layer may include Ni or stainless steel.
Fig. 2 is the cross-sectional view according to the integrated antenna package of other embodiments.In Fig. 2, with attached drawing identical in Fig. 1 Label indicates identical component, will omit descriptions thereof.
With reference to Fig. 2, integrated antenna package 200 has substantially the same with the configuration of integrated antenna package 100 shown in FIG. 1 Configuration.However, the top surface of substrate protective moulding unit 144 can have to be limited by step ST in integrated antenna package 200 Fixed concave surface RS2, the second chip 236 being mounted on above the second area II in multiple chips 130 are inserted into electromagnetic shielding In the opening 250H of film 150, and it is arranged in above the concave surface RS2 of substrate protective moulding unit 144.The width W3 of opening 250H can To be greater than width W4 of second chip 236 in the horizontal direction (X-direction) parallel with the extending direction of printed circuit board 110. In other words, the second chip 236 and electromagnetic shielding film 150 overlap in the X direction (rather than in z-direction), for example, the second core Piece 236 can be Chong Die with the entire side wall of electromagnetic shielding film 150 in opening 250H.
Here, the separation distance between the inner sidewall and the second chip 236 by making opening 250H is minimised as about 50 μm Or it is less, minimize the separation distance between electromagnetic shielding film 150 and the second chip 236, to improve the electromagnetic screen of encapsulation Ability is covered, and the size of the encapsulation due to caused by separation distance is inhibited to increase.The details and reference Fig. 2 of second chip 236 describe The second chip 136 details it is identical.
Fig. 3 is the cross-sectional view according to the integrated antenna package of other embodiment.It is and identical attached in Fig. 1 in Fig. 3 Icon note indicates identical component, will omit descriptions thereof.
With reference to Fig. 3, integrated antenna package 300 has substantially the same with the configuration of integrated antenna package 100 shown in FIG. 1 Configuration.However, printed circuit board 110 includes the mounting surface 112A with substrate body 112 in integrated antenna package 300 The ground electrode 314C for separating and being at least partly embedded in substrate body 112.Ground electrode 314C can be exposed to printed circuit The outside of the side surface of plate 110.In addition, electromagnetic shielding film 350 includes the opening 350H of exposure concave surface RS1 and extends to cover The substrate shield part 352 of the side surface of printed circuit board 110.The inner surface of substrate shield part 352 in printed circuit board The ground electrode 314C contact of exposure at 110 side surface.The details of electromagnetic shielding film 350 and electromagnetic shielding described in reference diagram 1 The details of film 150 is substantially the same.
Fig. 4 is the cross-sectional view according to the integrated antenna package of another embodiment.It is and identical attached in Fig. 1 in Fig. 4 Icon note indicates identical component, will omit descriptions thereof.
With reference to Fig. 4, integrated antenna package 400 has substantially the same with the configuration of integrated antenna package 100 shown in FIG. 1 Configuration.However, in integrated antenna package 400, printed circuit board 110 include multiple conductive welding disk 114A, 114B, 114D and 414.Conductive welding disk 414 in multiple conductive welding disk 114A, 114B, 114D and 414 can be exposed to the installation of substrate body 112 The outside of printed circuit board 110 between the first area I and the second area II of surface 112A.
Similar to moulding unit 140 shown in FIG. 1, moulding unit 440 includes on the first area I of covering mounting surface 112A The chip of first chip 132 and 134 of side protects moulding unit 442 and extends on the second area II and have than chip The substrate protective moulding unit 444 for the thickness for protecting moulding unit 442 small.However, chip protection moulding unit 442 and substrate are protected Shield moulding unit 444 is separated from each other, and shielding space 440S (see Fig. 7 B) is located at chip protection moulding unit 442 and substrate It protects between moulding unit 444, shielding space 440S is between the first area I and the second area II.Shielding space 440S is by electromagnetism Screened film 450 is filled.In addition, the top surface of substrate protective moulding unit 444 can have step ST4 and be limited by step ST4 Concave surface RS4.Therefore, substrate protective moulding unit 444 may include: marginal portion 444E, surrounds concave surface RS4 and has It is electromagnetically shielded by the grounding wire the top surface and side wall of the covering of film 450;And central part 444C, it is surrounded and is had by marginal portion 444E Concave surface RS4.Marginal portion 444E can have the thickness of the thickness less than chip protection moulding unit 442, and central part 444C can have the thickness of the thickness less than marginal portion 444E.
Electromagnetic shielding film 450 can chip protect extend between moulding unit 442 and substrate protective moulding unit 444 with The side wall and substrate protective moulding unit 444 of covering chip protection moulding unit 442 in shielding space 440S (referring to Fig. 7 B) Side wall.Side wall shielded segment 454 can be electrically connected to conductive welding disk 414 by connecting elements 428.Conductive welding disk 414 can be with It is ground electrode.
The details and conductive welding disk of conductive welding disk 414, connecting elements 428, moulding unit 440 and electromagnetic shielding film 450 The details substantially phase of 114A, 114B, 114C and 114D, the first connecting elements 122, moulding unit 140 and electromagnetic shielding film 150 Together, it is described by reference to Fig. 1.
The second chip 436 above the second area II being mounted in multiple chips 130 can be arranged in substrate protective molding It is stacked on the opening 450H in electromagnetic shielding film 450 in the vertical direction above the concave surface RS4 of unit 444, in the second chip 436 Position at.The details of second chip 436 is generally identical as the details of the second chip 136 of reference Fig. 1 description.
Fig. 5 A to Fig. 5 G be show it is according to the embodiment manufacture integrated antenna package method in each stage it is transversal Face figure.The method that reference Fig. 5 A to Fig. 5 G description is manufactured into integrated antenna package 100 shown in FIG. 1.In Fig. 5 A to Fig. 5 G, with Identical appended drawing reference indicates identical component in Fig. 1, will omit descriptions thereof.
With reference to Fig. 5 A, prepare printed circuit board 110.It, can be in substrate body 112 in order to prepare printed circuit board 110 Multiple conductive welding disk 114A, 114B, 114C and 114D are formed on mounting surface 112A and rear surface 112B, are formed insulation later and are protected Sheath 118 covers the mounting surface 112A and rear surface 112B of substrate body 112, so that multiple conductive welding disk 114A, 114B, 114C and 114D are exposed, and substrate body 112 has single layer structure or is stacked the multilayered structure of multiple base substrates, The single layer structure includes the single base substrate including multiple circuit pattern (not shown).
Conductive welding disk 114C can be with ground electrode, and electromagnetic shielding film 150 is connected to the ground electrode in subsequent technique.One In a little embodiments, at least one conductive welding disk 114C can be formed on the two sides of printed circuit board 110.In some other implementations In example, conductive welding disk 114C may include the line pattern extended along the outer edge of the first area I with annular.
With reference to Fig. 5 B, multiple conductive welding disk 114A, 114B on the mounting surface 112A for being exposed to substrate body 112 and Soldering paste is supplied on 114C, and multiple connecting elements 122,126P and 128 are consequently formed.Multiple connecting elements 122,126P and 128 can To include: the first connecting elements 122 formed on multiple conductive welding disk 114A on the first area I of mounting surface 112A;? The third connecting elements 128 formed on conductive welding disk 114C, conductive welding disk 114C are located at the side of the first area I of mounting surface 112A At edge, the edge of the first area I is far from the second area II;With multiple conductive welding disk 114B on the second area II of mounting surface 112A The preliminary second connecting elements 126P of upper formation.
Next, the first chip 132 and 134 is mounted on above the first area I, while exposure 128 He of third connecting elements Preliminary second connecting elements 126P.First chip 132 and 134 can be connected to multiple conductive welderings by the first connecting elements 122 Disk 114A.When installing the first chip 132 and 134, multiple conductive welding disk 114B and 114C are by preliminary second connecting elements 126P It is protected with third connecting elements 128.Due to can protect multiple conductive welding disk 114B and 114C from vibration, impact, moisture, outer Portion's pollution etc., it is possible to prevent multiple conductive welding disk 114B and 114C to be damaged or deteriorate and reliability can be kept.
In some embodiments, although solder jetting method can be used formed multiple connecting elements 122,126P and 128, but embodiment is without being limited thereto.For example, plating can be used, change in order to form multiple connecting elements 122,126P and 128 Learn plating, vacuum deposition, printing, soldered ball transfer or stud protrusion etc..
With reference to Fig. 5 C, moulding unit 140 is formed as covering the first area I and the second area II of mounting surface 112A.Molding is single Member 140 may include covering the chip protection moulding unit 142 of the first chip 132 and 134 on the first area I and second Extend and have the substrate protective moulding unit 144 of the thickness smaller than chip protection moulding unit 142 on area II.It can expose It is covered on the third connecting elements 128 of the conductive welding disk 114C around moulding unit 140.
In some embodiments, in order to form moulding unit 140, offer can be used with identical as moulding unit 140 The mold in the space of shape.In some other embodiments, being formed has uniform thickness and covers the first area I and the second area II Preliminary moulding unit, later by using laser by preliminary moulding unit from its top surface remove certain thickness so that only existing Preliminary moulding unit recess on second area II reaches certain thickness, to form the moulding unit with shape shown in Fig. 5 C 140。
With reference to Fig. 5 D, electromagnetic shielding film 150 forms and covers the exposure table of the moulding unit 140 on printed circuit board 110 Face.Electromagnetic shielding film 150 can contact the third connecting elements 128 of covering conductive welding disk 114.
In some embodiments, forming electromagnetic shielding film 150 may include covering printed circuit board 110 using mask pattern A part, the part is not around moulding unit 140 and electromagnetic shielding film 150 is formed on, so that electromagnetic shielding film 150 can be made only on the exposed surface of moulding unit 140.In order to form electromagnetic shielding film 150, injection can be used or splash Penetrate technique.In some embodiments, electromagnetic shielding film 150 can have about 5 μm to about 20 μm of thickness, but not limited to this.
With reference to Fig. 5 E, on the second area II, by partly remove electromagnetic shielding film 150 formed opening 150H, and by It is removed by the substrate protective moulding unit 144 of opening 150H exposure from its top surface in partly removal electromagnetic shielding film 150 Thus certain thickness forms step ST and concave surface RS1 on the top surface of substrate protective moulding unit 144, concave surface RS1 is by platform Rank ST is limited.Remaining substrate protective moulding unit 144 can protect the guarantor of the insulation on the second area II after forming concave surface RS1 Sheath 118 is from light, moisture or external impact.
After forming the technique of opening 150H of electromagnetic shielding film 150, it can be consecutively carried out to form step in original place The technique of ST and concave surface RS1.In some embodiments, electromagnetic shielding film 150 can be etched by using laser, and can be with Substrate protective moulding unit 144 is partly removed to the over etching of electromagnetic shielding film 150 by using laser, to be formed Concave surface RS1.In some embodiments, IR laser or green laser can be used as the laser, but embodiment is without being limited thereto.
With reference to Fig. 5 F, some region quilts for being selected from the concave surface RS1 of the substrate protective moulding unit 144 on the second area II Removal, to form multiple connecting hole 144H, connecting hole exposure covers the preliminary second connection structure of multiple conductive welding disk 114B Part 126P.Formed substrate protective moulding unit 144 step ST and concave surface RS1 technique after, can original place continuously Execute the technique for forming multiple connecting hole 144H.
In order to form multiple connecting hole 144H, the one of substrate protective moulding unit 144 can be removed by using laser A little parts.The laser for being used to form multiple connecting hole 144H, which applies technique, can apply work in the laser for being used to form concave surface RS1 It is continuously performed after skill.Although IR laser or green laser can be used as the laser for being used to form multiple connecting hole 144H, But embodiment is without being limited thereto.During the formation of multiple connecting hole 144H, by preliminary the second of multiple connecting hole 144H exposure Connecting elements 126P can by laser part be etched and be deformed, to be left lower connecting elements 126L.
With reference to Fig. 5 G, in the obtained product of Fig. 5 F, the second connecting elements 126 with double-layer structure passes through to be formed The upper connecting elements 126U of connecting elements 126L is formed under penetrating multiple connecting hole 144H and contacting, later via the second connection structure Second chip 136 is mounted on above the second area II by part 126, to manufacture integrated antenna package 100 shown in FIG. 1.
At the position that the second chip 136 is stacked in the vertical direction on the RS1 of concave surface, the second chip 136 can be with substrate Protect the concave surface RS1 of moulding unit 144 vertically spaced.
Integrated antenna package 200 shown in Fig. 2 can be manufactured by using the method for manufacture integrated antenna package, the party Method is described by reference to Fig. 5 A to Fig. 5 G.In some embodiments, in order to manufacture integrated antenna package shown in Fig. 2 200, it, can be with instead of forming opening 150H by partly removing electromagnetic shielding film 150 in the technique of reference Fig. 5 E description The size of the second chip 236 above the second area II to be mounted on by consideration to form opening 250H.Next, can will be by The substrate protective moulding unit 144 for the opening 250H exposure that size determines as described above removes certain thickness from its top surface, from And step ST and concave surface RS2 is formed on the top surface of substrate protective moulding unit 144, concave surface RS2 is limited by step ST.It connects down Come, the technique similar with the technique of Fig. 5 F and Fig. 5 G can be executed, to manufacture integrated antenna package 200 shown in Fig. 2.
Fig. 6 A to Fig. 6 E is each stage in the method shown according to the manufacture integrated antenna package of other embodiments Cross-sectional view.The method that reference Fig. 6 A to Fig. 6 E description is manufactured into integrated antenna package 300 shown in Fig. 3.In Fig. 6 A to Fig. 6 E In, identical component is indicated with appended drawing reference identical in Fig. 1 to Fig. 5 G, will omit descriptions thereof.
With reference to Fig. 6 A, prepare printed circuit board 110 in the method that the method described with reference Fig. 5 A is similar.However, at this Different from example shown in Fig. 5 A to Fig. 5 G in example, printed circuit board 110 does not include be formed in mounting surface 112A first Conductive welding disk 114C and third connecting elements 128 on area I, and including be formed in the inside of substrate body 112 and with installation table The ground electrode 314C of face 112A separation.Next, in the identical method described with reference Fig. 5 B, on printed circuit board 110 Form multiple connecting elements 122 and 126P.
Electromagnetic shielding film 350 (referring to Fig. 6 C) can be connected to ground electrode 314C in subsequent technique.In some implementations In example, at least one ground electrode 314C can be formed on the two sides of printed circuit board 110.In some other embodiments, ground Electrode 314C may include the line pattern extended along the outer edge of the first area I with annular.
Next, forming preliminary moulding unit 140P in the similar method of the method described with reference Fig. 5 C and covering it The the first area I and the second area II of lid mounting surface 112A.It, can be along chain-dotted line L1 and L2 shown in Fig. 6 A in subsequent technique Preliminary moulding unit 140P is cut, is thus separated into being individually encapsulated.In some embodiments, as shown in Figure 6A instead of being formed Preliminary moulding unit 140P, moulding unit 140 shown in Fig. 5 C can be formed.In such a case, it is possible to omit execution point From at the technique being individually encapsulated, which is had been described above.
Fig. 6 B is shown after the products obtained therefrom in Fig. 6 A cut along chain-dotted line L1 and L2, and ground electrode 314C is exposed to print Products obtained therefrom outside the side surface of printed circuit board 110.As shown in Figure 6B, as the institute along chain-dotted line L1 and L2 cutting drawing 6A Product as a result, include chip protection moulding unit 142 and substrate protective moulding unit 144 including moulding unit 140 can To be retained on printed circuit board 110.
It forms electromagnetic shielding film 350 in the similar method of the method described with reference Fig. 5 D with reference to Fig. 6 C and makes its covering The exposed surface of moulding unit 140 on printed circuit board 110.Electromagnetic shielding film 350 may include covering printed circuit board 110 Side surface substrate shield part 352.The side wall of printed circuit board can be completely covered in substrate shield part 352, and can To extend across the rear surface 112B of substrate 112 in z-direction.
With reference to Fig. 6 D, in the similar method of the method described with reference Fig. 5 E and Fig. 5 F, by second area's II upper portion Point ground removal electromagnetic shielding film 350 and form opening 350H, and by thus exposed substrate protective moulding unit 144 from Qi Ding Surface removes certain thickness, to form step ST and concave surface RS1, concave surface on the top surface of substrate protective moulding unit 144 RS1 is limited by step ST.Next, being selected from the concave surface RS1 of the substrate protective moulding unit 144 on the second area II by removal Some regions for selecting form connecting hole 144H, thus the connecting elements 126L under the bottom surface exposure of connecting hole 144H.
With reference to Fig. 6 E, in the similar method of the method described with reference Fig. 5 G, by forming upper connecting elements 126U shape At the second connecting elements 126 with double-layer structure, second chip 136 is mounted on via the second connecting elements 126 later Above two area II, to manufacture integrated antenna package 300 shown in Fig. 3.
Fig. 7 A to Fig. 7 E is each stage in the method shown according to the manufacture integrated antenna package of other embodiment Cross-sectional view.The method that reference Fig. 7 A to Fig. 7 E description is manufactured into integrated antenna package 400 shown in Fig. 4.In Fig. 7 A to figure In 7E, identical component is indicated with appended drawing reference identical in Fig. 1 to Fig. 6 E, will omit descriptions thereof.
With reference to Fig. 7 A, prepare printed circuit board 110 in the method that the method described with reference Fig. 5 A is similar, later with ginseng The similar method of method for examining Fig. 5 B description forms multiple connecting elements 122,126P and 428 on printed circuit board 110.At this Different from example shown in Fig. 5 A to Fig. 5 G in example, printed circuit board 110 does not include in the firstth area of mounting surface 112A Conductive welding disk 114C and third connecting elements 128 in I, but the mounting surface 112A including being exposed to substrate body 112 The connection of the conductive welding disk 414 and covering conductive welding disk 414 outside printed circuit board 110 between first area I and the second area II Component 428.
Conductive welding disk 414 can be with ground electrode, and electromagnetic shielding film 450 (referring to Fig. 7 C) is connected to the ground in subsequent technique Electrode.In some embodiments, a conductive welding disk 414 can be formed on the two sides of the second area II of printed circuit board 110. In some other embodiments, conductive welding disk 414 may include the line extended along the outer edge of the second area II with annular Pattern.
Next, the first chip 132 and 134 is pacified when the preliminary second connecting elements 126P exposure on the second area II On the first area I.First chip 132 and 134 can be connected to multiple conductive welding disk 114A by the first connecting elements 122. When installing the first chip 132 and 134, multiple conductive welding disk 114B and 414 are by preliminary second connecting elements 126P and connection structure Part 428 is protected.Due to can protect multiple conductive welding disk 114B and 414 from vibration, impact, moisture, external contamination etc., so Multiple conductive welding disk 114B and 414 can be prevented to be damaged or deteriorate and reliability can be kept.
It is single to form molding in the similar method of the forming method of moulding unit 140 described with reference Fig. 5 C with reference to Fig. 7 B Member 440 simultaneously makes it cover the first area I and the second area II of mounting surface 112A.However, moulding unit 440 includes covering installation table The chip of the first chip 132 and 134 on the first area I of face 112A is protected moulding unit 442 and is extended on the second area II And the substrate protective moulding unit 444 with the thickness smaller than chip protection film unit, and chip protects moulding unit 442 It is separated from each other with substrate protective moulding unit 444, shielding space 440S is located at chip protection moulding unit 442 and substrate protective Between moulding unit 444, shielding space 440S is between the first area I and the second area II.
In some embodiments, in order to form moulding unit 440, moulding unit 140 (referring to Fig. 5 C) with reference Fig. 5 to retouch The similar method of the method stated is formed on printed circuit board 110, by using laser part removes the first area I and later Moulding unit 140 between two area II protects moulding unit so as to form chip while forming shielding space 440S 442 and substrate protective moulding unit 444, the shielding space 440S make the connecting elements 428 being separated from each other, chip protection mould Unit 442 and substrate protective moulding unit 444 exposure processed, wherein shielding space 440S protects moulding unit 442 and lining in chip It protects between moulding unit 444 at bottom.
Although IR laser or green laser can be used as the laser for being used to form shielding space 440S, embodiment It is without being limited thereto.During forming shielding space 440S, the top of connecting elements 428 can be laser etched.
Electromagnetism is formed with reference to Fig. 7 C in the similar method of the forming method of electromagnetic shielding film 150 described with reference Fig. 5 D Screened film 450 simultaneously makes it cover the exposed surface of the moulding unit 440 on printed circuit board 110.
Electromagnetic shielding film 450 may include side wall shielded segment 454, which protects in chip and mould Extend and connect towards printed circuit board 110 in shielding space 440S between unit 442 and substrate protective moulding unit 444 To connecting elements 428.Side wall shielded segment 454 can be electrically connected by connecting elements 428 with conductive welding disk 414.
With reference to Fig. 7 D, in the method similar with method described in reference Fig. 5 E and Fig. 5 F, by above the second area II The substrate protective moulding unit 444 from its for partly removing electromagnetic shielding film 450 and forming opening 450H, and thus exposing Top surface removes certain thickness, so that step ST4 and concave surface RS4 is formed on the top surface of substrate protective moulding unit 444, it is recessed Face RS4 is limited by step ST4.Next, by being selected from the concave surface RS4 of the substrate protective moulding unit 444 on the second area II The removal of some regions, to form the connecting hole 444H of the lower connecting elements 126L of exposure.
With reference to Fig. 7 E, in the similar method of the method described with reference Fig. 5 G, by forming upper connecting elements 126U shape At the second connecting elements 126 with double-layer structure, second chip 436 is mounted on via the second connecting elements 126 later Above two area II, to manufacture integrated antenna package 400 as shown in Figure 4.
According to manufacture by reference to the side of Fig. 5 A to Fig. 7 E manufacture integrated antenna package 100,200,300 and 400 described Method, (wherein, described first in the SiP module including the first chip 132 and 134 and the second chip 136,236 or 436 Chip requires the electromagnetic shielding provided by electromagnetic shielding film 150,350 or 450, and second chip does not require by electromagnetic shielding film 150,350 or 450 provide electromagnetic shieldings or need to be exposed in light transmission environment), electromagnetic shielding film 150,350 or 450 with The separation distance between the second chip 136,236 or 436 being exposed to outside electromagnetic shielding film 150,350 or 450 can be gone It removes or minimizes, to improve the electromagnetic shielding capability of each encapsulation, and each envelope caused by inhibiting due to separation distance The size of dress increases.In addition, after forming moulding unit 140 or 440 and electromagnetic shielding film 150,350 or 450, by the second core Piece 136,236 or 436 is mounted on 110 top of printed circuit board, and thus the second chip 136,236 or 436 is not exposed to electromagnetic screen In the atmosphere for covering the formation process of film 150,350 or 450 and/or moulding unit 140 or 440.Therefore, the second chip can be removed 136, a possibility that 236 or 436 surface contamination.Particularly, when configuration passes through the exposure table of the second chip 136,236 or 436 When face senses the sensor of external environment (such as light or bio signal), moulding unit 140 or 440 and electromagnetic shielding are being formed Second chip 136,236 or 436 is installed after film 150,350 or 450, as in method according to the embodiment, is thus led to The surface contamination for inhibiting the second chip 136,236 or 436 is crossed, the performance degradation of sensor can be prevented.
Although by reference to Fig. 1 to Fig. 7 E describe integrated antenna package 100,200,300 and 400 according to the embodiment and Its manufacturing method, but embodiment is not limited to example shown in Fig. 1 to Fig. 7 E, can not depart from spirit and scope of the present disclosure In the case of make various changes and modifications.For example, although Fig. 1 to Fig. 7 E be shown in which to constitute integrated antenna package 100,200, 300 or 400 the second chip 136,236 or 436 is arranged in the approximate centre part of electromagnetic shielding film 150,350 or 450 simultaneously And electromagnetic shielding film 150,350 or 450 has the knot for the shape for surrounding the second chip 136,236 or 436 completely in the plan view Structure and its manufacturing method, but embodiment is not limited to above-mentioned example.For example, the second chip 136,236 or 436 can be arranged in electricity The edge of magnetic shield film 150,350 or 450 so that electromagnetic shielding film 150,350 or 450 partly surround the second chip 136, 236 or 436.Although in addition, have been illustrated in electromagnetic shielding film 150,350 or 450 formed opening 150H, a 350H or The example of 450H, but embodiment is not limited to above-mentioned example.For example, can be formed in electromagnetic shielding film 150,350 or 450 more A opening 150H, 350H or 450H, and multiple second chips 136,236 or 436 can with multiple opening 150H, 350H or 450H is correspondingly mounted to above the second area II.In this case, the multiple of 110 top of single printed circuit board are mounted on Second chip 136,236 or 436 can execute identical function, and wherein at least some can execute different functions.
Fig. 8 A and Fig. 8 B are the figures for showing wearable device according to the embodiment.It will match with reference to Fig. 8 A and Fig. 8 B detailed description It is set to the wearable device 500 of body wearable electronic.
With reference to figure gA and Fig. 8 B, wearable device 500 is including main body 510 and for main body 510 to be attached to the attached of user Unit 550.As it is used herein, term " user " can refer to using the people of electronic equipment, animal, plant or equipment, example Such as Artificial Intelligence's electronic equipment.
Such as the various circuit arrangements as application processor (AP), telecommunication circuit, memory devices etc. can be embedded in In main body 510.Display 512 can be arranged in the front surface of main body 510.Integrated antenna package 520 including sensor can To be embedded in main body 510.Integrated antenna package 520 may include sensor module, it may for example comprise bio signal sensing sensing The sensor module of device etc..
Integrated antenna package 520 may include at least one selected from integrated antenna package 100,200,300 and 400 Integrated antenna package and there is the structure being altered or modified from it without departing from the spirit and scope of the disclosure Integrated antenna package.
Window 530 can be formed in the rear surface 514 of main body 510, and the sensing that will include in integrated antenna package 520 Device chip is exposed to the outside of integrated antenna package 520, and sensor chip is mentioned to the outside of integrated antenna package 520 For signal.Window 530 can be blocked by the protective film 532 of the material including transparent to light.It is retouched for example, constituting referring to figs. 1 to Fig. 4 Second chip 136,236 or 436 of the integrated antenna package 100,200,300 or 400 stated can be by protective film 532 to integrated The external of circuit package 100,200,300 or 400 sends information and receives information from its outside.
The sensor chip for constituting integrated antenna package 520 can be installed into the rear surface 514 by main body 510 Window 530, as it can be seen that thus when user dresses wearable device 500, constitutes integrated circuit from the outside of integrated antenna package 520 The sensor chip (for example, second chip 136,236 or 436) of encapsulation 520 can be with user oriented physical feeling.
The sensor chip of integrated antenna package 520 can detecte the information of the health status about user, such as blood pressure, Heart rate variability (HRV), rhythm of the heart (HRM), photo-plethysmographic (PPG), sleep interval, skin temperature, heart rate, blood flow, At least one of blood glucose, oxygen saturation, pulse wave and electrocardiogram (ECG).
Adhesion unit 550 allows main body 510 to be attached to user, such as physical feeling, clothes, collar etc., and can have There are a various structures, such as belt, watchband, chain, buckle, and is not limited to shape shown in Fig. 8 A and 8B.For example, wearable device 500 can be by using adhesion unit 550 by the weared on wrist of user.Wearable device according to the embodiment be not limited to Fig. 8 A and Shape shown in Fig. 8 B, and can be implemented as various communication equipments or Medical Devices.
Fig. 9 is the block diagram of wearable device according to the embodiment.With reference to Fig. 9, wearable device 600 may include controller 610, display 620, power management module 630, sensor module 640, communication module 650 and memory 660.
Processor 610 may include at least one of following: central processing unit (CPU), application processor (AP), mailing address Manage device (CP) and micro controller unit (MCU).For example, controller 610 can control including in wearable device 600 at least Communication and/or data processing between one component or the multiple components of execution.
Display 620 may include panel, hologram device or projector.
Power management module 630 can manage the power supply of wearable device 600.For example, power management module 630 can wrap Include power management integrated circuit (PMIC), charger integrated circuit, battery or fuel quantity ga(u)ge.Communication module 650 can be by having Another electronic equipment (for example, smart phone) of the line/wireless communication outside wearable device 600 and wearable device 600 it Between execute data transmission and reception.
Sensor module 640 can will be measured by the physical quantity or sensing operation state for measuring wearable device 600 Or the information sensed is converted into electric signal.Sensor module 640 may include biosensor, range sensor, temperature biography Sensor or motion sensor.Biosensor can sense various types of biological informations of user, and biological information is sent To the outside of biosensor.Biological information may include pulse frequency, oxygen saturation, calorie consumption, pulse pressure, body temperature, electrocardio Figure, body fat, activity or blood pressure, but embodiment is not limited to above-mentioned example.
Wearable device 600 may include in the integrated antenna package 100,200,300 and 400 referring to figs. 1 to Fig. 4 description At least one, sensor module 640 may include referring to figs. 1 to Fig. 4 description the second chip 136,236 and 436 in extremely It is one few.
Communication module 650 can be communicated with various communication means with the electronic equipment outside wearable device 600.Example Such as, communication means may include long term evolution (LTE), wideband code division multiple access (WCDMA), global system for mobile communications (GSM), nothing Line fidelity (WiFi), bluetooth and near-field communication (NFC).
Memory 660 may include volatibility and or nonvolatile memory.For example, memory 660 can store and electricity At least one relevant order or data in other components of sub- equipment 600.
By summarizing and looking back, one or more embodiments provide a kind of integrated antenna package and including integrated antenna packages Wearable device, the integrated antenna package by minimize SiP module in separation distance, and have can improve electromagnetic screen It covers ability and inhibits due in electromagnetic armouring structure and the separation distance being exposed between the chip outside electromagnetic armouring structure Caused by the increased structure of size, wherein the SiP module includes the core for needing to be electromagnetically shielded by electromagnetic armouring structure Piece and need to be exposed to the chip in light transmission environment.
Since integrated antenna package according to the embodiment and wearable device allow electromagnetic armouring structure and are exposed to electromagnetism Separation distance between chip outside shielding construction minimizes, so integrated antenna package and wearable device can have most The size of smallization simultaneously shows improved electromagnetic shielding capability.
In addition, one or more embodiments provide a kind of method that integrated antenna package is manufactured in manufacture SiP module, The SiP module includes needing the chip being electromagnetically shielded by electromagnetic armouring structure and needing to be exposed to the core in light transmission environment A possibility that piece, this method can minimize the pollution that may cause during manufacturing SiP module, and by easily Control electromagnetic armouring structure and the relative position of chip being exposed to outside electromagnetic armouring structure and they the distance between prevent The only unnecessary increase of the size of integrated antenna package.
It include needing the chip being electromagnetically shielded by electromagnetic armouring structure and needing to be exposed in light transmission environment in manufacture Chip including SiP module in, manufacture integrated antenna package method can will pollution a possibility that minimize the (pollution May cause during manufacturing SiP module), and can be by easily controlling electromagnetic armouring structure and being exposed to electromagnetism The relative position of chip outside shielding construction and they the distance between come prevent integrated antenna package size need not The increase wanted.
Example embodiment has been disclosed herein, and specific term despite the use of, but they are used and only It is explained with generic and descriptive sense, rather than the purpose for limitation.In some cases, those skilled in the art should recognize Arrive, unless expressly stated otherwise, otherwise combine specific embodiment description feature, characteristic and/or element can be used alone or It is combined with feature, characteristic and/or the element for combining other embodiments to describe.Therefore, it will be understood by those skilled in the art that not Under the premise of being detached from the spirit and scope of the present invention as described in appended claims, in form and details each can be carried out Kind changes.

Claims (20)

1. a kind of integrated antenna package, comprising:
Printed circuit board;
First chip is arranged in above the firstth area of the mounting surface of the printed circuit board;
First chip is electrically connected to the printed circuit board by the first connecting elements;
Second chip is arranged in above the secondth area of the mounting surface of the printed circuit board;
Second chip is electrically connected to the printed circuit board by the second connecting elements;
Moulding unit covers the firstth area of the mounting surface of the printed circuit board and surrounds first chip;
Electromagnetic shielding film covers the side surface and upper surface of the moulding unit;And
Wherein, the electromagnetic shielding film is formed directly on the moulding unit.
2. integrated antenna package according to claim 1, wherein it is single that the electromagnetic shielding film fully covers the molding The side surface and upper surface of member.
3. integrated antenna package according to claim 1, wherein the electromagnetic shielding film, which is connected to, to be arranged in the printing The first conductive welding disk in the mounting surface of circuit board, and first conductive welding disk is located at the installation of the printed circuit board The boundary in the secondth area of the mounting surface in the firstth area and printed circuit board on surface.
4. integrated antenna package according to claim 3, wherein first conductive welding disk is ground electrode.
5. integrated antenna package according to claim 1, wherein second chip includes bio signal sensing sensing Device.
6. integrated antenna package according to claim 5, wherein the bio signal sensing sensor is that rhythm of the heart passes Sensor.
7. integrated antenna package according to claim 1, wherein second connecting elements is connected to the printed circuit The second conductive welding disk in the mounting surface of plate.
8. integrated antenna package according to claim 1, wherein the firstth area of the mounting surface of the printed circuit board has There is the ring structure in the secondth area of the mounting surface for surrounding the printed circuit board.
9. integrated antenna package according to claim 1, wherein the moulding unit include substrate protective moulding unit and Chip protects moulding unit, between the substrate protective moulding unit is filled between first chip and the printed circuit board Gap, and chip protection moulding unit covers the side surface and upper surface of first chip.
10. integrated antenna package according to claim 9, wherein the substrate protective moulding unit and the chip are protected Shield moulding unit is connected to each other and is formed as one.
11. a kind of integrated antenna package, comprising:
Printed circuit board;
First chip is arranged in above the firstth area of the mounting surface of the printed circuit board;
First chip is electrically connected to the printed circuit board by the first connecting elements;
Second chip is arranged in above the secondth area of the mounting surface of the printed circuit board;
Second chip is electrically connected to the printed circuit board by the second connecting elements;
Moulding unit covers the firstth area of the mounting surface of the printed circuit board and surrounds first chip;And
Electromagnetic shielding film fully covers the side surface and upper surface of the moulding unit;
Wherein, second chip and the moulding unit and the electromagnetic shielding UF membrane.
12. integrated antenna package according to claim 11, wherein the electromagnetic shielding film, which is connected to, to be arranged in the print The first conductive welding disk in the mounting surface of printed circuit board, first conductive welding disk are arranged on the peace of the printed circuit board Fill the boundary in the secondth area of firstth area on surface and the mounting surface of the printed circuit board.
13. integrated antenna package according to claim 12, wherein first conductive welding disk is ground electrode.
14. integrated antenna package according to claim 11, wherein second chip includes bio signal sensing sensing Device.
15. integrated antenna package according to claim 14, wherein the bio signal sensing sensor is rhythm of the heart Sensor.
16. integrated antenna package according to claim 11, wherein first chip and second chip are mounted In the similar face of the printed circuit board.
17. integrated antenna package according to claim 16, wherein second connecting elements connects second chip The second conductive welding disk being connected in the mounting surface of the printed circuit board, and second conductive welding disk be electrically connected to it is described First connecting elements.
18. integrated antenna package according to claim 11, wherein the firstth area of the mounting surface of the printed circuit board The ring structure in the secondth area with the mounting surface for surrounding the printed circuit board.
19. integrated antenna package according to claim 11, wherein the moulding unit includes substrate protective moulding unit Moulding unit is protected with chip, the substrate protective moulding unit is filled between first chip and the printed circuit board Gap, and chip protection moulding unit covers the side surface and upper surface of first chip.
20. integrated antenna package according to claim 19, wherein the substrate protective moulding unit and the chip are protected Shield moulding unit is connected to each other and is formed as one.
CN201810808732.1A 2016-09-23 2017-06-13 Integrated circuit package, method of manufacturing the same, and wearable device including the same Expired - Fee Related CN108962845B (en)

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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180032985A (en) * 2016-09-23 2018-04-02 삼성전자주식회사 Integrated circuit package and method of manufacturing the same and wearable device including integrated circuit package
WO2018198856A1 (en) * 2017-04-28 2018-11-01 株式会社村田製作所 Circuit module and method for manufacturing same
US20180331049A1 (en) * 2017-05-15 2018-11-15 Novatek Microelectronics Corp. Chip on film package
US11251135B2 (en) 2018-04-02 2022-02-15 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing the same
KR102592329B1 (en) 2018-06-26 2023-10-20 삼성전자주식회사 Fabrication method of semiconductor package
CN115943737A (en) 2018-08-01 2023-04-07 伟创力有限公司 Biosensing integrated garment
US11437322B2 (en) 2018-09-07 2022-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US11177226B2 (en) * 2018-09-19 2021-11-16 Intel Corporation Flexible shield for semiconductor devices
US10910322B2 (en) 2018-12-14 2021-02-02 STATS ChipPAC Pte. Ltd. Shielded semiconductor package with open terminal and methods of making
US10985109B2 (en) * 2018-12-27 2021-04-20 STATS ChipPAC Pte. Ltd. Shielded semiconductor packages with open terminals and methods of making via two-step process
CN109982506A (en) * 2019-03-14 2019-07-05 广东小天才科技有限公司 A kind of wearable device
CN109920779B (en) * 2019-03-19 2020-11-24 吴静雯 Preparation method of electromagnetic shielding layer of packaged product and packaged product
KR102522114B1 (en) * 2019-06-28 2023-04-14 주식회사 아모센스 Electronic device assembly package, circuit board for electronic device module and method of fabricating the same
US11309243B2 (en) * 2019-08-28 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package having different metal densities in different regions and manufacturing method thereof
EP3799539B1 (en) * 2019-09-27 2022-03-16 Siemens Aktiengesellschaft Circuit carrier, package and method for its production
US11662223B2 (en) * 2019-10-24 2023-05-30 Osram Opto Semiconductors Gmbh Optoelectronic device including a shielding cap and methods for operating and fabricating an optoelectronic device
EP3817043A1 (en) * 2019-10-31 2021-05-05 Heraeus Deutschland GmbH & Co KG Electromagnetic interference shielding in recesses of electronic modules
GB2589568A (en) 2019-11-28 2021-06-09 Prevayl Ltd Sensor device, system and wearable article
GB2589567A (en) * 2019-11-28 2021-06-09 Prevayl Ltd Semiconductor package, article and method
WO2021105676A1 (en) * 2019-11-28 2021-06-03 Prevayl Limited Sensor semiconductor package, article comprising the same and manufacturing method thereof
JP6930617B2 (en) * 2020-02-10 2021-09-01 ダイキン工業株式会社 Electrical components and manufacturing method of electrical components
CN111343782B (en) * 2020-04-14 2021-04-27 京东方科技集团股份有限公司 Flexible circuit board assembly, display assembly and display device
CN111710238A (en) * 2020-07-22 2020-09-25 京东方科技集团股份有限公司 Display device and electronic apparatus
CN111816625B (en) * 2020-08-25 2020-12-04 甬矽电子(宁波)股份有限公司 Multilayer chip stacking structure and multilayer chip stacking method
CN112382628B (en) * 2020-11-11 2022-09-20 歌尔微电子有限公司 Digital-analog hybrid packaging structure, electronic equipment and packaging process
DE112021005387T5 (en) * 2020-11-19 2023-07-20 Tdk Corporation MOUNTING PLATE AND CIRCUIT BOARD
US20220346239A1 (en) * 2021-04-23 2022-10-27 Advanced Semiconductor Engineering, Inc. Electronic device and method of manufacturing the same
CN113500839B (en) * 2021-07-16 2023-08-18 京东方科技集团股份有限公司 Chip protection film material, electronic equipment assembling method and electronic equipment
WO2024072042A1 (en) * 2022-09-28 2024-04-04 삼성전자 주식회사 Circuit board module and electronic apparatus including same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1715520A1 (en) * 2005-04-21 2006-10-25 St Microelectronics S.A. Device for protecting an electronic circuit
US20130241039A1 (en) * 2011-05-03 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material
US20160091575A1 (en) * 2014-09-30 2016-03-31 Kabushiki Kaisha Toshiba Magnetic shielded package
WO2016121491A1 (en) * 2015-01-30 2016-08-04 株式会社村田製作所 Electronic circuit module
WO2017047539A1 (en) * 2015-09-14 2017-03-23 株式会社村田製作所 High-frequency module

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828396B2 (en) * 1992-01-31 1996-03-21 株式会社東芝 Semiconductor device
JPH0828396A (en) * 1994-07-13 1996-01-30 Otix:Kk Lead wire of fuel distribution pipe
JP4042340B2 (en) * 2000-05-17 2008-02-06 カシオ計算機株式会社 Information equipment
JP4608777B2 (en) * 2000-12-22 2011-01-12 株式会社村田製作所 Electronic component module
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
JP2006332094A (en) * 2005-05-23 2006-12-07 Seiko Epson Corp Process for producing electronic substrate, process for manufacturing semiconductor device and process for manufacturing electronic apparatus
US20090000815A1 (en) * 2007-06-27 2009-01-01 Rf Micro Devices, Inc. Conformal shielding employing segment buildup
DE102005053765B4 (en) * 2005-11-10 2016-04-14 Epcos Ag MEMS package and method of manufacture
US20080054490A1 (en) * 2006-08-31 2008-03-06 Ati Technologies Inc. Flip-Chip Ball Grid Array Strip and Package
US7659617B2 (en) * 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
TW201032319A (en) * 2009-02-25 2010-09-01 Everlight Electronics Co Ltd Semiconductor optoelectronic device and quad flat non-leaded optoelectronic device
US8093691B1 (en) * 2009-07-14 2012-01-10 Amkor Technology, Inc. System and method for RF shielding of a semiconductor package
US8138062B2 (en) * 2009-12-15 2012-03-20 Freescale Semiconductor, Inc. Electrical coupling of wafer structures
US8624364B2 (en) 2010-02-26 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation connector and method of manufacture thereof
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
TWI448226B (en) * 2010-09-21 2014-08-01 Cyntec Co Ltd Power-converting module
JP5751079B2 (en) 2011-08-05 2015-07-22 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP5327299B2 (en) 2011-09-09 2013-10-30 オムロン株式会社 Semiconductor device and microphone
TWI448224B (en) * 2012-09-24 2014-08-01 Universal Scient Ind Shanghai Electronic module and method for same
KR101311236B1 (en) 2013-04-17 2013-09-25 주식회사 이노폴이 Shield case and its manufacture method
JP5576548B1 (en) * 2013-07-10 2014-08-20 太陽誘電株式会社 Circuit module and manufacturing method thereof
US9144183B2 (en) 2013-07-31 2015-09-22 Universal Scientific Industrial (Shanghai) Co., Ltd. EMI compartment shielding structure and fabricating method thereof
KR101487931B1 (en) * 2013-08-20 2015-02-02 레이트론(주) Photo sensor package for lighting
JP2015072935A (en) * 2013-09-03 2015-04-16 太陽誘電株式会社 Circuit module and method for manufacturing the same
US9520645B2 (en) 2013-09-09 2016-12-13 Apple Inc. Electronic device with electromagnetic shielding structures
JP6074345B2 (en) 2013-09-24 2017-02-01 株式会社東芝 Semiconductor device and manufacturing method thereof
KR101559154B1 (en) 2014-03-14 2015-10-12 (주)파트론 Pressure sensor package and manufacturing method thereof
KR101642560B1 (en) * 2014-05-07 2016-07-25 삼성전기주식회사 Electronic component module and manufacturing method thereof
US9851258B2 (en) 2014-11-04 2017-12-26 Maxim Integrated Products, Inc. Thermopile temperature sensor with a reference sensor therein
US9548273B2 (en) * 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
WO2016144039A1 (en) * 2015-03-06 2016-09-15 Samsung Electronics Co., Ltd. Circuit element package, manufacturing method thereof, and manufacturing apparatus thereof
US9786623B2 (en) * 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US9721903B2 (en) * 2015-12-21 2017-08-01 Apple Inc. Vertical interconnects for self shielded system in package (SiP) modules
JP5988004B1 (en) * 2016-04-12 2016-09-07 Tdk株式会社 Electronic circuit package
KR20180032985A (en) * 2016-09-23 2018-04-02 삼성전자주식회사 Integrated circuit package and method of manufacturing the same and wearable device including integrated circuit package
US20180134546A1 (en) * 2016-11-14 2018-05-17 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1715520A1 (en) * 2005-04-21 2006-10-25 St Microelectronics S.A. Device for protecting an electronic circuit
US20060274517A1 (en) * 2005-04-21 2006-12-07 Stmicroelectronics Sa Electronic circuit protection device
US20130241039A1 (en) * 2011-05-03 2013-09-19 Stats Chippac, Ltd. Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material
US20160091575A1 (en) * 2014-09-30 2016-03-31 Kabushiki Kaisha Toshiba Magnetic shielded package
WO2016121491A1 (en) * 2015-01-30 2016-08-04 株式会社村田製作所 Electronic circuit module
WO2017047539A1 (en) * 2015-09-14 2017-03-23 株式会社村田製作所 High-frequency module

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US20180090449A1 (en) 2018-03-29
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US10204869B2 (en) 2019-02-12
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US9978693B2 (en) 2018-05-22
US20180233458A1 (en) 2018-08-16
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