CN108899301A - 形成导电插塞的方法 - Google Patents

形成导电插塞的方法 Download PDF

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CN108899301A
CN108899301A CN201810635997.6A CN201810635997A CN108899301A CN 108899301 A CN108899301 A CN 108899301A CN 201810635997 A CN201810635997 A CN 201810635997A CN 108899301 A CN108899301 A CN 108899301A
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doped region
contact hole
dopant
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王欢
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Priority to US16/433,250 priority patent/US20190393039A1/en
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Abstract

本发明公开了一种形成导电插塞的方法，包括：提供一衬底，在所述衬底上形成具有第一掺杂类型的第一掺杂区和第二掺杂类型的第二掺杂区，所述第一掺杂区和所述第二掺杂区被介质层覆盖；刻蚀所述介质层以形成具有部分裸露所述第一掺杂区的第一接触孔和部分裸露所述第二掺杂区的第二接触孔；向所述第一接触孔和第二接触孔中注入第一掺杂类型的掺杂剂，增加所述第一掺杂区表面的掺杂浓度。在注入所述掺杂剂后，在所述第一接触孔和所述第二接触孔中填充导电材料以形成导电插塞。本发明降低了接触电阻，且在无需增加掩膜的情况下，通过控制所述第一掺杂剂的掺杂浓度减小其对所述第二掺杂区离子的影响。

Description

形成导电插塞的方法
技术领域
本发明涉及半导体技术领域，更具体地涉及一种形成导电插塞的方法。
背景技术
通常，电路的导通电阻主要受器件本征导通电阻和互连电阻的影响。在器件已经调好，前段工艺已经完成的情况下，器件本征导通电阻的值已经确定，后段互连电阻将影响电路的导通电阻。其中，金属的电阻率极低，可以忽略不计，那么就以接触孔电阻影响最大。
在目前非金属硅化物工艺中，由于不能形成很好的欧姆接触，导致接触孔电阻非常大，特别是P型有源区的接触电阻，而且受到表面掺杂浓度、热处理的影响，接触孔电阻的分布也不均匀。
目前的工艺做法是前段工艺(包括N+/P+注入，RTA热处理)后，进行接触孔光刻、刻蚀，然后直接淀积金属钨，形成前后段工艺互连。
发明内容
有鉴于此，本发明提供一种形成导电插塞的方法，以解决现有技术存在的问题。
本发明提出一种形成导电插塞的方法，包括：提供一衬底，在所述衬底上形成具有第一掺杂类型的第一掺杂区和第二掺杂类型的第二掺杂区，所述第一掺杂区和所述第二掺杂区被介质层覆盖；
刻蚀所述介质层以形成具有部分裸露所述第一掺杂区的第一接触孔和部分裸露所述第二掺杂区的第二接触孔；
通过所述第一接触孔和所述第二接触孔向所述第一掺杂区和所述第二掺杂区注入第一掺杂类型的掺杂剂，以增加所述第一掺杂区表面的掺杂浓度；
在注入所述掺杂剂后，在所述第一接触孔和所述第二接触孔中填充导电材料以形成导电插塞，
其中，在无需增加掩膜的情况下，通过控制所述第一掺杂剂的掺杂浓度减小其对所述第二掺杂区表面离子的影响。
优选地，进一步包括，在所述衬底上分别形成具有第二掺杂类型的第一阱区和具有第一掺杂类型的第二阱区，其中，所述第一掺杂区位于所述第一阱区中，所述第二掺杂区位于所述第二阱区中。
优选地，进一步包括，在填充所述导电材料之后，在所述导电材料表面淀积金属以形成互连线。
优选地，所述导电材料与所述第一掺杂区表面接触形成第一接触电阻，与所述第二掺杂区表面接触形成第二接触电阻。
优选地，通过控制所述第一掺杂类型的掺杂剂的掺杂浓度以使得所述第一接触电阻减小，而所述第二接触电阻基本保持不变。
优选地，所述第一接触电阻减小的幅度大于所述第二接触电阻增加的幅度。
优选地，所述第一掺杂类型的掺杂剂的掺杂浓度越大，所述第一接触电阻越小。
优选地，注入所述第一掺杂类型的掺杂剂掺杂浓度为所述第一掺杂区掺杂浓度的3％-20％。
优选地，注入所述第一掺杂类型的掺杂剂掺杂浓度为所述第二掺杂区掺杂浓度的3％-20％。
优选地，控制所述第一掺杂类型的掺杂剂的能量使注入深度位于所述第一掺杂区表面。
优选地，所述第一掺杂类型的掺杂剂的注入能量为所述第一掺杂区注入能量的80％-100％。
优选地，所述第一掺杂类型的掺杂剂的注入能量为所述第二掺杂区注入能量的80％-100％。
优选地，所述导电材料为钨或铝。
优选地，在填充所述导电材料之前，在所述第一接触孔和所述第二接触孔淀积一层Ti/TiN，以形成所述导电材料和所述第一接触孔和所述第二接触孔的粘结层。
优选地，所述第一掺杂类型为n型或p型的一种，所述第二掺杂类型为n型或p型的另一种。
优选地，所述第一掺杂区为MOS器件的漏源区。
优选地，所述第二掺杂区为MOS器件的漏源区。
本发明提出的形成导电插塞的方法，在形成接触孔之后对漏源区的进行注入，增加接触孔表面的掺杂浓度，使得后续形成的导电插塞和漏源区形成良好的欧姆接触，以降低接触电阻，且注入过程只会影响接触孔那一块的面积，不会影响器件的整体掺杂浓度。另外，因为本发明提出的形成导电插塞的方法直接在两种不同掺杂类型的掺杂区注入同样类型掺杂剂，减少了一到两步光刻工艺，没有增加光刻掩膜等工艺成本，通过控制注入的掺杂浓度，减小了其对与其具有相反掺杂类型的掺杂区的电阻影响。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为本发明形成导电插塞的方法流程图；
图2a-2e为本发明形成导电插塞各个步骤的结构示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“A直接在B上面”或“A在B上面并与之邻接”的表述方式。在本申请中，“A直接位于B中”表示A位于B中，并且A与B直接邻接，而非A位于B中形成的掺杂区中。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本发明公开了一种形成导电插塞的方法，其流程如图1所示，具体包括以下步骤：
步骤S101：提供一衬底，在所述衬底上形成具有第一掺杂类型的第一掺杂区和第二掺杂类型的第二掺杂区，所述第一掺杂区和所述第二掺杂区被介质层覆盖；
步骤S102：刻蚀所述介质层以形成具有部分裸露所述第一掺杂区的第一接触孔和部分裸露所述第二掺杂区的第二接触孔；
步骤S103：通过所述第一接触孔和第二接触孔向所述第一掺杂区和所述第二掺杂区中注入第一掺杂类型的掺杂剂，以增加所述第一掺杂区表面的掺杂浓度；
步骤S104：在注入所述第一掺杂剂后，在所述第一接触孔和所述第二接触孔中填充导电材料以形成导电插塞，
其中，在无需增加掩膜的情况下，通过控制所述第一掺杂剂的掺杂浓度减小其对所述第二掺杂区离子的影响。
图2为本发明形成导电插塞各个步骤的结构示意图，具体结合图2对本发明形成导电插塞的方法进行详细说明。在本实施例中，所述第一掺杂类型选择为P型，所述第二掺杂类型选择为N型，所述导电插塞形成于一包括NMOS和PMOS的半导体器件的漏源区之上。具体地，如图2a所示，所述半导体器件包括衬底101，在所述衬底101中形成的N型第一阱区102和P型第二阱区103，在所述第一阱区102中形成的P型第一掺杂区104，在所述第二阱区103中形成的N型第二掺杂区105，在所述衬底101的上表面形成的场隔离区以及在第一阱区102和第二阱区103表面形成的栅介质层和栅极导体，其中，在本实施例中，所述第一掺杂区104为所述PMOS管的P型漏源区，所述第二掺杂区105为所述NMOS管的N型漏源区。
首先，在所述衬底101的上表面淀积一定厚度的介质层106以完全覆盖所述第一阱区102和第二阱区103。所述介质层可以为二氧化硅。
随后，如图2b所示，刻蚀部分所述介质层106以形成具有部分裸露所述第一掺杂区的第一接触孔107和部分裸露所述第二掺杂区的第二接触孔108，同时也通过刻蚀所述介质层106形成部分裸露所述栅导体的第三接触孔(图中未标记)。其中，后续工艺中，在所述第一接触孔107中填充的导电材料与所述第一掺杂区104表面接触形成第一接触电阻，在所述第二接触孔108中填充的导电材料与所述第二掺杂区105表面接触形成第二接触电阻。
随后，如图2c所示，进行离子注入工艺109，通过所述第一接触孔107和所述第二接触孔108向所述P型漏源区104和N型漏源区105表面注入P型掺杂剂，以提高所述P型漏源区104表面的掺杂浓度，减小所述第一接触电阻，为后续工艺可以形成良好的欧姆接触。需要强调的一点是，工艺中需要控制好注入P型掺杂剂的剂量，以减小其对N型漏源区105离子的影响，也就是减小其对所述第二接触电阻的影响，保证所述第二接触电阻基本保持不变。同时也需控制P型掺杂剂的注入能量使得注入深度位于所述P型漏源区的表面。具体地，所述P型掺杂剂的掺杂浓度越大，所述第一接触电阻越小。控制所述P型掺杂剂的掺杂浓度为P型漏源区和/或N型漏源区掺杂浓度3％-20％，减小其对N型漏源区离子的影响，使得所述第一接触电阻减小的幅度大于所述第二接触电阻增大的幅度。其中，所述P型掺杂剂的掺杂浓度为P型漏源区和/或N型漏源区掺杂浓度的10％为最佳。控制所述P型掺杂剂的注入能量为所述P型漏源区和/或N型漏源区注入能量的80％-100％，其中，所述P型掺杂剂的注入能量为所述P型漏源区和/或N型漏源区注入能量的80％为最佳。在本实施例中，选择所述P型掺杂剂的掺杂浓度为P型漏源区掺杂浓度的10％，约为2e14cm-2，所述掺杂剂可以为硼，注入能量为40Kev。当然，本领域的技术人员也可在不影响N型漏源区接触电阻的情况下，根据P型漏源区接触电阻的要求相应地调整注入能量和剂量。
本发明提出在形成接触孔之后进行离子注入，这样离子注入只会影响接触孔下方那一块的掺杂浓度，不会对器件的整体掺杂浓度造成影响，也不会影响器件的沟道浓度。另外，通过控制离子注入的剂量，在NMOS区域和PMOS区域的漏源区同时注入P型掺杂剂，可以节省一到两层光刻步骤，无需增加掩膜，且通过离子注入之后，对PMOS管的接触电阻有明显改善，对NMOS管的接触电阻影响也较小。
如图2d所示，在完成注入之后，向所述第一至第三接触孔中淀积导电材料，以形成导电插塞110。具体地，首先在所述接触孔中淀积一层Ti/TiN，使得后续的导电材料与接触孔更好的粘附在一起，接着，继续在接触孔中淀积导电材料，通过化学机械抛光(CMP)去除介质层上表面的导电材料，形成导电插塞110。在本实施例中，所述导电材料可以为钨或铝。
随后，如图2e所示，在介质层表面淀积金属铝，通过光刻，刻蚀工艺形成源极，栅极和漏极的连线111。
本发明的第一掺杂类型可以选择N型或P型中的一种，第二掺杂类型选择N型或P型中的另一种。
本发明提出的形成导电插塞的方法，在形成接触孔之后对漏源区的进行注入，增加漏源区表面的掺杂浓度，使得后续形成的导电插塞和漏源区形成良好的欧姆接触，以降低接触电阻，且注入过程只会影响接触孔那一块的面积，不会影响器件的整体掺杂浓度。另外，因为本发明提出的形成导电插塞的方法直接在两种不同掺杂类型的掺杂区注入同样类型掺杂剂，减少了一到两步光刻工艺，没有增加光刻掩膜等工艺成本，通过控制注入的掺杂浓度，减小了其对与其具有相反掺杂类型的掺杂区的电阻影响。
依照本发明实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (17)

1.一种形成导电插塞的方法，包括：
提供一衬底，在所述衬底上形成具有第一掺杂类型的第一掺杂区和第二掺杂类型的第二掺杂区，所述第一掺杂区和所述第二掺杂区被介质层覆盖；
刻蚀所述介质层以形成具有部分裸露所述第一掺杂区的第一接触孔和部分裸露所述第二掺杂区的第二接触孔；
通过所述第一接触孔和所述第二接触孔向所述第一掺杂区和所述第二掺杂区注入第一掺杂类型的掺杂剂，以增加所述第一掺杂区表面的掺杂浓度；
在注入所述掺杂剂后，在所述第一接触孔和所述第二接触孔中填充导电材料以形成导电插塞，
其中，在无需增加掩膜的情况下，通过控制所述第一掺杂剂的掺杂浓度减小其对所述第二掺杂区表面离子的影响。
2.根据权利要求1所述的方法，进一步包括，在所述衬底上分别形成具有第二掺杂类型的第一阱区和具有第一掺杂类型的第二阱区，其中，所述第一掺杂区位于所述第一阱区中，所述第二掺杂区位于所述第二阱区中。
3.根据权利要求1所述的方法，进一步包括，在填充所述导电材料之后，在所述导电材料表面淀积金属以形成互连线。
4.根据权利要求1所述的方法，其中，所述导电材料与所述第一掺杂区表面接触形成第一接触电阻，与所述第二掺杂区表面接触形成第二接触电阻。
5.根据权利要求4所述的方法，其中，通过控制所述第一掺杂类型的掺杂剂的掺杂浓度以使得所述第一接触电阻减小，而所述第二接触电阻基本保持不变。
6.根据权利要求5所述的方法，其中，所述第一接触电阻减小的幅度大于所述第二接触电阻增加的幅度。
7.根据权利要求5所述的方法，所述第一掺杂类型的掺杂剂的掺杂浓度越大，所述第一接触电阻越小。
8.根据权利要求7所述的方法，其中，注入所述第一掺杂类型的掺杂剂掺杂浓度为所述第一掺杂区掺杂浓度的3％-20％。
9.根据权利要求7所述的方法，其中，注入所述第一掺杂类型的掺杂剂掺杂浓度为所述第二掺杂区掺杂浓度的3％-20％。
10.根据权利要求1所述的方法，其中，控制所述第一掺杂类型的掺杂剂的能量使注入深度位于所述第一掺杂区表面。
11.根据权利要求10所述的方法，其中，所述第一掺杂类型的掺杂剂的注入能量为所述第一掺杂区注入能量的80％-100％。
12.根据权利要求10所述的方法，其中，所述第一掺杂类型的掺杂剂的注入能量为所述第二掺杂区注入能量的80％-100％。
13.根据权利要求1所述的方法，其中，所述导电材料为钨或铝。
14.根据权利要求1所述的方法，其中，在填充所述导电材料之前，在所述第一接触孔和所述第二接触孔淀积一层Ti/TiN，以形成所述导电材料和所述第一接触孔和所述第二接触孔的粘结层。
15.根据权利要求1所述的方法，所述第一掺杂类型为n型或p型的一种，所述第二掺杂类型为n型或p型的另一种。
16.根据权利要求1所述的方法，其中，所述第一掺杂区为MOS器件的漏源区。
17.根据权利要求1所述的方法，其中，所述第二掺杂区为MOS器件的漏源区。
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