CN108878292A - 缩减finfet短沟道栅极高度的方法 - Google Patents

缩减finfet短沟道栅极高度的方法 Download PDF

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CN108878292A
CN108878292A CN201810442557.9A CN201810442557A CN108878292A CN 108878292 A CN108878292 A CN 108878292A CN 201810442557 A CN201810442557 A CN 201810442557A CN 108878292 A CN108878292 A CN 108878292A
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CN108878292B (zh
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窦新元
余鸿
胡振宇
张兴
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GlobalFoundries US Inc
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Abstract

本发明涉及缩减FINFET短沟道栅极高度的方法，所提供的是使FinFET装置上的SC GH缩减同时保护LC装置的方法及所产生的装置。具体实施例包括在FinFET装置的衬底上方形成ILD，该ILD具有SC区与LC区；分别在该SC区与LC区内形成SC栅极与LC栅极，该SC及LC栅极的上表面与该ILD的上表面实质共面；在该LC区上方形成光刻堆栈；使该SC栅极凹陷；将该光刻堆栈剥除；在该SC区与LC区上方形成SiN覆盖层；在该SiN覆盖层上方形成TEOS层；以及平坦化该TEOS层。

Description

缩减FINFET短沟道栅极高度的方法
技术领域
本发明是关于形成鳍式场效应晶体管(FinFET)装置的方法。本发明尤其适用于14纳米(nm)及更先进的技术节点。
背景技术
用于在14nm FinFET装置上形成短沟道(SC)与长沟道(LC)装置的习知程序会使两装置在金属栅极化学机械研磨(CMP)后有28nm的栅极高度(GH)。在SC鳍片顶端功函数(WF)金属与栅极表面之间产生的裕度例如为14nm至15nm，比LC装置的裕度大更多。期望的是能够缩减SC GH或缩小裕度以降低装置的有效电容(Ceff)，并因此改善装置的环式振荡器(RO)效能。然而，FinFET装置上的LC装置在被进一步研磨蚀，无法避免的会有因长与宽栅极区上极为有限的LC裕度以及常见的CMP凹陷问题而使LC鳍片顶端WF金属曝露的风险。
因此，需要能够使FinFET装置上的SC GH缩减但不使LC装置的鳍片曝露的方法、以及所产生的装置。
发明内容
本发明的一态样为使FinFET装置上SC GH缩减同时保护LC装置的程序。
本发明的另一态样是一种FinFET装置，其具有比LC GH更低的SC GH。
本发明的再一态样是一种FinFET装置，其具有比LC GH与区域更低的SC GH与区域。
本发明的附加态样及其它特征将会在以下说明中提出，并且对于审查以下内容的所属技术领域中具有通常知识者部分将会显而易见，或可经由实践本发明来学习。可如随附权利要求书中特别指出的内容来实现并且获得本发明的优点。
根据本发明，可通过一种方法来部分达成一些技术功效，该方法包括：在FinFET装置的衬底上方形成层间介电质(ILD)，该ILD具有SC区与LC区；分别在该SC区与LC区内形成SC栅极与LC栅极，该SC及LC栅极的上表面与该ILD的上表面实质共面；在该LC区上方形成光刻堆栈；使该SC栅极凹陷；将该光刻堆栈剥除；在该SC区与LC区上方形成氮化硅(SiN)覆盖层；在该SiN覆盖层上方形成四乙氧基硅烷(tetraethyl orthosilicate；TEOS)层；以及平坦化该TEOS层。
本发明的态样包括形成高密度等离子(high density plasma；简称HDP)氧化物与低k间隔物的该ILD。其它态样包括通过下列步骤形成该SC栅极与LC栅极：分别在该ILD的该SC区与LC区中形成SC沟槽与LC沟槽向下至硅(Si)鳍；在该SC沟槽与LC沟槽中及该SC区与LC区上方形成保形介电层；在该介电层上方形成保形WF金属层；在该WF金属层上方形成保形阻障金属层；在该阻障金属层上方形成钨(W)层；以及使该W、阻障金属、WF金属、及介电层向下平坦化至该ILD。进一步态样包括通过下列步骤形成该光刻堆栈：在该LC区上方形成旋涂硬罩(SOH)层；在该SOH层上方形成氮氧化硅(SION)层；在该SiON层上方形成埋置型抗反射涂(BARC)层；以及在该BARC层上方形成光阻层。另一态样包括通过下列步骤使该SC栅极凹陷：以干蚀刻剂将该SC栅极选择性蚀刻到8nm至10nm的深度，形成凹穴。附加态样包括在该凹穴的侧表面与底端表面上形成该SiN覆盖层。其它态样包括包含使该ILD的SC区与该SC栅极凹陷时同时凹陷。进一步态样包括通过下列步骤使ILD的该SC区凹陷：以干蚀刻剂将该SC区蚀刻到8nm至10nm的深度。另一态样包括在该光刻堆栈的该剥除之后以及在该SiN覆盖层的该形成之前，平坦化介于该已凹陷SC区与该LC区之间的该ILD。附加态样包括在该剥除之后以及在该SiN覆盖层的该形成之前，清理该SC区与LC区。其它态样包括将该SiN覆盖层形成到至的厚度。
本发明的另一态样是一种装置，其包括：ILD；SC栅极与LC栅极，位在该ILD内，该SC栅极的上表面低于该LC栅极与ILD的上表面；SiN覆盖层，其位在该SC栅极与LC栅极及ILD上方，并且沿着该SC栅极上面该ILD的侧壁；以及平面型TEOS层，位在该SiN覆盖层上方。
该装置的态样包括该SC栅极的该上表面为8nm至10nm，比该LC栅极与ILD的该上表面更低。其它态样包括该SiN覆盖层具有至的厚度。进一步态样包括该ILD为HDP氧化物与低k间隔物。
本装置的再一态样为一种装置，其包括：具有SC区与LC区的ILD；分别位在该SC区与LC区内的SC栅极与LC栅极，该ILD的该SC栅极与SC区的上表面低于该ILD的该LC栅极与LC区的上表面；SiN覆盖层，其位在该SC栅极与LC栅极及ILD上方，并且沿着介于该SC区与LC区之间的该ILD的侧壁；以及位在该SiN覆盖层上方的平面型TEOS层。
该装置的态样包括该ILD的该SC栅极与SC区的该上表面比该ILD的该LC栅极与LC区的该上表面低8nm至10nm。其它态样包括介于该SC区与LC区之间的该ILD的一部分具有平滑的边缘。进一步态样包括该SiN覆盖层具有至的厚度。另一态样包括该ILD为HDP氧化物与低k间隔物。
本发明的附加态样及技术功效经由以下详细说明对于所属技术领域中具有通常知识者将会轻易地变为显而易见，其中本发明的具体实施例单纯地通过经深思用以实行本发明的最佳模式的说明来描述。如将会了解的是，本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改，全都不会脱离本发明。因此，图式及说明本质上要视为说明性，而不是作为限制。
附图说明
本发明是在随附图式的附图中举例来说明，但非作为限制性，图中相同的参考附图标记是指类似的组件，并且其中：
图1至6根据一例示性具体实施例，示意性绘示用于形成FinFET装置的程序流程的截面图，该FinFET装置具有低于LC GH的SC GH；以及
图7至13根据一例示性具体实施例，示意性绘示用于形成FinFET装置的程序流程的截面图，该FinFET装置具有低于LC GH与区域的SC GH与区域。
具体实施方式
在底下的说明中，为了解释，提出许多特定细节以便透彻理解例示性具体实施例。然而，应显而易知的是，没有这些特定细节或利用均等配置也可实践例示性具体实施例。在其它实例中，众所周知的结构及装置是以方块图形式来展示，为的是要避免不必要地混淆例示性具体实施例。另外，除非另有所指，本说明书及权利要求书中用来表达成分、反应条件等等的量、比率、及数值特性的所有数字都要了解为在所有实例中是以「约」一语来修饰。
本发明因应并解决目前在14nm及更先进的FinFET装置上形成SC与LC两装置时，在SC鳍尖与栅极表面之间裕度过大的问题。此问题特别是通过形成所具SC GH低于LC GH或所具SC GH与区域低于LC GH与区域的FinFET装置来解决。
根据本发明的具体实施例的方法包括在FinFET装置的衬底上方形成ILD，该ILD具有SC区与LC区。分别在该SC区与LC区内形成SC栅极与LC栅极，该SC及LC栅极的上表面与该ILD的上表面实质共面。在该LC区上方形成光刻堆栈，使该SC栅极凹陷，然后将该光刻堆栈剥除。在该SC区与LC区上方形成SiN覆盖层。在该SiN覆盖层上方形成TEOS层，然后平坦化该TEOS层。
单纯地通过所思及的最佳模式的描述，对于所属技术领域中具有通常知识者而言，经由下文的详细说明，其它的态样、特征、以及技术功效将变得显而易知，其中图示以及说明的是较佳具体实施例。本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改。因此，图式及说明本质上要视为说明性，而不是作为限制性。
图1至6根据一例示性具体实施例，示意性绘示用于形成FinFET装置的程序流程的截面图，该FinFET装置具有低于LC GH的SC GH。请看图1，由例如HDP氧化物与低k间隔物(为便于说明而未展示)的ILD 101是在FinFET装置的衬底(为便于说明而未展示)上方形成。ILD 101具有SC区103与LC区105，如矩形107所表示。随后，分别在SC区103与LC区105中形成SC栅极109与LC栅极111。举例来说，通过分别在SC区103与LC区105中穿过ILD 101将SC沟槽与LC沟槽(两者为便于说明而未展示)向下形成至Si鳍(为便于说明而未展示)，可分别形成SC栅极与LC栅极109与111。接着，分别在SC沟槽与LC沟槽中且在SC区与LC区103与105上方形成例如二氧化铪(HfO2)与氧化铪的保形介电层113。其次，在介电层113上方形成例如氮化钛(TiN)与碳化钛(TiC)的保形WF金属层115。接着，在WF金属层115上方形成例如TiN的保形阻障金属层117。之后，分别在阻障金属层115与W、阻障金属、WF金属、及介电层119、117、115与113上方形成W层119，然后，例如通过CMP使其向下平坦化至ILD101，如图2所示。于此阶段，SC栅极109与LC栅极111的上表面实质共面，并且具有例如28nm的GH。SC栅极与LC栅极109与111的GH分别实质共面，而不是绝对共面，因为W、阻障金属、WF金属及介电层119、117、115与113的平坦化共同地分别使装置的长与宽栅极区凹陷至例如6nm至9nm的深度，如以上所述。
请看图3，在LC区105上方形成光刻堆栈301。可形成例如SOH层303、SION层305、BARC层307及光阻层309的光刻堆栈301。接着，以例如三氟化氮(NF3)与氯(Cl2)或氟化气体的干蚀刻剂将SC栅极109选择性蚀刻至例如8nm至10nm的深度，形成凹穴401，如图4所示。
接下来，将光刻堆栈301剥除，然后举例来说，使用灰化程序、倾斜灰化(bevelash)、及稀硫酸/过氧化氢(DSP)程序，分别清理SC区与LC区103与105(为便于说明而未展示)，如图5所示。请看图6，分别在凹穴401的侧表面与底端表面上及SC区与LC区103与105上方形成SiN覆盖层601至例如至的厚度。接着，在SiN覆盖层601上方形成TEOS层603并例如通过CMP而将其平坦化。所以，通过使SC栅极109的GH缩减例如8nm至10nm，使SC栅极109的效能灵敏度增大且有效电容降低，藉以改善SC装置RO效能。
图7至13根据一例示性具体实施例，示意性绘示用于形成FinFET装置的程序流程的截面图，该FinFET装置具有低于LC GH与区域的SC GH与区域。图7至9的步骤等同于图1至3的步骤。请看图10，在LC区105上方形成图3的光刻堆栈301之后，以例如NF3与Cl2或氟化气体的干蚀刻剂将SC栅极109与SC区103两者同时蚀刻至例如8nm至10nm的深度。接着，将光刻堆栈301剥除，并且举例来说，使用灰化程序、倾斜灰化、及DSP程序，分别清理SC区与LC区103与105(为便于说明而未展示)，如图11所示。
请看图12，例如通过次要的CMP使介于已凹陷的SC区103与LC区105之间的ILD 101的一部分平坦化，以分别使介于已凹陷的SC区103与LC区105之间的ILD 101的边缘平滑。类似于图7，分别在SC区与LC区103与105上方形成SiN覆盖层1301至例如至的厚度，并且在SiN覆盖层1301上方形成TEOS层1303，然后例如通过CMP将其平坦化。再次地，通过使SC栅极109的GH缩减例如8nm至10nm，使SC栅极109的效能灵敏度增大且有效电容降低，藉以改善SC装置RO效能。
本发明的具体实施例可达到数种技术功效，包括增加SC栅极的效应灵敏度及降低有效电容，藉以改善SC装置RO效能，但不会有使LC鳍片顶端WF金属曝露的风险。举例而言，本发明的具体实施例在各种工业应用中享有实用性，如：微处理器、智能型手机、移动电话、蜂巢式手机、机顶盒、DVD录像机与播放器、汽车导航、打印机与外围装置、网络链接与电信设备、游戏系统、以及数字相机。因此，本发明在各种类型的高度整合型半导体装置的任一者中享有产业利用性，包括具有SC装置与LC装置的14nm及更先进的FinFET装置。
在前述说明中，本发明是参照其具体例示性具体实施例作说明。然而，明显的是，可对其实施各种修改和变更而不脱离本发明较广的精神与范畴，如权利要求书所提者。本说明书及图式从而要视为说明性而非作为限制性。据了解，本发明能够使用各种其它组合及具体实施例，并且如本文中所表达，能够在本发明概念的范畴内作任何变更或修改。

Claims (20)

1.一种方法，包含：
在鳍式场效应晶体管(FinFET)装置的衬底上方形成层间介电质(ILD)，该ILD具有短沟道(SC)区及长沟道(LC)区；
分别在该SC区与LC区内形成SC栅极与LC栅极，该SC栅极及LC栅极的上表面与该ILD的上表面实质共面；
在该LC区上方形成光刻堆栈；
使该SC栅极凹陷；
将该光刻堆栈剥除；
在该SC区与LC区上方形成氮化硅(SiN)覆盖层；
在该SiN覆盖层上方形成四乙氧基硅烷(TEOS)层；以及
平坦化该TEOS层。
2.如权利要求1所述的方法，包含形成高密度等离子(HDP)氧化物与低k间隔物的该ILD。
3.如权利要求1所述的方法，包含通过下列步骤形成该SC栅极与LC栅极：
分别在该ILD的该SC区与LC区中形成SC沟槽与LC沟槽向下至硅(Si)鳍；
在该SC沟槽与LC沟槽中及该SC区与LC区上方形成保形介电层；
在该介电层上方形成保形功函数(WF)金属层；
在该WF金属层上方形成保形阻障金属层；
在该阻障金属层上方形成钨(W)层；以及
使该W、阻障金属、WF金属、及介电层向下平坦化至该ILD。
4.如权利要求1所述的方法，包含通过下列步骤形成该光刻堆栈：
在该LC区上方形成旋涂硬罩(SOH)层；
在该SOH层上方形成氮氧化硅(SION)层；
在该SiON层上方形成埋置型抗反射涂(BARC)层；以及
在该BARC层上方形成光阻层。
5.如权利要求1所述的方法，包含通过下列步骤使该SC栅极凹陷：
以干蚀刻剂将该SC栅极选择性蚀刻到8纳米(nm)至10nm的深度，形成凹穴。
6.如权利要求5所述的方法，包含在该凹穴的侧表面与底端表面上形成该SiN覆盖层。
7.如权利要求1所述的方法，更包含使该ILD的SC区与该SC栅极凹陷时同时凹陷。
8.如权利要求7所述的方法，包含通过下列步骤使ILD的该SC区凹陷：
以干蚀刻剂将该SC区蚀刻到8nm至10nm的深度。
9.如权利要求7所述的方法，包含在该光刻堆栈的该剥除之后且在该SiN覆盖层的该形成之前，平坦化介于该已凹陷SC区与该LC区之间的该ILD。
10.如权利要求1所述的方法，更包含在该剥除之后以及在该SiN覆盖层的该形成之前，清理该SC区与LC区。
11.如权利要求1所述的方法，包含将该SiN覆盖层形成到 至的厚度。
12.一种装置，包含：
层间介电质(ILD)；
短沟道(SC)栅极与长沟道(LC)栅极，位在该ILD内，该SC栅极的上表面低于该LC栅极与ILD的上表面；
氮化硅(SiN)覆盖层，位在该SC栅极与LC栅极及ILD上方，并且沿着该SC栅极之上的该ILD的侧壁；以及
平面型四乙氧基硅烷(TEOS)层，位在该SiN覆盖层上方。
13.如权利要求12所述的装置，其中，该SC栅极的该上表面为8纳米(nm)至10nm，比该LC栅极与ILD的该上表面更低。
14.如权利要求12所述的装置，其中，该SiN覆盖层包含至的厚度。
15.如权利要求12所述的装置，其中，该ILD包含高密度等离子(HDP)氧化物及低k间隔物。
16.一种装置，包含：
层间介电质(ILD)，具有短沟道(SC)区及长沟道(LC)区；
SC栅极与LC栅极，分别位在该SC区与LC区内，该ILD的该SC栅极与SC区的上表面低于该ILD的该LC栅极与LC区的上表面；
氮化硅(SiN)覆盖层，位在该SC栅极与LC栅极及ILD上方，并且沿着介于该SC区与LC区之间的该ILD的侧壁；以及
平面型四乙氧基硅烷(TEOS)层，位在该SiN覆盖层上方。
17.如权利要求16所述的装置，其中，该ILD的该SC栅极与SC区的该上表面为8纳米(nm)至10nm，比该ILD的该LC栅极与LC区的该上表面更低。
18.如权利要求16所述的装置，其中，介于该SC区与LC区之间的该ILD的一部分包含平滑的边缘。
19.如权利要求16所述的装置，其中，该SiN覆盖层包含至的厚度。
20.如权利要求16所述的装置，其中，该ILD包含高密度等离子(HDP)氧化物及低k间隔物。
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