TW201807781A - 具有等效ｎｆｅｔ／ｐｆｅｔ間隔物寛度之差動ｓｇ／ｅｇ間隔物整合及在ｆｄｓｏｉ上致能高壓ｅｇ裝置之雙凸起源極汲極磊晶矽與三重氮化物間隔物整合 - Google Patents

具有等效ｎｆｅｔ／ｐｆｅｔ間隔物寛度之差動ｓｇ／ｅｇ間隔物整合及在ｆｄｓｏｉ上致能高壓ｅｇ裝置之雙凸起源極汲極磊晶矽與三重氮化物間隔物整合 Download PDF

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TW201807781A
TW201807781A TW106103802A TW106103802A TW201807781A TW 201807781 A TW201807781 A TW 201807781A TW 106103802 A TW106103802 A TW 106103802A TW 106103802 A TW106103802 A TW 106103802A TW 201807781 A TW201807781 A TW 201807781A
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pfet
nfet
gate
structures
layer
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喬治 羅伯特 姆芬格
萊恩 史波爾
瑞克Ｊ 卡特
彼特 巴爾斯
漢斯 朱葛爾 史
詹 候尼史奇爾
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格羅方德半導體公司
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Abstract

所提供的是一種就SG與EG結構以相異寬度形成匹配之PFET/NFET間隔物之方法、及一種就SG NFET與SG PFET結構及PFET/NFET EG結構形成相異寬度氮化物間隔物之方法、以及其各別產生之裝置。具體實施例包括提供PFET SG與EG結構及NFET SG與EG結構；在基材上方形成第一氮化物層；形成氧化物襯墊；在PFET及NFET EG結構之側壁上形成第二氮化物層；移除第一氮化物層及氧化物襯墊在PFET SG與EG結構上方之水平部分；在各PFET SG與EG結構之對立側上形成RSD結構；移除第一氮化物層及氧化物襯墊在NFET SG與EG結構上方之水平部分；以及在各NFET SG與EG結構之對立側上形成RSD 結構。

Description

具有等效NFET/PFET間隔物寛度之差動SG/EG間隔物整合及在FDSOI上致能高壓EG裝置之雙凸起源極汲極磊晶矽與三重氮化物間隔物整合
本揭露係關於p型場效電晶體(PFET)及n型場效電晶體(NFET)核心裝置(SG)與I/O裝置(EG)間隔物整合。本揭露尤其是，適用於全空乏絕緣體上矽(FDSOI)裝置及/或需要隆起源極/汲極(RSD)磊晶之任何技術。
EG裝置需要更厚的間隔物才能通過標準可靠度要求。不過，SG裝置上希望薄間隔物以維持標準效能準則。典型的雙RSD整合憑靠添加之NFET/PFET間隔物以阻絕不希望的磊晶(epi)生長。然而，具有更厚間隔物之裝置通常影響到效能。具體而言，高RSD/閘極電容使Fmax降低。已知的方法涉及使用多重間隔物材料來強制RSD磊晶刻面；在所有裝置上使用更厚的間隔物而犧牲SG效能； 或添加另兩個間隔物、遮罩層、及磊晶步驟以支撐NFET及PFET EG裝置。另一種已知方法涉及形成氮化物/氧化物間隔物合夾，其由於使用例如多重磊晶預清潔之數個氧化物消耗步驟而難以控制。
因此，需要能以匹配之NFET/PFET間隔物寬度使SG效能與EG可靠度達到平衡的方法、能在FDSOI上以不同間隔物厚度形成SG NFET、SG PGET、及EG NFET與PFET裝置的方法、以及其產生之裝置。
本揭露之一態樣是一種就SG與EG閘極結構以相異寬度形成匹配之PFET/NFET間隔物之程序。
本揭露之另一態樣是一種就該等SG與EG閘極結構以相異寬度包括匹配之PFET/NFET間隔物之裝置。
本揭露之再一態樣是一種分別就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構形成相異寬度氮化物間隔物之程序。
本揭露之一附加態樣是一種就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構具有各別氮化物間隔物寬度之FDSOI高k金屬閘極(HKMG)裝置。
本揭露之附加態樣及其它特徵將會在以下說明中提出，並且對於審查以下內容之所屬技術領域中具有通常知識者部分將會顯而易見，或可經由實踐本揭露來 學習。可如隨附申請專利範圍中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露，可藉由一種方法來達到一些技術功效，該方法包括：在基材上提供PFET SG與EG閘極結構及NFET SG與EG閘極結構，該等PFET及NFET結構側向隔開；在該基材上方形成第一保形氮化物層；在該基材上方形成氧化物襯墊；在該等PFET及NFET EG閘極結構之側壁上形成第二保形氮化物層；移除該第一氮化物層及該氧化物襯墊在該等PFET SG與EG閘極結構及基材上方之水平部分；在各該PFET SG與EG閘極結構之對立側上形成RSD結構；移除該第一氮化物層及該氧化物襯墊在該等NFET SG與EG閘極結構及基材上方之水平部分；以及在各該NFET SG與EG閘極結構之對立側上形成RSD結構。
本揭露之態樣包括在該等PFET及NFET EG閘極結構之該等側壁上形成第二保形氮化物層係藉由下列步驟：在該基材上方形成該第二保形氮化物層；將該第二保形氮化物層向下平坦化至該氧化物襯墊；在該等PFET及NFET EG閘極結構上方形成光阻層；將該第二保形氮化物層從該等PFET及NFET SG閘極結構移除，以及移除該光阻層。其它態樣包括移除該第一氮化物層及該氧化物襯墊在該等PFET SG與EG閘極結構及基材上方之該等水平部分係藉由下列步驟：在該基材上方形成硬罩層；在該等NFET SG與EG閘極結構上方形成光阻層；移除該等PFET SG與EG閘極結構上方之該硬罩層；將該第一保形氮化物層及該氧化物襯墊向下蝕刻至該基材；以及移除該光阻層。進一步態樣包括該蝕刻形成位在各該PFET SG與EG閘極結構之對立側上之L形第一保形氮化物層間隔物、及位在該PFET EG閘極結構之對立側上之L形氧化物襯墊間隔物。附加態樣包括移除該第一氮化物層及該氧化物襯墊在該等NFE SG與EG閘極結構及基材上方之該等水平部分係藉由下列步驟：在該基材上方形成硬罩層；在該等PFET SG與EG閘極結構上方形成光阻層；移除該等NFET SG與EG閘極結構上方之該硬罩層；將該第一保形氮化物層及該氧化物襯墊向下蝕刻至該基材；移除該光阻層；以及移除該等PFET SG與EG閘極結構上方之該硬罩層。另一態樣包括該蝕刻形成位在各該NFET SG與EG閘極結構之對立側上之L形第一保形氮化物層間隔物、及位在該NFET EG閘極結構之對立側上之L形氧化物襯墊間隔物。其它態樣包括各該PFET及NFET SG閘極結構之該等對立側上所形成之該等RSD結構係受到刻面。
本揭露之另一態樣是一種裝置，其包括：基材上所形成之PFET SG與EG閘極結構及NFET SG與EG閘極結構，該等PFET與NFET結構側向隔開；該基材上且相鄰於各該PFET及NFET SG與EG閘極結構之側壁所形成之一對L形氮化物間隔物；該等PFET及NFET EG閘極結構之各L形氮化物間隔物上且與之相鄰所形成之L形氧化物間隔物；各L形氧化物間隔物上且與之相鄰所形成之 氮化物間隔物；各該PFET及NFET SG閘極結構之對立側上所形成之刻面RSD結構；以及各該PFET及NFET EG閘極結構之對立側上所形成之RSD結構。該裝置之態樣包括各L形氮化物間隔物及各氮化物間隔物乃由矽氧碳氮化物(SiOCN)、高溫iRadTM氮化物、或矽硼碳氮化物(SiBCN)所構成。
本揭露之再一態樣乃是一種方法，其包括：在FDSOI基材上提供NFET SG與EG閘極結構及PFET SG與EG閘極結構，該等SG與EG結構側向隔開，並且各包括閘極及閘極覆蓋層；在該等NFET及PFET SG與EG閘極結構及該基材上方形成保形第一氮化物層；在該等NFET及PFET SG與EG閘極結構及基材上方形成氧化物襯墊；在該等NFET及PFET SG與EG結構及基材上方形成第二保形氮化物層；移除該第二氮化物層之水平部分；遮罩該等NFET及PFET EG閘極結構；移除該第二氮化物層相鄰於該等NFET及PFET SG結構及已曝露氮化物襯墊之垂直部分；遮罩NFET或PFET EG與SG閘極結構；移除該第一氮化物層之水平部分；分別在該基材上相鄰於該等PFET或NFET SG與EG結構形成RSD結構；在該整個基材上方形成第三氮化物層；分別遮罩PFET或NFET SG與EG閘極結構；移除該第三氮化物層之水平部分；分別在該等PFET或NFET SG與EG閘極結構之對立側上形成RSD結構；以及將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋 層、及該氧化物襯墊向下移除至該閘極之上表面。
本揭露之態樣包括在形成該氧化物襯墊之後遮罩該等NFET及PFET SG結構；從該等NFET及PFET EG閘極結構移除該氧化物襯墊；以及移除該遮罩。其它態樣包括移除該第二氮化物層之該等水平部分係藉由下列步驟：將該第二氮化物層向下蝕刻至該氧化物襯墊。進一步態樣包括在遮罩該等NFET及PFET SG與EG閘極結構前，先移除該等NFET及PFET EG閘極結構之該遮罩。附加態樣包括在形成相鄰於該等PFET或NFET SG與EG結構之該等RSD結構前，先移除該等NFET及PFET SG與EG閘極結構之該遮罩。另一態樣包括在將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋層、及該氧化物襯墊向下移除至該閘極之上表面前，先移除該等PFET或NFET SG與EG閘極結構之該遮罩。其它態樣包括將該第三氮化物層從該等NFET或PFET EG與SG閘極結構之該等對立側上之該等RSD結構上方移除；以及將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋層、及該氧化物襯墊向下移除至該閘極之上表面後，進行間隔物氮化物沉積、蝕刻、及矽化。
本揭露之另一態樣是一種裝置，其包括：FDSOI基材；該FDSOI基材上所形成之PFET SG與EG閘極結構及NFET SG與EG閘極結構，該等SG與EG結構側向隔開；該等NFET及PFET SG閘極結構之各側壁上所形 成之雙氮化物層間隔物；該等NFET及PFET EG閘極結構之各側壁上所形成之三重氮化物層間隔物；以及該等NFET及PFET SG與EG閘極結構之對立側上所形成之RSD結構。該裝置之態樣包括該雙氮化物層間隔物比該三重氮化物層間隔物更薄。其它態樣包括該PFET SG閘極結構是在矽鍺(SiGe)層上方形成，而該等PFET EG及NFET SG與EG結構是在矽層上方形成。進一步態樣包括氧化物層是在該等NFET及PFET EG結構之第一及第二氮化物層之間形成。
本揭露之附加態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變為顯而易見，其中本揭露之具體實施例單純地藉由經深思用以實行本揭露之最佳模式的說明來描述。如將會瞭解的是，本揭露能夠是其它及不同的具體實施例，而且其數項細節能夠在各種明顯方面進行修改，全都不會脫離本揭露。因此，圖式及說明本質上要視為說明性，而不是作為限制性。
101‧‧‧PFET SG閘極結構
103‧‧‧PFET EG閘極結構
105‧‧‧NFET SG閘極結構
107‧‧‧NFET EG閘極結構
109‧‧‧基材
110‧‧‧閘極蓋體
111‧‧‧氮化物層
111’‧‧‧L形間隔物、氮化物間隔物
113‧‧‧氧化物襯墊
113’‧‧‧L形間隔物
115‧‧‧氮化物層、氮化物間隔物
117‧‧‧光阻層
301‧‧‧犧牲硬罩、硬罩、硬罩層
303‧‧‧光阻層
401‧‧‧RSD結構
601‧‧‧硬罩層、硬罩、犧牲硬罩
603‧‧‧光阻層
701‧‧‧RSD結構
901‧‧‧NFET SG結構、NFET SG閘極結構
903‧‧‧NFET EG結構、NFET EG閘極結構
905‧‧‧PFET SG結構、PFET SG閘極結構
907‧‧‧PFET EG結構、PFET EG閘極結構
909‧‧‧高K金屬閘極
911‧‧‧矽層
912‧‧‧閘極蓋體
913‧‧‧厚閘極氧化物層
915‧‧‧埋置型氧化物(BOX)層、BOX層
917‧‧‧矽通道層、Si層
921‧‧‧BOX層淺溝槽隔離(STI)區
923‧‧‧氮化物層
925‧‧‧氧化物襯墊
1001‧‧‧光阻層
1101‧‧‧氮化物層
1301‧‧‧光阻層
1601‧‧‧光阻層
1801‧‧‧RSD結構
1901‧‧‧氮化物層
1903‧‧‧光阻層
2001‧‧‧RSD結構
2201‧‧‧NFET SG閘極結構、NFET SG結構
2203‧‧‧NFET EG閘極結構、NFET EG結構
2205‧‧‧PFET SG結構、PFET SG閘極結構
2207‧‧‧PFET EG結構、PFET EG閘極結構
2209‧‧‧高K金屬閘極
2211‧‧‧矽層
2212‧‧‧閘極蓋體
2213‧‧‧厚閘極氧化物層
2215‧‧‧BOX層
2217‧‧‧Si通道層、Si層
2219‧‧‧SiGe通道層、SiGe層
2221‧‧‧STI區
2223‧‧‧氮化物層
2225‧‧‧氧化物襯墊
2227‧‧‧氮化物層
2501‧‧‧光阻層
2701‧‧‧光阻層
2801‧‧‧RSD結構
2901‧‧‧氮化物層
2903‧‧‧光阻層
3001‧‧‧RSD結構
本揭露是在隨附圖式的附圖中舉例來說明，但非作為限制，圖中相同的參考元件符號係指類似的元件，並且其中：第1至8圖根據一例示性具體實施例，繪示用於就SG與EG閘極結構以相異寬度形成匹配之PFET/NFET間隔物之程序流程；第9至21圖根據一例示性具體實施例，示 意性繪示就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構形成具有不同氮化物間隔物寬度之FDSOI HKMG裝置的程序流程；以及第22至31圖根據一例示性具體實施例，示意性繪示就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構形成具有不同氮化物及/或氮化物/氧化物間隔物寬度之FDSOI HKMG裝置的另一程序流程。
在底下的說明中，為了解釋，提出許多特定細節以便透徹理解例示性具體實施例。然而，應顯而易知的是，沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中，眾所周知的結構及裝置是以方塊圖形式來展示，為的是要避免不必要地混淆例示性具體實施例。另外，除非另有所指，本說明書及申請專利範圍中用來表達成分、反應條件等等之量、比率、及數值特性的所有數字都要了解為在所有實例中是以「約」一語來修飾。
本揭露處理並解決以下目前面臨的問題：在整合型RSD形成後，因汲極電壓高，所以就效能與可靠度及間隔物崩潰方面，PFET及NFET SG與EG閘極結構會有不平衡的問題。本揭露亦因應並解決FDSOI HKMG形成所帶來氮化物/氧化物間隔物形成控制困難之當前問題。
根據本揭露之具體實施例之方法包括在基材上提供PFET SG與EG閘極結構及NFET SG與EG閘極 結構，該等PFET及NFET結構側向隔開。第一保形氮化物層及氧化物襯墊是在該基材上方形成，而第二保形氮化物層是在該等PFET及NFET EG閘極結構之側壁上形成。將該第一氮化物層及該氧化物襯墊之水平部分從該等PFET SG與EG閘極結構上方移除，並且在各該PFET SG與EG閘極結構之對立側上形成RSD結構。將該第一氮化物層及該氧化物襯墊之水平部分從該等NFET SG與EG閘極結構上方移除，並且在各該NFET SG與EG閘極結構之對立側上形成RSD結構。
單純地藉由描述所思及之最佳模式，還有其它態樣、特徵、以及技術功效經由下文的實施方式對於所屬技術領域中具有通常知識者將顯而易知，其中表示並且說明的是較佳具體實施例。本揭露能夠是其它及不同的具體實施例，而且其數項細節能夠在各種明顯方面進行修改。因此，圖式及說明本質上要視為說明性，而不是作為限制性。
第1至8圖(截面圖)係根據例示性具體實施例，繪示用於就SG與EG閘極結構以相異寬度形成匹配之PFET/NFET間隔物之程序流程。言及第1圖，在基材109上形成PFET SG閘極結構101、PFET EG閘極結構103、NFET SG閘極結構105、以及NFET SG閘極結構107。各閘極結構包括氮化物閘極蓋體110。氮化物層111是在基材109上方以保形方式形成。氮化物層111舉例而言，可由低K SiOCN、高溫(630℃)iRadTM氮化物、或低K SiBCN 所構成，厚度達4nm至8nm。氮化矽層111需要厚到足以防止磊晶矽在RSD區域中生長，但需要薄到足以最佳化此等源極/汲極區之重疊。還在基材109上方形成氧化物襯墊113，其舉例來說，係由未摻雜氧化物(UDOX)、iRadTM氧化物、或臭氧四乙氧基矽烷(TEOS)所構成。氧化物襯墊113在厚度方面，舉例而言，可形成達3nm至6nm。氧化物襯墊113需要能夠耐受後續所形成之氮化物層移除及犧牲硬罩蝕刻。
其次，氮化物層115是在基材109上方以保形方式形成。氮化物層115係由與氮化物層111相同的材料所構成，並且在厚度方面舉例來說，可形成達3nm至15nm，端視技術(即多晶間距或鰭片間距)、可靠度限制條件、以及操作汲極電壓而定。氮化物層115必須對程序中後續的犧牲硬罩具有選擇性。氮化物層115接著舉例來說，係使用四氟甲烷(CF4)藉由反應性離子蝕刻(RIE)向下蝕刻至氧化物襯墊113而形成外部間隔物。光阻層117接著是分別在PFET及NFET EG閘極結構103及107上方形成，而氮化物層115是藉由等向性且對氧化物襯墊113具有選擇性之蝕刻劑，分別從PFET及NFET SG閘極結構101及105移除，如第2圖所示。接著移除光阻層117。
言及第3圖，在基材109上方形成犧牲硬罩301。該硬罩係由對氮化物層115具有選擇性之材料所構成，例如：450℃至500℃的iRadTM氮化物或電漿增強型化學氣相沉積(PECVD)氮化物。光阻層303接著是分別在 NFET SG與EG閘極結構105與107上方形成。接著舉例來說，使用熱磷酸將PFET SG與EG閘極結構101與103上方之硬罩301分別移除。硬罩301舉例而言，亦可使用氟代甲烷/氧化物(CH3F/O2)藉由RIE來移除，用以等向性蝕刻硬罩301並於氧化物襯墊113上終止。
接著，例如使用CF4，藉由RIE將氧化物襯墊113及氮化物層111向下非等向性蝕刻至基材109及閘極蓋體110，在PFET EG閘極結構103之對立側上形成氮化物L形間隔物111’及氧化物L形間隔物113’，如第4圖所示。在最終PFET間隔物蝕刻之後，移除光阻層303。氧化物襯墊113亦可藉由氫氟(HF)預清潔來移除，在PFET SG閘極結構101上留下氮化物L形間隔物111’。之後，藉由磊晶生長來形成RSD結構401，而互補裝置則受犧牲硬罩301保護。L形間隔物111’及113’之水平表面之特定長度，例如2nm至6nm，將會取決於諸如磊晶先驅物氣體、鹽酸(HCL)流動、間隔物材料、及間隔物形狀等因素之組合而定。視需要地，生長RSD結構401之後，薄氧化物襯墊(為便於說明而未圖示)可舉例來說，藉由電漿氧化作用或藉由經沉積之氧化物來形成，以在進一步處理步驟期間保護RSD結構401。若沉積薄氧化物襯墊，則應該儘量薄，例如：2nm至3nm，以防止NFET SG閘極結構105之最終L形間隔物變得太寬。
言及第5圖，將硬罩層301從NFET SG與EG閘極結構105與107上方分別等向性移除。接著，類似 於第3圖之步驟，在基材109上方形成新硬罩層601，如第6圖所示。或者，在沉積硬罩層601之前，硬罩層301可分別留在NFET SG與EG閘極結構105與107上方。光阻層603接著是分別在PFET SG與EG閘極結構101與103上方形成，而NFET SG與EG閘極結構105與107上方之硬罩層601(及硬罩層301，若仍存在)則舉例來說，使用熱磷酸來等向性移除，如第7圖所示。類似於硬罩層301，硬罩層601亦可舉例而言，使用CH3F/O2藉由RIE來移除。
例如使用CF4，藉由RIE將氧化物襯墊113及氮化物層111向下非等向性蝕刻至基材109及閘極蓋體110，分別在NFET SG與EG閘極結構105與107之對立側上形成氮化物L形間隔物111’及氧化物L形間隔物113’。在最終NFET間隔物蝕刻之後，移除光阻層603。再次地，氧化物襯墊113亦可藉由在NFET SG閘極結構105上形成氮化物L形間隔物111’之HF預清潔來移除。接著，藉由磊晶生長來形成RSD結構701，而互補裝置則受犧牲硬罩601保護。視需要地，生長RSD結構701之後，薄氧化物襯墊(為便於說明而未圖示)可舉例來說，再次地藉由電漿氧化作用或藉由經沉積之氧化物來形成，以在後續移除硬罩層601期間保護RSD結構701。接著，舉例來說，以熱磷酸或使用CH3F/O2之RIE，將PFET SG與EG閘極結構101與103上方之硬罩601分別等向性移除，如第8圖所示。所以，氮化物間隔物111’及115就PFET及NFET SG與EG閘極結構具有匹配寬度。同樣地，SG效能與EG可靠度要 求達到平衡。
第9至21圖(截面圖)根據一例示性具體實施例，示意性繪示就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構形成具有不同氮化物間隔物寬度之FDSOI HKMG裝置的程序流程。言及第9圖，FDSOI基材(為便於說明而未圖示)上方分別形成NFET SG與EG閘極結構901與903、以及分別形成PFET SG與EG結構905與907。各閘極結構包括高K金屬閘極909、矽層911、及氮化物閘極蓋體912，而相較於SG側上看不到的閘極氧化物，NFET及PFET EG結構903及907亦分別包括厚閘極氧化物層913。埋置型氧化物(BOX)層915及矽通道層917或SiGe通道層919是在FDSOI基材上方、及諸BOX層淺溝槽隔離(STI)區921之間形成。氮化物層923接著是在基材上方以保形方式形成。氮化物層923可藉由分子層沉積(MLD)來形成，厚度舉例來說，達56埃(Å)至64Å。之後，在氮化物層923上方以保形方式形成氧化物襯墊925，厚度舉例而言，達20Å至40Å。
言及第10圖，分別在NFET及PFET SG結構901及905上方形成光阻層1001，並且將氧化物襯墊925分別從NFET與PFET EG結構903與907、及基材移除。氧化物襯墊925舉例而言，可藉由WINGTM或SiCoNiTM程序來移除。之後，移除光阻層1001。氮化物層1101接著藉由MLD在基材上方以保形方式形成，厚度達60Å至80Å，如第11圖所示。接著，氮化物層1101之水平部分， 舉例而言，藉由向下進行間隔物蝕刻至剩餘氧化物襯墊925來移除，如第12圖所示。約略40%至80%之晶片面積在此時是被氧化物襯墊925包覆，因此，其作用為充分清楚的蝕刻終止信號。氮化物層923因蝕刻氮化物層1101所導致的損耗因而降到最小，例如：小於10Å。
進行軟性清潔，然後分別在NFET及PFET EG閘極結構903及907上方形成光阻層1301，如第13圖所示。言及第14圖，藉由對氧化物高度具有選擇性之等向性氮化物蝕刻，例如：二氟甲烷(CH2F2)或CH3F，分別將氮化物層1101之垂直部分從NFET及PFET SG閘極結構901及905移除。接著，將光阻層1301剥除，並且舉例來說，藉由濕或乾蝕刻將氧化物襯墊925移除，如第15圖所示。晶圓表面於此步驟係完全受氮化物層923保護，因此，應該不會因移除氧化物襯墊925而對晶圓造成損壞。
言及第16圖，光阻層1601是分別在NFET SG與EG閘極結構901與903上方形成。或者，光阻層1601可分別在PFET SG與EG閘極結構905與907上方形成。是否要先遮罩NFET或PFET閘極結構係取決於各裝置之所欲間隔物厚度，因為較晚階段遮罩產生之間隔物較厚。接著舉例來說，氮化物層923之已曝露水平部分係藉由RIE分別從PFET SG及EG結構905及907移除，如第17圖所示。之後，剥除光阻層1601，而磊晶預清潔程序係例如使用已稀釋氫氟酸(DHF)/SiCoNiTM來進行，其將會移除一些BOX層915(為便於說明而未圖示)。
接著，分別在相鄰於PFET SG與EG結構905與907之SiGe層919及Si層917上、或分別在相鄰於NFET SG與EG結構901與903之Si層917上，藉由磊晶生長來形成RSD結構1801，端視先遮罩的是哪些閘極結構而定，如第18圖所示。接著，氮化物層1901是在整個基材(為便於說明而未圖示)上方形成。接著，分別在PFET SG與EG閘極結構905與907上方、或分別在NFET SG與EG閘極結構901與903上方形成光阻層1903，端視先遮罩的是哪些閘極結構而定。接著，舉例來說，氮化物層1901及923之水平部分係藉由RIE分別從NFET SG及EG結構901及903移除。
言及第20圖，類似於第17圖，剥除光阻層1903，而磊晶預清潔程序係例如使用DHF/SiCoNiTM來進行，再次地移除一些BOX層915(為便於說明而未圖示)。接著分別在相鄰於NFET SG與EG結構901與903之Si層917上、或分別在相鄰於PFET SG與EG結構905與907之SiGe層919及Si層917上，藉由磊晶生長來形成RSD結構2001，端視先遮罩的是哪些閘極結構而定。其次，移除閘極蓋體912，並且舉例來說，使用熱磷酸，藉由RIE或藉由適當的濕蝕刻，將氮化物層923、1101及1901向下蝕刻至矽層911之上表面，如第21圖所示。接著，氮化物層1901係從RSD結構1801或2001終仍剩餘處被移除。氮化物層923、1101、及1901之移除亦可用視需要的有機平坦化層(OPL)加上回蝕保護來進行。之後，進行間隔物氮化物 沉積、蝕刻、及矽化(為便於說明而未圖示)。
第22至31圖(截面圖)根據一例示性具體實施例，示意性繪示就NFET SG閘極結構、PFET SG結構、及PFET/NFET EG閘極結構形成具有不同氮化物及/或氮化物/氧化物間隔物寬度之FDSOI HKMG裝置的另一程序流程。言及第22圖，類似於第9圖，FDSOI基材(為便於說明而未圖示)上方分別形成NFET SG與EG閘極結構2201與2203、以及分別形成PFET SG與EG結構2205與2207。各閘極結構包括高K金屬閘極2209、矽層2211、及閘極蓋體2212，而相較於SG側上看不到的閘極氧化物，NFET及PFET EG結構2203及2207亦分別包括厚閘極氧化物層2213。BOX層2215及Si通道層2217或SiGe通道層2219是在FDSOI基材上方形成，而STI區2221是在BOX層2215之間形成。氮化物層2223接著是在基材上方以保形方式形成。氮化物層2223可藉由MLD來形成，厚度舉例來說，達56埃(Å)至64Å。之後，在氮化物層2223上方以保形方式形成氧化物襯墊2225，厚度舉例而言，達20Å至40Å。
接著，氮化物層2227是在基材上方藉由MLD以保形方式形成，厚度達60Å至80Å，如第23圖所示。氮化物層2227之水平部分係接著舉例而言，藉由向下進行間隔物蝕刻至氧化物襯墊2225來移除，留下觸碰不到的氮化物層2223，如第24圖所示。之後，例如使用冷SC1溶液來進行軟性清潔。
言及第25圖，光阻層2501是分別在NFET 與PFET EG閘極結構2203與2207上方形成。接著，舉例而言，藉由對氧化物高度具有選擇性之等向性氮化物蝕刻，例如：CH2F2或CH3F，分別將氮化物層2227之垂直部分從NFET及PFET SG閘極結構2201及2205移除。接著，將光阻層2501剥除，並且舉例來說，藉由濕或乾蝕刻將曝露之氧化物襯墊2225移除，僅分別在NFET及PFET EG閘極結構2203及2207之氮化物層2223與2227之間留下氧化物襯墊2225，如第26圖所示。
第27至31圖大體上遵循如同第16至21圖之程序流程；然而，產生之裝置需要的遮罩少一個，而且還分別在NFET及PFET EG閘極結構2203及2207中包括小L形氧化物襯墊2225。言及第27圖，光阻層2701是分別在NFET SG與EG閘極結構2201與2203上方形成。或者，光阻層2701可分別在PFET SG與EG閘極結構2205與2207上方形成。是否要先遮罩NFET或PFET閘極結構係取決於各裝置之所欲間隔物厚度，因為較晚階段遮罩產生之間隔物較厚。接著舉例來說，氮化物層2223之水平部分係藉由RIE分別從PFET SG及EG結構2205及2207移除。之後，剥除光阻層2701，而磊晶預清潔程序係例如使用DHF/SiCoNiTM來進行，其將會移除一些BOX層2215(為便於說明而未圖示)。
接著，分別在相鄰於PFET SG與EG結構2205與2207之SiGe層2219及Si層2217上、或分別在相鄰於NFET SG與EG結構2201與2203之Si層2217上，藉 由磊晶生長來形成RSD結構2801，端視先遮罩的是哪些閘極結構而定，如第28圖所示。言及第29圖，氮化物層2901是在整個基材(為便於說明而未圖示)上方以保形方式形成。接著，分別在PFET SG與EG閘極結構2205與2207上方、或分別在NFET SG與EG閘極結構2201與2203上方形成光阻層2903，端視第27圖中先遮罩的是哪些閘極結構而定。接著舉例來說，藉由RIE移除氮化物層2901及2223之已曝露水平部分。
言及第30圖，剥除光阻層2903，而磊晶預清潔程序係再次地例如使用DHF/SiCoNiTM來進行，移除一些BOX層2215(為便於說明而未圖示)。接著分別在相鄰於NFET SG與EG結構2201與2203之Si層2217上、或分別在相鄰於PFET SG與EG結構2205與2207之SiGe層2219及Si層2217上，藉由磊晶生長來形成RSD結構3001，端視第27圖中先遮罩的是哪些閘極結構而定。
接著，移除閘極蓋體2212，並且舉例來說，使用熱磷酸，藉由RIE或藉由適當的濕蝕刻，將氮化物層2223、2227及2901、以及氧化物襯墊2225向下蝕刻至矽層2211之上表面，如第31圖所示。接著，氮化物層2901係從RSD結構2801或3001中仍剩餘處被移除。氮化物層2223、2227、及2901、以及氧化物襯墊2225之移除亦可用視需要的OPL加上回蝕保護來進行。之後，進行間隔物氮化物沉積、蝕刻、及矽化(為便於說明而未圖示)。
本揭露之具體實施例可達到數種技術功 效，包括另外需要的遮罩層僅一個(重複使用現有的EG遮罩)；形成更厚的NFET及PFET EG間隔物以提升可靠度但未犧牲SG效能；形成匹配之PFET及NFET間隔物；以及形成因L形間隔物而具有受刻面RSD(faceted RSD)的SG裝置，使閘極與RSD間電容降低，並且使寄生電容(Ceff)改善，其直接導致交流效能提升。本揭露之具體實施例亦可達到數種另外的技術功效，包括就FDSOI上之SG NFET、SG PFET、及PFET/NFET EG閘極結構、以及所有具有完全氮化物間隔物之閘極結構，形成不同且獨立之間隔物厚度。舉例而言，本揭露之具體實施例在各種工業應用中享有實用性，如：微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD錄影機與播放器、汽車導航、列印機與週邊裝置、網路連結與電信設備、遊戲系統、以及數位相機。本揭露因此在FDSOI裝置及/或任何需要RSD磊晶之任何技術中享有產業利用性。
在前述說明中，本揭露係參照其具體例示性具體實施例來說明。然而，明顯的是，可對其實施各種修改和變更而不脫離本揭露較廣之精神與範疇，如申請專利範圍所提。本說明書及圖式從而要視為說明性而非作為限制性。應了解的是，本揭露能夠使用各種其它組合及具體實施例，並且如本文中所表達，能夠在本發明概念的範疇內作任何變更或修改。
101‧‧‧PFET SG閘極結構
103‧‧‧PFET EG閘極結構
105‧‧‧NFET SG閘極結構
107‧‧‧NFET EG閘極結構
109‧‧‧基材
111’‧‧‧L形間隔物、氮化物間隔物
113’‧‧‧L形間隔物
115‧‧‧氮化物層、氮化物間隔物
401‧‧‧RSD結構
701‧‧‧RSD結構

Claims (20)

  1. 一種方法，其包含：在基材上提供p型場效電晶體(PFET)核心裝置(SG)與I/O裝置(EG)閘極結構、n型場效電晶體(NFET)SG與EG閘極結構，該等PFET及NFET結構側向隔開；在該基材上方形成第一保形氮化物層；在該基材上方形成氧化物襯墊；在該等PFET及NFET EG閘極結構之側壁上形成第二保形氮化物層；移除該第一氮化物層及該氧化物襯墊在該等PFET SG與EG閘極結構及基材上方之水平部分；在各該PFET SG與EG閘極結構之對立側上形成隆起源極/汲極(RSD)結構；移除該第一氮化物層及該氧化物襯墊在該等NFET SG與EG閘極結構及基材上方之水平部分；以及在各該NFET SG與EG閘極結構之對立側上形成RSD結構。
  2. 如申請專利範圍第1項所述之方法，其包含在該等PFET及NFET EG閘極結構之該等側壁上形成第二保形氮化物層係藉由下列步驟：在該基材上方形成該第二保形氮化物層；將該第二保形氮化物層向下平坦化至該氧化物襯墊；在該等PFET及NFET EG閘極結構上方形成光阻 層；將該第二保形氮化物層從該等PFET及NFET SG閘極結構移除；以及移除該光阻層。
  3. 如申請專利範圍第1項所述之方法，其包含移除該第一氮化物層及該氧化物襯墊在該等PFET SG與EG閘極結構及基材上方之該等水平部分係藉由下列步驟：在該基材上方形成硬罩層；在該等NFET SG與EG閘極結構上方形成光阻層；移除該等PFET SG與EG閘極結構上方之該硬罩層；將該第一保形氮化物層及該氧化物襯墊向下蝕刻至該基材；以及移除該光阻層。
  4. 如申請專利範圍第3項所述之方法，其中，該蝕刻形成位在各該PFET SG與EG閘極結構之對立側上之L形第一保形氮化物層間隔物、及位在該PFET EG閘極結構之對立側上之L形氧化物襯墊間隔物。
  5. 如申請專利範圍第1項所述之方法，其包含移除該第一氮化物層及該氧化物襯墊在該等NFET SG與EG閘極結構及基材上方之該等水平部分係藉由下列步驟：在該基材上方形成硬罩層；在該等PFET SG與EG閘極結構上方形成光阻層；移除該等NFET SG與EG閘極結構上方之該硬罩 層；將該第一保形氮化物層及該氧化物襯墊向下蝕刻至該基材；移除該光阻層；以及移除該等PFET SG與EG閘極結構上方之該硬罩層。
  6. 如申請專利範圍第5項所述之方法，其中，該蝕刻形成位在各該NFET SG與EG閘極結構之對立側上之L形第一保形氮化物層間隔物、及位在該NFET EG閘極結構之對立側上之L形氧化物襯墊間隔物。
  7. 如申請專利範圍第1項所述之方法，其中，各該PFET及NFET SG閘極結構之該等對立側上所形成之該等RSD結構係受到刻面。
  8. 一種裝置，其包含：基材上所形成之p型場效電晶體(PFET)核心裝置(SG)與I/O裝置(EG)閘極結構、n型場效電晶體(NFET)SG與EG閘極結構，該等PFET及NFET結構側向隔開；該基材上且相鄰於各該PFET及NFET SG與EG閘極結構之側壁所形成之一對L形氮化物間隔物；該等PFET及NFET EG閘極結構之各L形氮化物間隔物上且與之相鄰所形成之L形氧化物間隔物；各L形氧化物間隔物上且與之相鄰所形成之氮化物間隔物；各該PFET及NFET SG閘極結構之對立側上所形成 之刻面隆起源極/汲極(RSD)結構；以及各該PFET及NFET EG閘極結構之對立側上所形成之RSD結構。
  9. 如申請專利範圍第8項所述之裝置，其中，各L形氮化物間隔物及各氮化物間隔物係由矽氧碳氮化物(SiOCN)、高溫iRadTM氮化物、或矽硼碳氮化物(SiBCN)所構成。
  10. 一種方法，其包含：在全空乏絕緣體上矽(FDSOI)基材上提供n型場效電晶體(NFET)核心裝置(SG)與I/O裝置(EG)閘極結構、及p型場效電晶體(PFET)SG與EG閘極結構，該等SG與EG結構側向隔開，並且各包括閘極及閘極覆蓋層；在該等NFET及PFET SG與EG閘極結構及該基材上方形成保形第一氮化物層；在該等NFET及PFET SG與EG閘極結構及基材上方形成氧化物襯墊；在該等NFET及PFET SG與EG結構及基材上方形成第二保形氮化物層；移除該第二氮化物層之水平部分；遮罩該等NFET及PFET EG閘極結構；移除該第二氮化物層相鄰於該等NFET及PFET SG結構及已曝露氮化物襯墊之垂直部分；遮罩NFET或PFET EG與SG閘極結構；移除該第一氮化物層之水平部分； 分別在相鄰於該等PFET或NFET SG與EG結構之該基材上形成隆起源極/汲極(RSD)結構；在該整個基材上方形成第三氮化物層；分別遮罩PFET或NFET SG與EG閘極結構；移除該第三氮化物層之水平部分；分別在該等PFET或NFET SG與EG閘極結構之對立側上形成RSD結構；以及將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋層、及該氧化物襯墊向下移除至該閘極之上表面。
  11. 如申請專利範圍第10項所述之方法，其包含：在形成該氧化物襯墊之後，遮罩該等NFET及PFET SG結構；從該等NFET及PFET EG閘極結構移除該氧化物襯墊；以及移除該遮罩。
  12. 如申請專利範圍第10項所述之方法，其包含移除該第二氮化物層之該等水平部分係藉由下列步驟：將該第二氮化物層向下蝕刻至該氧化物襯墊。
  13. 如申請專利範圍第10項所述之方法，其包含：在遮罩該等NFET及PFET SG與EG閘極結構前，先移除該等NFET及PFET EG閘極結構之該遮罩。
  14. 如申請專利範圍第10項所述之方法，其包含在形成相鄰於該等PFET或NFET SG與EG結構之該等RSD結構 前，先移除該等NFET及PFET SG與EG閘極結構之該遮罩。
  15. 如申請專利範圍第10項所述之方法，其包含在將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋層、及該氧化物襯墊向下移除至該閘極之上表面前，先移除該等PFET或NFET SG與EG閘極結構之該遮罩。
  16. 如申請專利範圍第15項所述之方法，其包含：從該等NFET或PFET EG與SG閘極結構之該等對立側上的該等RSD結構上方移除該第三氮化物層；以及將該等第一、第二、及第三氮化物層及該閘極覆蓋層或該等第一、第二、及第三氮化物層、該閘極覆蓋層、及該氧化物襯墊向下移除至該閘極之上表面後，進行間隔物氮化物沉積、蝕刻、及矽化。
  17. 一種裝置，其包含：全空乏絕緣體上矽(FDSOI)基材；p型場效電晶體(PFET)核心裝置(SG)與I/O裝置(EG)閘極結構、及n型場效電晶體(NFET)SG與EG閘極結構，形成在該FDSOI基材上，該等SG與EG結構側向隔開；雙氮化物層間隔物，形成在該等NFET及PFET SG閘極結構之各側壁上；三重氮化物層間隔物，形成在該等NFET及PFET EG閘極結構之各側壁上；以及隆起源極/汲極(RSD)結構，形成在該等NFET及PFET SG與EG閘極結構之對立側上。
  18. 如申請專利範圍第17項所述之裝置，其中，該雙氮化物層間隔物比該三重氮化物層間隔物更薄。
  19. 如申請專利範圍第17項所述之裝置，其中，該PFET SG閘極結構是在矽鍺(SiGe)層上方形成，而該等PFET EG及NFET SG與EG結構是在矽層上方形成。
  20. 如申請專利範圍第17項所述之裝置，其中，氧化物層是在該等NFET及PFET EG結構之第一及第二氮化物層之間形成。
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