CN107425058A - 间隔物整合的方法及所产生的装置 - Google Patents

间隔物整合的方法及所产生的装置 Download PDF

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CN107425058A
CN107425058A CN201710331380.0A CN201710331380A CN107425058A CN 107425058 A CN107425058 A CN 107425058A CN 201710331380 A CN201710331380 A CN 201710331380A CN 107425058 A CN107425058 A CN 107425058A
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pfet
nfet
structures
grid
grid structures
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CN107425058B (zh
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乔治·罗伯特·姆芬格
R·施波雷尔
R·J·卡特
彼特·巴尔斯
H·J·特厄斯
J·亨切尔
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GlobalFoundries US Inc
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Abstract

本发明涉及间隔物整合的方法及所产生的装置，所提供的是一种就SG与EG结构以相异宽度形成匹配的PFET/NFET间隔物的方法、及一种就SG NFET与SG PFET结构及PFET/NFET EG结构形成相异宽度氮化物间隔物的方法、以及其各别产生的装置。具体实施例包括提供PFET SG与EG结构及NFET SG与EG结构；在衬底上方形成第一氮化物层；形成氧化物衬垫；在PFET及NFET EG结构的侧壁上形成第二氮化物层；移除第一氮化物层及氧化物衬垫在PFET SG与EG结构上方的水平部分；在各PFET SG与EG结构的对立侧上形成RSD结构；移除第一氮化物层及氧化物衬垫在NFET SG与EG结构上方的水平部分；以及在各NFET SG与EG结构的对立侧上形成RSD结构。

Description

间隔物整合的方法及所产生的装置
技术领域
本发明是关于p型场效应晶体管(PFET)及n型场效应晶体管(NFET)核心装置(SG)与I/O装置(EG)间隔物整合。本发明尤其是，适用于完全耗尽型绝缘体上硅(FDSOI)装置及/或需要隆起源极/漏极(RSD)外延的任何技术。
背景技术
EG装置需要更厚的间隔物才能通过标准可靠度要求。不过，SG装置上希望薄间隔物以维持标准效能准则。典型的双RSD整合凭靠添加的NFET/PFET间隔物以阻绝不希望的外延(epi)生长。然而，具有更厚间隔物的装置通常影响到效能。具体而言，高RSD/栅极电容使Fmax降低。已知的方法涉及使用多重间隔物材料来强制RSD外延刻面；在所有装置上使用更厚的间隔物而牺牲SG效能；或添加另两个间隔物、屏蔽层、及外延步骤以支撑NFET及PFETEG装置。另一种已知方法涉及形成氮化物/氧化物间隔物合夹，其由于使用例如多重外延预清洁的数个氧化物消耗步骤而难以控制。
因此，需要能以匹配的NFET/PFET间隔物宽度使SG效能与EG可靠度达到平衡的方法、能在FDSOI上以不同间隔物厚度形成SG NFET、SG PGET、及EG NFET与PFET装置的方法、以及其产生的装置。
发明内容
本发明的一态样是一种就SG与EG栅极结构以相异宽度形成匹配的PFET/NFET间隔物的程序。
本发明的另一态样是一种就该SG与EG栅极结构以相异宽度包括匹配的PFET/NFET间隔物的装置。
本发明的再一态样是一种分别就NFET SG栅极结构、PFET SG结构、及PFET/NFETEG栅极结构形成相异宽度氮化物间隔物的程序。
本发明的一附加态样是一种就NFET SG栅极结构、PFET SG结构、及PFET/NFET EG栅极结构具有各别氮化物间隔物宽度的FDSOI高k金属栅极(HKMG)装置。
本发明的附加态样及其它特征将会在以下说明中提出，并且对于审查以下内容的所属领域技术人员部分将会显而易见，或可经由实践本发明来学习。可如随附权利要求书中特别指出的内容来实现并且获得本发明的优点。
根据本发明，可通过一种方法来达到一些技术功效，该方法包括：在衬底上提供PFET SG与EG栅极结构及NFET SG与EG栅极结构，该PFET及NFET结构侧向隔开；在该衬底上方形成第一保形氮化物层；在该衬底上方形成氧化物衬垫；在该PFET及NFET EG栅极结构的侧壁上形成第二保形氮化物层；移除该第一氮化物层及该氧化物衬垫在该PFET SG与EG栅极结构及衬底上方的水平部分；在各该PFET SG与EG栅极结构的对立侧上形成RSD结构；移除该第一氮化物层及该氧化物衬垫在该NFET SG与EG栅极结构及衬底上方的水平部分；以及在各该NFET SG与EG栅极结构的对立侧上形成RSD结构。
本发明的态样包括在该PFET及NFET EG栅极结构的该侧壁上形成第二保形氮化物层是通过下列步骤：在该衬底上方形成该第二保形氮化物层；将该第二保形氮化物层向下平坦化至该氧化物衬垫；在该PFET及NFET EG栅极结构上方形成光阻层；将该第二保形氮化物层从该PFET及NFET SG栅极结构移除，以及移除该光阻层。其它态样包括移除该第一氮化物层及该氧化物衬垫在该PFET SG与EG栅极结构及衬底上方的该水平部分是通过下列步骤：在该衬底上方形成硬掩模层；在该NFETSG与EG栅极结构上方形成光阻层；移除该PFETSG与EG栅极结构上方的该硬掩模层；将该第一保形氮化物层及该氧化物衬垫向下蚀刻至该衬底；以及移除该光阻层。进一步态样包括该蚀刻形成位在各该PFETSG与EG栅极结构的对立侧上的L形第一保形氮化物层间隔物、及位在该PFET EG栅极结构的对立侧上的L形氧化物衬垫间隔物。附加态样包括移除该第一氮化物层及该氧化物衬垫在该NFE SG与EG栅极结构及衬底上方的该水平部分是通过下列步骤：在该衬底上方形成硬掩模层；在该PFET SG与EG栅极结构上方形成光阻层；移除该NFET SG与EG栅极结构上方的该硬掩模层；将该第一保形氮化物层及该氧化物衬垫向下蚀刻至该衬底；移除该光阻层；以及移除该PFET SG与EG栅极结构上方的该硬掩模层。另一态样包括该蚀刻形成位在各该NFET SG与EG栅极结构的对立侧上的L形第一保形氮化物层间隔物、及位在该NFET EG栅极结构的对立侧上的L形氧化物衬垫间隔物。其它态样包括各该PFET及NFET SG栅极结构的该对立侧上所形成的该RSD结构受到刻面。
本发明的另一态样是一种装置，其包括：衬底上所形成的PFET SG与EG栅极结构及NFET SG与EG栅极结构，该PFET与NFET结构侧向隔开；该衬底上且相邻于各该PFET及NFETSG与EG栅极结构的侧壁所形成的一对L形氮化物间隔物；该PFET及NFET EG栅极结构的各L形氮化物间隔物上且与各该L形氮化物间隔物相邻所形成的L形氧化物间隔物；各L形氧化物间隔物上且与各该L形氧化物间隔物相邻所形成的氮化物间隔物；各该PFET及NFET SG栅极结构的对立侧上所形成的刻面RSD结构；以及各该PFET及NFET EG栅极结构的对立侧上所形成的RSD结构。该装置的态样包括各L形氮化物间隔物及各氮化物间隔物是由硅氧碳氮化物(SiOCN)、高温iRadTM氮化物、或硅硼碳氮化物(SiBCN)所构成。
本发明的再一态样是一种方法，其包括：在FDSOI衬底上提供NFETSG与EG栅极结构及PFET SG与EG栅极结构，该SG与EG结构侧向隔开，并且各包括栅极及栅极覆盖层；在该NFET及PFET SG与EG栅极结构及该衬底上方形成保形第一氮化物层；在该NFET及PFET SG与EG栅极结构及衬底上方形成氧化物衬垫；在该NFET及PFET SG与EG结构及衬底上方形成第二保形氮化物层；移除该第二氮化物层的水平部分；屏蔽该NFET及PFET EG栅极结构；移除该第二氮化物层相邻于该NFET及PFET SG结构及已曝露氮化物衬垫的垂直部分；屏蔽NFET或PFET EG与SG栅极结构；移除该第一氮化物层的水平部分；分别在该衬底上相邻于该PFET或NFET SG与EG结构形成RSD结构；在该整个衬底上方形成第三氮化物层；分别屏蔽PFET或NFET SG与EG栅极结构；移除该第三氮化物层的水平部分；分别在该PFET或NFET SG与EG栅极结构的对立侧上形成RSD结构；以及将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面。
本发明的态样包括在形成该氧化物衬垫之后屏蔽该NFET及PFETSG结构；从该NFET及PFET EG栅极结构移除该氧化物衬垫；以及移除该屏蔽。其它态样包括移除该第二氮化物层的该水平部分是通过下列步骤：将该第二氮化物层向下蚀刻至该氧化物衬垫。进一步态样包括在屏蔽该NFET及PFET SG与EG栅极结构前，先移除该NFET及PFET EG栅极结构的该屏蔽。附加态样包括在形成相邻于该PFET或NFET SG与EG结构的该RSD结构前，先移除该NFET及PFET SG与EG栅极结构的该屏蔽。另一态样包括在将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面前，先移除该PFET或NFET SG与EG栅极结构的该屏蔽。其它态样包括将该第三氮化物层从该NFET或PFETEG与SG栅极结构的该对立侧上的该RSD结构上方移除；以及将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面后，进行间隔物氮化物沉积、蚀刻、及硅化。
本发明的另一态样是一种装置，其包括：FDSOI衬底；该FDSOI衬底上所形成的PFETSG与EG栅极结构及NFET SG与EG栅极结构，该SG与EG结构侧向隔开；该NFET及PFET SG栅极结构的各侧壁上所形成的双氮化物层间隔物；该NFET及PFET EG栅极结构的各侧壁上所形成的三重氮化物层间隔物；以及该NFET及PFET SG与EG栅极结构的对立侧上所形成的RSD结构。该装置的态样包括该双氮化物层间隔物比该三重氮化物层间隔物更薄。其它态样包括该PFET SG栅极结构是在硅锗(SiGe)层上方形成，而该PFET EG及NFET SG与EG结构是在硅层上方形成。进一步态样包括氧化物层是在该NFET及PFET EG结构的第一及第二氮化物层之间形成。
本发明的附加态样及技术功效经由以下详细说明对于所属领域技术人员将会轻易地变为显而易见，其中本发明的具体实施例单纯地通过经深思用以实行本发明的最佳模式的说明来描述。如将会了解的是，本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改，全都不会脱离本发明。因此，图式及说明本质上要视为说明性，而不是作为限制性。
附图说明
本发明是在随附图式的附图中举例来说明，但非作为限制，图中相同的附图标记是指类似的元件，并且其中：
图1至8根据一例示性具体实施例，绘示用于就SG与EG栅极结构以相异宽度形成匹配的PFET/NFET间隔物的程序流程；
图9至21根据一例示性具体实施例，示意性绘示就NFET SG栅极结构、PFET SG结构、及PFET/NFET EG栅极结构形成具有不同氮化物间隔物宽度的FDSOI HKMG装置的程序流程；以及
图22至31根据一例示性具体实施例，示意性绘示就NFET SG栅极结构、PFET SG结构、及PFET/NFET EG栅极结构形成具有不同氮化物及/或氮化物/氧化物间隔物宽度的FDSOI HKMG装置的另一程序流程。
具体实施方式
在底下的说明中，为了解释，提出许多特定细节以便透彻理解例示性具体实施例。然而，应显而易知的是，没有这些特定细节或利用均等配置也可实践例示性具体实施例。在其它实例中，众所周知的结构及装置是以方块图形式来展示，为的是要避免不必要地混淆例示性具体实施例。另外，除非另有所指，本说明书及权利要求书中用来表达成分、反应条件等等之量、比率、及数值特性的所有数字都要了解为在所有实例中是以“约”一语来修饰。
本发明处理并解决以下目前面临的问题：在整合型RSD形成后，因漏极电压高，所以就效能与可靠度及间隔物崩溃方面，PFET及NFET SG与EG栅极结构会有不平衡的问题。本发明亦因应并解决FDSOI HKMG形成所带来氮化物/氧化物间隔物形成控制困难的当前问题。
根据本发明的具体实施例的方法包括在衬底上提供PFET SG与EG栅极结构及NFETSG与EG栅极结构，该PFET及NFET结构侧向隔开。第一保形氮化物层及氧化物衬垫是在该衬底上方形成，而第二保形氮化物层是在该PFET及NFET EG栅极结构的侧壁上形成。将该第一氮化物层及该氧化物衬垫的水平部分从该PFET SG与EG栅极结构上方移除，并且在各该PFET SG与EG栅极结构的对立侧上形成RSD结构。将该第一氮化物层及该氧化物衬垫的水平部分从该NFET SG与EG栅极结构上方移除，并且在各该NFET SG与EG栅极结构的对立侧上形成RSD结构。
单纯地通过描述所思及的最佳模式，还有其它态样、特征、以及技术功效经由下文的实施方式对于所属领域技术人员将显而易知，其中表示并且说明的是较佳具体实施例。本发明能够是其它及不同的具体实施例，而且其数项细节能够在各种明显方面进行修改。因此，图式及说明本质上要视为说明性，而不是作为限制性。
图1至8(截面图)是根据例示性具体实施例，绘示用于就SG与EG栅极结构以相异宽度形成匹配的PFET/NFET间隔物的程序流程。言及图1，在衬底109上形成PFET SG栅极结构101、PFET EG栅极结构103、NFET SG栅极结构105、以及NFET SG栅极结构107。各栅极结构包括氮化物栅极盖体110。氮化物层111是在衬底109上方以保形方式形成。氮化物层111举例而言，可由低K SiOCN、高温(630℃)iRadTM氮化物、或低K SiBCN所构成，厚度达4nm至8nm。氮化硅层111需要厚到足以防止外延硅在RSD区域中生长，但需要薄到足以最佳化此等源极/漏极区的重迭。还在衬底109上方形成氧化物衬垫113，其举例来说，是由未掺杂氧化物(UDOX)、iRadTM氧化物、或臭氧四乙氧基硅烷(TEOS)所构成。氧化物衬垫113在厚度方面，举例而言，可形成达3nm至6nm。氧化物衬垫113需要能够耐受后续所形成的氮化物层移除及牺牲硬掩模蚀刻。
其次，氮化物层115是在衬底109上方以保形方式形成。氮化物层115是由与氮化物层111相同的材料所构成，并且在厚度方面举例来说，可形成达3nm至15nm，端视技术(即多晶间距或鳍片间距)、可靠度限制条件、以及操作漏极电压而定。氮化物层115必须对程序中后续的牺牲硬掩模具有选择性。氮化物层115接着举例来说，使用四氟甲烷(CF4)通过反应性离子蚀刻(RIE)向下蚀刻至氧化物衬垫113而形成外部间隔物。光阻层117接着是分别在PFET及NFET EG栅极结构103及107上方形成，而氮化物层115是通过各向同性且对氧化物衬垫113具有选择性的蚀刻剂，分别从PFET及NFET SG栅极结构101及105移除，如图2所示。接着移除光阻层117。
言及图3，在衬底109上方形成牺牲硬掩模301。该硬掩模是由对氮化物层115具有选择性的材料所构成，例如：450℃至500℃的iRadTM氮化物或电浆增强型化学气相沉积(PECVD)氮化物。光阻层303接着是分别在NFET SG与EG栅极结构105与107上方形成。接着举例来说，使用热磷酸将PFET SG与EG栅极结构101与103上方的硬掩模301分别移除。硬掩模301举例而言，亦可使用氟代甲烷/氧化物(CH3F/O2)通过RIE来移除，用以各向同性蚀刻硬掩模301并于氧化物衬垫113上终止。
接着，例如使用CF4，通过RIE将氧化物衬垫113及氮化物层111向下各向异性蚀刻至衬底109及栅极盖体110，在PFET EG栅极结构103的对立侧上形成氮化物L形间隔物111’及氧化物L形间隔物113’，如图4所示。在最终PFET间隔物蚀刻之后，移除光阻层303。氧化物衬垫113亦可通过氢氟(HF)预清洁来移除，在PFET SG栅极结构101上留下氮化物L形间隔物111’。之后，通过外延生长来形成RSD结构401，而互补装置则受牺牲硬掩模301保护。L形间隔物111’及113’的水平表面的特定长度，例如2nm至6nm，将会取决于诸如外延先驱物气体、盐酸(HCL)流动、间隔物材料、及间隔物形状等因素的组合而定。视需要地，生长RSD结构401之后，薄氧化物衬垫(为便于说明而未图示)可举例来说，通过电浆氧化作用或通过经沉积的氧化物来形成，以在进一步处理步骤期间保护RSD结构401。若沉积薄氧化物衬垫，则应该尽量薄，例如：2nm至3nm，以防止NFET SG栅极结构105的最终L形间隔物变得太宽。
言及图5，将硬掩模层301从NFET SG与EG栅极结构105与107上方分别各向同性移除。接着，类似于图3的步骤，在衬底109上方形成新硬掩模层601，如图6所示。或者，在沉积硬掩模层601之前，硬掩模层301可分别留在NFET SG与EG栅极结构105与107上方。光阻层603接着是分别在PFET SG与EG栅极结构101与103上方形成，而NFET SG与EG栅极结构105与107上方的硬掩模层601(及硬掩模层301，若仍存在)则举例来说，使用热磷酸来各向同性移除，如图7所示。类似于硬掩模层301，硬掩模层601亦可举例而言，使用CH3F/O2通过RIE来移除。
例如使用CF4，通过RIE将氧化物衬垫113及氮化物层111向下各向异性蚀刻至衬底109及栅极盖体110，分别在NFET SG与EG栅极结构105与107的对立侧上形成氮化物L形间隔物111’及氧化物L形间隔物113’。在最终NFET间隔物蚀刻之后，移除光阻层603。再次地，氧化物衬垫113亦可通过在NFET SG栅极结构105上形成氮化物L形间隔物111’的HF预清洁来移除。接着，通过外延生长来形成RSD结构701，而互补装置则受牺牲硬掩模601保护。视需要地，生长RSD结构701之后，薄氧化物衬垫(为便于说明而未图示)可举例来说，再次地通过电浆氧化作用或通过经沉积的氧化物来形成，以在后续移除硬掩模层601期间保护RSD结构701。接着，举例来说，以热磷酸或使用CH3F/O2的RIE，将PFET SG与EG栅极结构101与103上方的硬掩模601分别各向同性移除，如图8所示。所以，氮化物间隔物111’及115就PFET及NFETSG与EG栅极结构具有匹配宽度。同样地，SG效能与EG可靠度要求达到平衡。
图9至21(截面图)根据一例示性具体实施例，示意性绘示就NFETSG栅极结构、PFETSG结构、及PFET/NFET EG栅极结构形成具有不同氮化物间隔物宽度的FDSOI HKMG装置的程序流程。言及图9，FDSOI衬底(为便于说明而未图示)上方分别形成NFET SG与EG栅极结构901与903、以及分别形成PFET SG与EG结构905与907。各栅极结构包括高K金属栅极909、硅层911、及氮化物栅极盖体912，而相较于SG侧上看不到的栅极氧化物，NFET及PFET EG结构903及907亦分别包括厚栅极氧化物层913。埋置型氧化物(BOX)层915及硅沟道层917或SiGe沟道层919是在FDSOI衬底上方、及诸BOX层浅沟槽隔离(STI)区921之间形成。氮化物层923接着是在衬底上方以保形方式形成。氮化物层923可通过分子层沉积(MLD)来形成，厚度举例来说，达56埃至之后，在氮化物层923上方以保形方式形成氧化物衬垫925，厚度举例而言，达至
言及图10，分别在NFET及PFET SG结构901及905上方形成光阻层1001，并且将氧化物衬垫925分别从NFET与PFET EG结构903与907、及衬底移除。氧化物衬垫925举例而言，可通过WINGTM或SiCoNiTM程序来移除。之后，移除光阻层1001。氮化物层1101接着通过MLD在衬底上方以保形方式形成，厚度达至如图11所示。接着，氮化物层1101的水平部分，举例而言，通过向下进行间隔物蚀刻至剩余氧化物衬垫925来移除，如图12所示。约略40％至80％的晶片面积在此时是被氧化物衬垫925包覆，因此，其作用为充分清楚的蚀刻终止信号。氮化物层923因蚀刻氮化物层1101所导致的损耗因而降到最小，例如：小于
进行软性清洁，然后分别在NFET及PFET EG栅极结构903及907上方形成光阻层1301，如图13所示。言及图14，通过对氧化物高度具有选择性的各向同性氮化物蚀刻，例如：二氟甲烷(CH2F2)或CH3F，分别将氮化物层1101的垂直部分从NFET及PFET SG栅极结构901及905移除。接着，将光阻层1301剥除，并且举例来说，通过湿或干蚀刻将氧化物衬垫925移除，如图15所示。晶圆表面于此步骤完全受氮化物层923保护，因此，应该不会因移除氧化物衬垫925而对晶圆造成损坏。
言及图16，光阻层1601是分别在NFET SG与EG栅极结构901与903上方形成。或者，光阻层1601可分别在PFET SG与EG栅极结构905与907上方形成。是否要先屏蔽NFET或PFET栅极结构是取决于各装置的所欲间隔物厚度，因为较晚阶段屏蔽产生的间隔物较厚。接着举例来说，氮化物层923的已曝露水平部分是通过RIE分别从PFET SG及EG结构905及907移除，如图17所示。之后，剥除光阻层1601，而外延预清洁程序是例如使用已稀释氢氟酸(DHF)/SiCoNiTM来进行，其将会移除一些BOX层915(为便于说明而未图示)。
接着，分别在相邻于PFET SG与EG结构905与907的SiGe层919及Si层917上、或分别在相邻于NFET SG与EG结构901与903的Si层917上，通过外延生长来形成RSD结构1801，端视先屏蔽的是哪些栅极结构而定，如图18所示。接着，氮化物层1901是在整个衬底(为便于说明而未图示)上方形成。接着，分别在PFET SG与EG栅极结构905与907上方、或分别在NFETSG与EG栅极结构901与903上方形成光阻层1903，端视先屏蔽的是哪些栅极结构而定。接着，举例来说，氮化物层1901及923的水平部分是通过RIE分别从NFET SG及EG结构901及903移除。
言及图20，类似于图17，剥除光阻层1903，而外延预清洁程序是例如使用DHF/SiCoNiTM来进行，再次地移除一些BOX层915(为便于说明而未图示)。接着分别在相邻于NFETSG与EG结构901与903的Si层917上、或分别在相邻于PFET SG与EG结构905与907的SiGe层919及Si层917上，通过外延生长来形成RSD结构2001，端视先屏蔽的是哪些栅极结构而定。其次，移除栅极盖体912，并且举例来说，使用热磷酸，通过RIE或通过适当的湿蚀刻，将氮化物层923、1101及1901向下蚀刻至硅层911的上表面，如图21所示。接着，氮化物层1901是从RSD结构1801或2001终仍剩余处被移除。氮化物层923、1101、及1901的移除亦可用视需要的有机平坦化层(OPL)加上回蚀保护来进行。之后，进行间隔物氮化物沉积、蚀刻、及硅化(为便于说明而未图示)。
图22至31(截面图)根据一例示性具体实施例，示意性绘示就NFETSG栅极结构、PFET SG结构、及PFET/NFET EG栅极结构形成具有不同氮化物及/或氮化物/氧化物间隔物宽度的FDSOI HKMG装置的另一程序流程。言及图22，类似于图9，FDSOI衬底(为便于说明而未图示)上方分别形成NFET SG与EG栅极结构2201与2203、以及分别形成PFET SG与EG结构2205与2207。各栅极结构包括高K金属栅极2209、硅层2211、及栅极盖体2212，而相较于SG侧上看不到的栅极氧化物，NFET及PFETEG结构2203及2207亦分别包括厚栅极氧化物层2213。BOX层2215及Si沟道层2217或SiGe沟道层2219是在FDSOI衬底上方形成，而STI区2221是在BOX层2215之间形成。氮化物层2223接着是在衬底上方以保形方式形成。氮化物层2223可通过MLD来形成，厚度举例来说，达56埃至之后，在氮化物层2223上方以保形方式形成氧化物衬垫2225，厚度举例而言，达至
接着，氮化物层2227是在衬底上方通过MLD以保形方式形成，厚度达至如图23所示。氮化物层2227的水平部分是接着举例而言，通过向下进行间隔物蚀刻至氧化物衬垫2225来移除，留下触碰不到的氮化物层2223，如图24所示。之后，例如使用冷SC1溶液来进行软性清洁。
言及图25，光阻层2501是分别在NFET与PFET EG栅极结构2203与2207上方形成。接着，举例而言，通过对氧化物高度具有选择性的各向同性氮化物蚀刻，例如：CH2F2或CH3F，分别将氮化物层2227的垂直部分从NFET及PFET SG栅极结构2201及2205移除。接着，将光阻层2501剥除，并且举例来说，通过湿或干蚀刻将曝露的氧化物衬垫2225移除，仅分别在NFET及PFET EG栅极结构2203及2207的氮化物层2223与2227之间留下氧化物衬垫2225，如图26所示。
图27至31大体上遵循如同图16至21的程序流程；然而，产生的装置需要的屏蔽少一个，而且还分别在NFET及PFET EG栅极结构2203及2207中包括小L形氧化物衬垫2225。言及图27，光阻层2701是分别在NFET SG与EG栅极结构2201与2203上方形成。或者，光阻层2701可分别在PFET SG与EG栅极结构2205与2207上方形成。是否要先屏蔽NFET或PFET栅极结构是取决于各装置的所欲间隔物厚度，因为较晚阶段屏蔽产生的间隔物较厚。接着举例来说，氮化物层2223的水平部分是通过RIE分别从PFET SG及EG结构2205及2207移除。之后，剥除光阻层2701，而外延预清洁程序是例如使用DHF/SiCoNiTM来进行，其将会移除一些BOX层2215(为便于说明而未图示)。
接着，分别在相邻于PFET SG与EG结构2205与2207的SiGe层2219及Si层2217上、或分别在相邻于NFET SG与EG结构2201与2203的Si层2217上，通过外延生长来形成RSD结构2801，端视先屏蔽的是哪些栅极结构而定，如图28所示。言及图29，氮化物层2901是在整个衬底(为便于说明而未图示)上方以保形方式形成。接着，分别在PFET SG与EG栅极结构2205与2207上方、或分别在NFET SG与EG栅极结构2201与2203上方形成光阻层2903，端视图27中先屏蔽的是哪些栅极结构而定。接着举例来说，通过RIE移除氮化物层2901及2223的已曝露水平部分。
言及图30，剥除光阻层2903，而外延预清洁程序是再次地例如使用DHF/SiCoNiTM来进行，移除一些BOX层2215(为便于说明而未图示)。接着分别在相邻于NFET SG与EG结构2201与2203的Si层2217上、或分别在相邻于PFET SG与EG结构2205与2207的SiGe层2219及Si层2217上，通过外延生长来形成RSD结构3001，端视图27中先屏蔽的是哪些栅极结构而定。
接着，移除栅极盖体2212，并且举例来说，使用热磷酸，通过RIE或通过适当的湿蚀刻，将氮化物层2223、2227及2901、以及氧化物衬垫2225向下蚀刻至硅层2211的上表面，如图31所示。接着，氮化物层2901是从RSD结构2801或3001中仍剩余处被移除。氮化物层2223、2227、及2901、以及氧化物衬垫2225的移除亦可用视需要的OPL加上回蚀保护来进行。之后，进行间隔物氮化物沉积、蚀刻、及硅化(为便于说明而未图示)。
本发明的具体实施例可达到数种技术功效，包括另外需要的屏蔽层仅一个(重复使用现有的EG屏蔽)；形成更厚的NFET及PFET EG间隔物以提升可靠度但未牺牲SG效能；形成匹配的PFET及NFET间隔物；以及形成因L形间隔物而具有受刻面RSD(faceted RSD)的SG装置，使栅极与RSD间电容降低，并且使寄生电容(Ceff)改善，其直接导致交流效能提升。本发明的具体实施例亦可达到数种另外的技术功效，包括就FDSOI上的SG NFET、SG PFET、及PFET/NFET EG栅极结构、以及所有具有完全氮化物间隔物的栅极结构，形成不同且独立的间隔物厚度。举例而言，本发明的具体实施例在各种工业应用中享有实用性，如：微处理器、智慧型手机、行动电话、蜂巢式手机、机上盒、DVD录影机与播放器、汽车导航、打印机与周边装置、网络连结与电信设备、游戏系统、以及数字相机。本发明因此在FDSOI装置及/或任何需要RSD外延的任何技术中享有产业利用性。
在前述说明中，本发明是参照其具体例示性具体实施例来说明。然而，明显的是，可对其实施各种修改和变更而不脱离本发明较广的精神与范畴，如权利要求书所提。本说明书及图式从而要视为说明性而非作为限制性。应了解的是，本发明能够使用各种其它组合及具体实施例，并且如本文中所表达，能够在本发明概念的范畴内作任何变更或修改。

Claims (20)

1.一种方法，包含：
在衬底上提供p型场效应晶体管(PFET)核心装置(SG)与I/O装置(EG)栅极结构、n型场效应晶体管(NFET)SG与EG栅极结构，该PFET及NFET结构侧向隔开；
在该衬底上方形成第一保形氮化物层；
在该衬底上方形成氧化物衬垫；
在该PFET及NFET EG栅极结构的侧壁上形成第二保形氮化物层；
移除该第一氮化物层及该氧化物衬垫在该PFET SG与EG栅极结构及衬底上方的水平部分；
在各该PFET SG与EG栅极结构的对立侧上形成隆起源极/漏极(RSD)结构；
移除该第一氮化物层及该氧化物衬垫在该NFET SG与EG栅极结构及衬底上方的水平部分；以及
在各该NFET SG与EG栅极结构的对立侧上形成RSD结构。
2.如权利要求1所述的方法，其包含在该PFET及NFET EG栅极结构的该侧壁上形成第二保形氮化物层是通过下列步骤：
在该衬底上方形成该第二保形氮化物层；
将该第二保形氮化物层向下平坦化至该氧化物衬垫；
在该PFET及NFET EG栅极结构上方形成光阻层；
将该第二保形氮化物层从该PFET及NFET SG栅极结构移除；以及
移除该光阻层。
3.如权利要求1所述的方法，其包含移除该第一氮化物层及该氧化物衬垫在该PFET SG与EG栅极结构及衬底上方的该水平部分是通过下列步骤：
在该衬底上方形成硬掩模层；
在该NFET SG与EG栅极结构上方形成光阻层；
移除该PFET SG与EG栅极结构上方的该硬掩模层；
将该第一保形氮化物层及该氧化物衬垫向下蚀刻至该衬底；以及
移除该光阻层。
4.如权利要求3所述的方法，其中，该蚀刻形成位在各该PFET SG与EG栅极结构的对立侧上的L形第一保形氮化物层间隔物、及位在该PFET EG栅极结构的对立侧上的L形氧化物衬垫间隔物。
5.如权利要求1所述的方法，其包含移除该第一氮化物层及该氧化物衬垫在该NFET SG与EG栅极结构及衬底上方的该水平部分是通过下列步骤：
在该衬底上方形成硬掩模层；
在该PFET SG与EG栅极结构上方形成光阻层；
移除该NFET SG与EG栅极结构上方的该硬掩模层；
将该第一保形氮化物层及该氧化物衬垫向下蚀刻至该衬底；
移除该光阻层；以及
移除该PFET SG与EG栅极结构上方的该硬掩模层。
6.如权利要求5所述的方法，其中，该蚀刻形成位在各该NFET SG与EG栅极结构的对立侧上的L形第一保形氮化物层间隔物、及位在该NFET EG栅极结构的对立侧上的L形氧化物衬垫间隔物。
7.如权利要求1所述的方法，其中，各该PFET及NFET SG栅极结构的该对立侧上所形成的该RSD结构受到刻面。
8.一种装置，包含：
衬底上所形成的p型场效应晶体管(PFET)核心装置(SG)与I/O装置(EG)栅极结构、n型场效应晶体管(NFET)SG与EG栅极结构，该PFET及NFET结构侧向隔开；
该衬底上且相邻于各该PFET及NFET SG与EG栅极结构的侧壁所形成的一对L形氮化物间隔物；
该PFET及NFET EG栅极结构的各L形氮化物间隔物上且与各该L形氮化物间隔物相邻所形成的L形氧化物间隔物；
各L形氧化物间隔物上且与各该L形氧化物间隔物相邻所形成的氮化物间隔物；
各该PFET及NFET SG栅极结构的对立侧上所形成的刻面隆起源极/漏极(RSD)结构；以及
各该PFET及NFET EG栅极结构的对立侧上所形成的RSD结构。
9.如权利要求8所述的装置，其中，各L形氮化物间隔物及各氮化物间隔物是由硅氧碳氮化物(SiOCN)、高温iRadTM氮化物、或硅硼碳氮化物(SiBCN)所构成。
10.一种方法，包含：
在完全耗尽型绝缘体上硅(FDSOI)衬底上提供n型场效应晶体管(NFET)核心装置(SG)与I/O装置(EG)栅极结构、及p型场效应晶体管(PFET)SG与EG栅极结构，该SG与EG结构侧向隔开，并且各包括栅极及栅极覆盖层；
在该NFET及PFET SG与EG栅极结构及该衬底上方形成保形第一氮化物层；
在该NFET及PFET SG与EG栅极结构及衬底上方形成氧化物衬垫；
在该NFET及PFET SG与EG结构及衬底上方形成第二保形氮化物层；
移除该第二氮化物层的水平部分；
屏蔽该NFET及PFET EG栅极结构；
移除该第二氮化物层相邻于该NFET及PFET SG结构及已曝露氮化物衬垫的垂直部分；
屏蔽NFET或PFET EG与SG栅极结构；
移除该第一氮化物层的水平部分；
分别在相邻于该PFET或NFET SG与EG结构的该衬底上形成隆起源极/漏极(RSD)结构；
在该整个衬底上方形成第三氮化物层；
分别屏蔽PFET或NFET SG与EG栅极结构；
移除该第三氮化物层的水平部分；
分别在该PFET或NFET SG与EG栅极结构的对立侧上形成RSD结构；以及
将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面。
11.如权利要求10所述的方法，其包含：
在形成该氧化物衬垫之后，屏蔽该NFET及PFET SG结构；
从该NFET及PFET EG栅极结构移除该氧化物衬垫；以及
移除该屏蔽。
12.如权利要求10所述的方法，其包含移除该第二氮化物层的该水平部分是通过下列步骤：
将该第二氮化物层向下蚀刻至该氧化物衬垫。
13.如权利要求10所述的方法，其包含：
在屏蔽该NFET及PFET SG与EG栅极结构前，先移除该NFET及PFETEG栅极结构的该屏蔽。
14.如权利要求10所述的方法，其包含在形成相邻于该PFET或NFET SG与EG结构的该RSD结构前，先移除该NFET及PFET SG与EG栅极结构的该屏蔽。
15.如权利要求10所述的方法，其包含在将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面前，先移除该PFET或NFET SG与EG栅极结构的该屏蔽。
16.如权利要求15所述的方法，其包含：
从该NFET或PFET EG与SG栅极结构的该对立侧上的该RSD结构上方移除该第三氮化物层；以及
将该第一、第二、及第三氮化物层及该栅极覆盖层或该第一、第二、及第三氮化物层、该栅极覆盖层、及该氧化物衬垫向下移除至该栅极的上表面后，进行间隔物氮化物沉积、蚀刻、及硅化。
17.一种装置，其包含：
完全耗尽型绝缘体上硅(FDSOI)衬底；
p型场效应晶体管(PFET)核心装置(SG)与I/O装置(EG)栅极结构、及n型场效应晶体管(NFET)SG与EG栅极结构，形成在该FDSOI衬底上，该SG与EG结构侧向隔开；
双氮化物层间隔物，形成在该NFET及PFET SG栅极结构的各侧壁上；
三重氮化物层间隔物，形成在该NFET及PFET EG栅极结构的各侧壁上；以及
隆起源极/漏极(RSD)结构，形成在该NFET及PFET SG与EG栅极结构的对立侧上。
18.如权利要求17所述的装置，其中，该双氮化物层间隔物比该三重氮化物层间隔物更薄。
19.如权利要求17所述的装置，其中，该PFET SG栅极结构是在硅锗(SiGe)层上方形成，而该PFET EG及NFET SG与EG结构是在硅层上方形成。
20.如权利要求17所述的装置，其中，氧化物层是在该NFET及PFETEG结构的第一及第二氮化物层之间形成。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10756184B2 (en) * 2018-11-05 2020-08-25 Globalfoundries Inc. Faceted epitaxial source/drain regions
US11476415B2 (en) * 2018-11-30 2022-10-18 International Business Machines Corporation Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features
US10777642B2 (en) 2019-01-30 2020-09-15 Globalfoundries Inc. Formation of enhanced faceted raised source/drain epi material for transistor devices
US10825897B2 (en) 2019-01-30 2020-11-03 Globalfoundries Inc. Formation of enhanced faceted raised source/drain EPI material for transistor devices
KR20200113130A (ko) 2019-03-22 2020-10-06 삼성전자주식회사 반도체 소자
US11205647B2 (en) * 2019-06-28 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11127860B2 (en) 2019-09-12 2021-09-21 Globalfoundries U.S. Inc. Extended-drain field-effect transistors including a floating gate
GB2591787A (en) * 2020-02-06 2021-08-11 X Fab France Sas Methods for forming multiple gate sidewall spacer widths
US11315949B2 (en) 2020-09-15 2022-04-26 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Charge-trapping sidewall spacer-type non-volatile memory device and method
US11817479B2 (en) 2021-09-29 2023-11-14 Globalfoundries U.S. Inc. Transistor with air gap under raised source/drain region in bulk semiconductor substrate
US11677000B2 (en) 2021-10-07 2023-06-13 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer under trench isolations adjacent source/drain regions

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060286729A1 (en) * 2005-06-21 2006-12-21 Jack Kavalieros Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
US20070015324A1 (en) * 2005-07-12 2007-01-18 Promos Technologies Inc. Fabrication method for single and dual gate spacers on a semiconductor device
US20130011975A1 (en) * 2010-04-14 2013-01-10 International Business Machines Corporation Raised source/drain structure for enhanced strain coupling from stress liner

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652332B2 (en) * 2007-08-10 2010-01-26 International Business Machines Corporation Extremely-thin silicon-on-insulator transistor with raised source/drain
US8482076B2 (en) * 2009-09-16 2013-07-09 International Business Machines Corporation Method and structure for differential silicide and recessed or raised source/drain to improve field effect transistor
TW201206630A (en) * 2010-06-30 2012-02-16 Applied Materials Inc Endpoint control during chemical mechanical polishing by detecting interface between different layers through selectivity change
US8647952B2 (en) * 2010-12-21 2014-02-11 Globalfoundries Inc. Encapsulation of closely spaced gate electrode structures
DE102011004322B4 (de) * 2011-02-17 2012-12-06 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Herstellung eines Halbleiterbauelements mit selbstjustierten Kontaktelementen und einer Austauschgateelektrodenstruktur
KR102050779B1 (ko) * 2013-06-13 2019-12-02 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
US9245903B2 (en) * 2014-04-11 2016-01-26 International Business Machines Corporation High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process
US9385232B2 (en) * 2014-10-23 2016-07-05 Globalfoundries Inc. FD devices in advanced semiconductor techniques
KR102320820B1 (ko) * 2015-02-24 2021-11-02 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060286729A1 (en) * 2005-06-21 2006-12-21 Jack Kavalieros Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
US20070015324A1 (en) * 2005-07-12 2007-01-18 Promos Technologies Inc. Fabrication method for single and dual gate spacers on a semiconductor device
US20130011975A1 (en) * 2010-04-14 2013-01-10 International Business Machines Corporation Raised source/drain structure for enhanced strain coupling from stress liner

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