CN108711441A - A kind of storage organization that anti-SEU is reinforced - Google Patents
A kind of storage organization that anti-SEU is reinforced Download PDFInfo
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- CN108711441A CN108711441A CN201810489576.7A CN201810489576A CN108711441A CN 108711441 A CN108711441 A CN 108711441A CN 201810489576 A CN201810489576 A CN 201810489576A CN 108711441 A CN108711441 A CN 108711441A
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- Prior art keywords
- memory node
- branch
- nmos tube
- tube
- grid
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention discloses a kind of storage organizations that anti-SEU is reinforced, memory node D is set in the first branch, memory node A is set in the second branch, memory node B is set to third branch road, memory node C is set to the 4th road, the first branch is connected with the second branch and the 4th branch respectively by the memory node D, the second branch is connected with the first branch and third branch respectively by memory node A, third branch is connected with the second branch and the 4th branch respectively by memory node B, 4th branch stores point C by section and is connected respectively with the first branch and third branch.The present invention increases two NMOS tubes of grounded-grid on the basis of Quatro is designed, influence degrees of the sensitive nodes A and B by single particle effect is reduced using electric resistance partial pressure principle, increase the performance of anti-SEU, in addition corresponding peripheral circuit, can be used as SRAM or trigger to use.
Description
Technical field
The present invention relates to a kind of storage organizations that anti-SEU is reinforced, and belong to latch anti-single particle overturning (SEU) Design of Reinforcement
Technical field.
Background technology
The residing outer space of spacecraft operation, there is extremely severe radiation environments.Chip in space by radiating ring
The influence in border easily generates single particle effect and causes chip memory（Such as latch）Data overturn, this mistake
It is referred to as single-particle inversion（SEU）.Continue forward development with modern production process, radiation environment for deep-submicron,
The influence of the storage unit circuit of nanometer technology size is increasing, causes circuit more and more sensitive to single particle effect.
The basic structure of conventional memory cell is a pair of back-to-back phase inverter, is connected with each other, is had by positive feedback
Two complementary memory node A and A '.Assuming that node A logic levels are 0, then A ' logic levels are 1.If node A ' is by beating
It hits and is turned into 0, then node A is possible to therefore be turned into 1, and mistake occurs to the logic level values of two nodes of A and A '.
With the fast development of China's aerospace, urgent skill is proposed to high stability, the chip for capableing of Flouride-resistani acid phesphatase
Art demand.Moreover, commercial product also proposed higher finger in the application of ground key to the performance of anti-single particle effect
Mark requires.
Invention content
In order to overcome the deficiencies of existing technologies, the present invention proposes a kind of storage organization that anti-SEU is reinforced, and is tied based on Quatro
Structure, the transistor that two are turned off（That is resistance）Be placed on Quatro structures two draw high on path, reduce node A and B
Sensitivity, it is compact-sized, save area.
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
A kind of storage organization that anti-SEU is reinforced, including the first branch, the second branch, third branch, the 4th branch, memory node
D, memory node A, memory node B, memory node C, overturning reference mode AU, overturning reference mode BU, the first branch packet
PMOS tube P1 and NMOS tube N1 are included, the source electrode of the PMOS tube P1 is connected with power supply, and the drain electrode of the PMOS tube P1 connects NMOS
The drain electrode of pipe N1 is grounded in memory node D, the source electrode of the NMOS tube N1, grid and the memory node C phases of the PMOS tube P1
Even, the grid of the NMOS tube N1 is connected with memory node A；The second branch include PMOS tube P2, NMOS tube N5,
NMOS tube N2, the source electrode of the PMOS tube P2 are connected with power supply, and the source electrode of the drain electrode connection NMOS tube N5 of PMOS tube P2 is in turning over
Turn reference mode AU, the drain electrode of NMOS tube N5 is connected in memory node A with the drain electrode of NMOS tube N2, and the source electrode of NMOS tube N2 connects
The grid on ground, the PMOS tube P2 is connected with memory node D, the grounded-grid of the NMOS tube N5, the grid of the NMOS tube N2
Pole is connected with memory node B；The third branch includes PMOS tube P3, NMOS tube N6 and NMOS tube N3, the PMOS tube P3's
Source electrode is connected with power supply, and the drain electrode of the PMOS tube P3 and the source electrode of NMOS tube N6 are connected to overturning reference mode BU, described
The source electrode that the drain electrode of NMOS tube N6 is connected to memory node B, the NMOS tube N3 with the drain electrode of NMOS tube N3 is grounded, described
The grid of PMOS tube P3 is connected with memory node C, the grounded-grid of the NMOS tube N6, the grid of the NMOS tube N3 and storage
Node A is connected；4th branch includes PMOS tube P4 and NMOS tube N4, and the source electrode of the PMOS tube P4 meets power supply, PMOS
The drain electrode of the drain electrode connection NMOS tube N4 of pipe P4 is in memory node C, and the source electrode of NMOS tube N4 is grounded, the grid of the PMOS tube P4
Pole is connected with memory node D, and the grid of the NMOS tube N4 is connected with memory node B.
Advantageous effect：The present invention provides a kind of storage organization that anti-SEU is reinforced, and is increased on the basis of Quatro is designed
Two NMOS tubes of grounded-grid, reduce sensitive nodes A and B using electric resistance partial pressure principle is influenced journey by single particle effect
Degree, increases the performance of anti-SEU.In addition corresponding peripheral circuit, can be used as SRAM or trigger to use.
Description of the drawings
Fig. 1 is the integrated circuit connection structure diagram of the present invention.
Fig. 2 is the peripheral front end circuit in the present invention.
Fig. 3 is the first SRAM read/write circuits of the present invention.
Fig. 4 is the 2nd SRAM read/write circuits of the present invention.
Specific implementation mode
In order to make those skilled in the art better understand the technical solutions in the application, below to the embodiment of the present application
In technical solution be clearly and completely described, it is clear that described embodiments are only a part of embodiments of the present application,
Instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art are not making creative labor
The every other embodiment obtained under the premise of dynamic, shall fall within the protection scope of the present application.
As shown in Figure 1, a kind of storage organization that anti-SEU is reinforced, including the first branch, the second branch, third branch, the 4th
Branch, memory node D, memory node A, memory node B, memory node C, overturning reference mode AU, overturning reference mode BU, institute
It includes PMOS tube P1 and NMOS tube N1 to state the first branch, and the source electrode of the PMOS tube P1 is connected with power supply, the PMOS tube P1's
The drain electrode of drain electrode connection NMOS tube N1 is grounded in memory node D, the source electrode of the NMOS tube N1, the grid of the PMOS tube P1
It is connected with memory node C, the grid of the NMOS tube N1 is connected with memory node A；The second branch includes PMOS tube
P2, NMOS tube N5, NMOS tube N2, the source electrode of the PMOS tube P2 are connected with power supply, and the drain electrode of PMOS tube P2 connects NMOS tube
The source electrode of N5 is connected in memory node A, NMOS in overturning reference mode AU, the drain electrode of NMOS tube N5 with the drain electrode of NMOS tube N2
The source electrode of pipe N2 is grounded, and the grid of the PMOS tube P2 is connected with memory node D, and the grounded-grid of the NMOS tube N5 is described
The grid of NMOS tube N2 is connected with memory node B；The third branch includes PMOS tube P3, NMOS tube N6 and NMOS tube N3, institute
The source electrode for stating PMOS tube P3 is connected with power supply, and the drain electrode of the PMOS tube P3 is connected to overturning reference node with the source electrode of NMOS tube N6
Point BU, the drain electrode of the NMOS tube N6 are connected to memory node B with the drain electrode of NMOS tube N3, and the source electrode of the NMOS tube N3 connects
The grid on ground, the PMOS tube P3 is connected with memory node C, the grounded-grid of the NMOS tube N6, the grid of the NMOS tube N3
Pole is connected with memory node A；4th branch includes PMOS tube P4 and NMOS tube N4, and the source electrode of the PMOS tube P4 connects electricity
Source, the drain electrode of the drain electrode connection NMOS tube N4 of PMOS tube P4 is in memory node C, and the source electrode of NMOS tube N4 is grounded, the PMOS
The grid of pipe P4 is connected with memory node D, and the grid of the NMOS tube N4 is connected with memory node B.
The present invention can be used as latch by the peripheral front end circuit of addition and use, peripheral front end circuit such as Fig. 2 of addition
It is shown.Prefix logic circuit includes the first logic circuit and the second logic circuit.First logic circuit includes PMOS tube
P01, PMOS tube P02, NMOS tube N01, NMOS tube N02, the PMOS tube P01 source electrode connect power supply, the drain electrode of PMOS tube P01 connects
The source electrode of PMOS tube P02 is connect, the drain electrode of PMOS tube P02 connects the drain electrode of NMOS tube N01 in the data output end of the first logic circuit
ID1, the source electrode of NMOS tube N01 meet the drain electrode of NMOS tube N02, the source electrode ground connection of NMOS tube N02, the PMOS tube P01 and NMOS
The grid of pipe N02 is connected the data input pin D1 as the first logic circuit, and the grid of the PMOS tube P02 is as clock
The input terminal of clock, the input terminal of the grid of NMOS tube N01 as clock clock '；Second logic circuit includes PMOS
Pipe P03, PMOS tube P04, NMOS tube N03 and NMOS tube N04, the PMOS tube P03 source electrode connect power supply, the leakage of PMOS tube P03
Pole connects the source electrode of P04 pipes, and the drain electrode of PMOS tube P04 meets data output end iD2 of the drain electrode in the second logic circuit of NMOS tube,
The source electrode of NMOS tube N03 connects the drain electrode of N04 pipes, the source electrode ground connection of NMOS tube N04, the grid of the PMOS tube P03 and PMOS tube N04
Pole is connected input of the grid as the data input pin D2, the PMOS tube P04 of the second logic circuit as clock clock
End, the input terminal of the grid of NMOS tube N03 as clock clock '.The input terminal D1 connection data of first logic circuit
Data, clock input clock and clock ', the output end iD1 connections memory node A of first logic circuit；It is described
The input terminal D2 of second logic circuit connects the inverse value of data data, clock input clock and clock ', the second logic electricity
The output end iD2 on road meets the memory node B.
The present invention is used as SRAM and is used by the way that the first SRAM read/write circuits and the 2nd SRAM read/write circuits is added, and Fig. 3 is the
The circuit connection diagram of one SRAM read/write circuits, Fig. 4 are the circuit connection diagrams of the 2nd SRAM read/write circuits.Wherein, institute
It includes NMOS tube N9, NMOS tube N10, wordline WL1, bit line BL1, reverse phase bit line BLB1 to state the first SRAM read/write circuits, described
The grid of the grid of NMOS tube N9 and the NMOS tube N10 are connected with the wordline WL1 respectively, the source electrode of the NMOS tube N9
It is connected with the reverse phase bit line BLB1, the source electrode of the NMOS tube N10 is connected with the bit line BL1, the NMOS tube N9
Drain electrode be connected with the memory node B, the drain electrode of the NMOS tube N10 is connected with the memory node C；Described second
SRAM read/write circuits include NMOS tube N11, NMOS tube N12, wordline WL2, bit line BL2, reverse phase bit line BLB2, the MMOS pipes
The grid of the grid of N11 and the NMOS tube N12 are connected with the wordline WL2 respectively, the source electrode of the NMOS tube N11 and institute
It states reverse phase bit line BLB2 to be connected, the source electrode of the NMOS tube N12 is connected with the bit line BL2, the leakage of the NMOS tube N11
Pole is connected with the memory node D, and the drain electrode of the NMOS tube N12 is connected with the memory node A.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Two kinds of modifications of these embodiments will be apparent to those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (1)
1. a kind of storage organization that anti-SEU is reinforced, which is characterized in that including the first branch, the second branch, third branch, the 4th
Branch, memory node D, memory node A, memory node B, memory node C, overturning reference mode AU, overturning reference mode BU, institute
It includes PMOS tube P1 and NMOS tube N1 to state the first branch, and the source electrode of the PMOS tube P1 is connected with power supply, the PMOS tube P1's
The drain electrode of drain electrode connection NMOS tube N1 is grounded in memory node D, the source electrode of the NMOS tube N1, the grid of the PMOS tube P1
It is connected with memory node C, the grid of the NMOS tube N1 is connected with memory node A；The second branch includes PMOS tube
P2, NMOS tube N5, NMOS tube N2, the source electrode of the PMOS tube P2 are connected with power supply, and the drain electrode of PMOS tube P2 connects NMOS tube
The source electrode of N5 is connected in memory node A, NMOS in overturning reference mode AU, the drain electrode of NMOS tube N5 with the drain electrode of NMOS tube N2
The source electrode of pipe N2 is grounded, and the grid of the PMOS tube P2 is connected with memory node D, and the grounded-grid of the NMOS tube N5 is described
The grid of NMOS tube N2 is connected with memory node B；The third branch includes PMOS tube P3, NMOS tube N6 and NMOS tube N3, institute
The source electrode for stating PMOS tube P3 is connected with power supply, and the drain electrode of the PMOS tube P3 is connected to overturning reference node with the source electrode of NMOS tube N6
Point BU, the drain electrode of the NMOS tube N6 are connected to memory node B with the drain electrode of NMOS tube N3, and the source electrode of the NMOS tube N3 connects
The grid on ground, the PMOS tube P3 is connected with memory node C, the grounded-grid of the NMOS tube N6, the grid of the NMOS tube N3
Pole is connected with memory node A；4th branch includes PMOS tube P4 and NMOS tube N4, and the source electrode of the PMOS tube P4 connects electricity
Source, the drain electrode of the drain electrode connection NMOS tube N4 of PMOS tube P4 is in memory node C, and the source electrode of NMOS tube N4 is grounded, the PMOS
The grid of pipe P4 is connected with memory node D, and the grid of the NMOS tube N4 is connected with memory node B.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810489576.7A CN108711441A (en) | 2018-05-21 | 2018-05-21 | A kind of storage organization that anti-SEU is reinforced |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810489576.7A CN108711441A (en) | 2018-05-21 | 2018-05-21 | A kind of storage organization that anti-SEU is reinforced |
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| CN108711441A true CN108711441A (en) | 2018-10-26 |
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| CN201810489576.7A Pending CN108711441A (en) | 2018-05-21 | 2018-05-21 | A kind of storage organization that anti-SEU is reinforced |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510076B1 (en) * | 2002-02-12 | 2003-01-21 | Pmc-Sierra, Inc. | Variable read/write margin high-performance soft-error tolerant SRAM bit cell |
| US20080205112A1 (en) * | 2007-02-23 | 2008-08-28 | Lawson David C | Apparatus for Hardening a Static Random Access Memory Cell from Single Event Upsets |
| CN102122950A (en) * | 2011-01-10 | 2011-07-13 | 深圳市国微电子股份有限公司 | High-speed low-power consumption latch device capable of resisting SEU (single event upset) |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN106059565A (en) * | 2016-06-21 | 2016-10-26 | 河海大学常州校区 | Novel SR latch resisting single event upset |
| CN106328195A (en) * | 2016-08-19 | 2017-01-11 | 西安空间无线电技术研究所 | Single event upset resistant SRAM (static random access memory) |
| US20180025774A1 (en) * | 2015-03-27 | 2018-01-25 | Institute Of Automation Chinese Academy Of Sciences | Memory Cell of Static Random Access Memory Based on Resistance Hardening |
-
2018
- 2018-05-21 CN CN201810489576.7A patent/CN108711441A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510076B1 (en) * | 2002-02-12 | 2003-01-21 | Pmc-Sierra, Inc. | Variable read/write margin high-performance soft-error tolerant SRAM bit cell |
| US20080205112A1 (en) * | 2007-02-23 | 2008-08-28 | Lawson David C | Apparatus for Hardening a Static Random Access Memory Cell from Single Event Upsets |
| CN102122950A (en) * | 2011-01-10 | 2011-07-13 | 深圳市国微电子股份有限公司 | High-speed low-power consumption latch device capable of resisting SEU (single event upset) |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| US20180025774A1 (en) * | 2015-03-27 | 2018-01-25 | Institute Of Automation Chinese Academy Of Sciences | Memory Cell of Static Random Access Memory Based on Resistance Hardening |
| CN106059565A (en) * | 2016-06-21 | 2016-10-26 | 河海大学常州校区 | Novel SR latch resisting single event upset |
| CN106328195A (en) * | 2016-08-19 | 2017-01-11 | 西安空间无线电技术研究所 | Single event upset resistant SRAM (static random access memory) |
Non-Patent Citations (2)
| Title |
|---|
| （美）毕查德·拉扎维著；陈贵灿，程军，张瑞智等译: "《模拟CMOS集成电路设计（简编版）》", 30 April 2013, 西安交通大学出版社 * |
| JAHINUZZAMAN S M，RENNIE D J，SACHDEV M: "《A softerror tolerant 10T SRAM bit-cell with differential read capability》", 《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 * |
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