CN108666309B - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN108666309B CN108666309B CN201810183015.4A CN201810183015A CN108666309B CN 108666309 B CN108666309 B CN 108666309B CN 201810183015 A CN201810183015 A CN 201810183015A CN 108666309 B CN108666309 B CN 108666309B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 219
- 239000010410 layer Substances 0.000 claims description 164
- 239000011229 interlayer Substances 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 33
- 238000002955 isolation Methods 0.000 claims description 24
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- 238000005859 coupling reaction Methods 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 abstract description 11
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- YAFQFNOUYXZVPZ-UHFFFAOYSA-N liproxstatin-1 Chemical compound ClC1=CC=CC(CNC=2C3(CCNCC3)NC3=CC=CC=C3N=2)=C1 YAFQFNOUYXZVPZ-UHFFFAOYSA-N 0.000 description 23
- 101150077696 lip-1 gene Proteins 0.000 description 21
- 101100074846 Caenorhabditis elegans lin-2 gene Proteins 0.000 description 12
- 101100497386 Mus musculus Cask gene Proteins 0.000 description 12
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
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- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
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- 238000012827 research and development Methods 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
一种具有FINFET的半导体器件,其提供了增强的可靠性。该半导体器件包括第一N沟道FET和第二N沟道FET,它们串联耦合在用于2输入NAND电路的输出的布线和用于第二电源电位的布线之间。在平面图中,局部布线设置在沿第二方向延伸的第一N沟道FET的第一N栅电极和第二N沟道FET的第二N栅电极之间,并且与沿第一方向延伸的半导体层交叉且沿第二方向延伸。局部布线耦合至用于热量消散的布线。
Description
相关申请的交叉参考
于2017年3月27日提交的日本专利申请第2017-061804号、包括说明书、附图和摘要的公开结合于此作为参考。
技术领域
本发明涉及半导体器件,更具体地,涉及可用于具有FINFET的半导体器件的技术。
背景技术
近年来,在使用硅的LSI(大规模集成)领域中,发展趋势是朝向作为LSI组成元件的MISFET(金属绝缘体半导体场效应晶体管)的尺寸的减小,尤其在栅电极的栅极长度方面。根据比例定律来进行减小MISFET尺寸的努力。然而,随着器件生成的进步,发现了各种问题,并且难以抑制MISFET中的短沟道效应,同时实现高电流驱动功率。在这种背景下,强有力地推进替代现有平面MISFET的新结构器件的研究和开发。
FINFET是上述新结构器件的一种,并且是不同于平面MISFET的三维MISFET。在FINFET中,以从半导体衬底的主面突出的薄板的形状,FET形成在半导体层之上,所以存在在FET的操作期间生成的热量难以传送到半导体衬底的问题。
例如,日本未审查专利申请公开第2009-16418号公开了关于FINFET的热量消散的技术。
发明内容
本发明努力增强具有FINFET的半导体器件的可靠性。已知半导体层温度由于FINFET操作期间的热量生成而升高,并且例如发生引起FET可靠性下降的称为HCI(热载流子注入)的现象。此外,涉及这种热量对耦合至FET的布线的影响,例如EM(电迁移)。
简而言之,需要增强具有FINFET的半导体器件的可靠性。
本发明的上述和进一步的目的和新颖特征将从以下说明书和附图的详细描述中更完整地明白。
以下简要概述本文将公开的本发明的主要方面。
根据本发明的一个方面,提供了一种半导体器件,其包括第一N沟道FET和第二N沟道FET,它们串联耦合在用于2输入NAND电路的输出的布线与用于第二功率电位的布线之间。在平面图中,局部布线设置在沿第二方向延伸的、第一N沟道FET的第一N栅电极与第二N沟道FET的第二N栅电极G2之间,并且与沿第一方向延伸的半导体层交叉且沿第二方向延伸。局部布线耦合至用于热量消散的布线。
根据本发明,增强了半导体器件的可靠性。
附图说明
图1是示出根据本发明实施例的半导体器件的配置的等效电路图;
图2是示出根据本实施例的半导体器件的配置的平面图;
图3是示出根据本实施例的半导体器件的配置的平面图;
图4是示意性示出根据本实施例的半导体器件的配置的立体图;
图5是沿着图2的线A-A截取的截面图;
图6是沿着图2的线B-B截取的截面图;
图7是沿着图2的线C-C截取的截面图;
图8是沿着图2的线D-D截取的截面图;
图9是示出根据本实施例的半导体器件的不完整立体图;
图10是沿着图9的线E-E截取的截面图;
图11是示出根据本实施例的半导体器件的布线层的不完整平面图;
图12是示出根据变形例1的半导体器件的不完整立体图;
图13是示出根据变形例2的半导体器件的配置的截面图;
图14是示出根据变形例3的半导体器件的配置的平面图;
图15是示出根据变形例3的半导体器件的不完整立体图;
图16是示出根据变形例4的半导体器件的配置的平面图;以及
图17是沿着图16的线F-F截取的截面图。
具体实施方式
以下将在不同部分中或者根据需要或为了方便独立地描述本发明的优选实施例,但是如此描述的实施例不相互无关,除非另有指定。一个实施例可以整体或部分地作为另一个实施例的修改、应用、详细或补充形式。此外,在以下描述的优选实施例中,当通过特定数字给出用于元件的数字信息时(片数、数值、量、范围等),不限于具体数字,除非另有指定或者理论上限于该特定数字;其可以大于或小于该特定数字。
在以下描述的优选实施例中,组成元件(包括组成步骤)不是必须是必要的,除非另有指定或者理论上是必要的。类似地,在以下描述的优选实施例中,当针对元件指出具体形式或位置关系时,应该解释为包括基本接近或类似于该具体形式或位置关系的形式或位置关系,除非另有指定或者理论上限于该具体形式或位置关系。这同样适用于上述数字信息(片数、数值、量、范围等)。
接下来,将详细参照附图描述优选实施例。在示出实施例的所有附图中,具有相同功能的构件由相同或相关联的参考符号来表示,并且省略其重复描述。如果存在多个类似构件(部分),则在一些情况下,特定的参考符号被添加给用于这种构件的一般性参考符号以表示各个或特定部分。在以下描述的实施例中,除非必要时,否则不重复相同或相似部分的基本描述。
关于用于示出实施例的附图,为了容易理解,即使在截面图中也可以省略阴影。此外,为了容易理解,即使在平面图中也可以使用阴影。
在截面图和平面图中,每个部分的尺寸可以不与实际器件中的尺寸成比例。为了容易理解,特定部分可以不成比例地放大示出。即使在平面图对应于截面图时,一个示图中的每个部分的尺寸也可以不与另一示图中的尺寸成比例。
在附图中,每个组成元件(例如,半导体衬底)的主表面表示其上表面,背表面表示其下表面,并且侧表面(侧壁)表示连接主表面和背表面的表面,即使没有示出它们的参考符号。
实施例
接下来,将详细描述根据本发明实施例的半导体器件(半导体集成电路器件)。根据该实施例的半导体器件具有FINFET作为半导体元件。图1是示出根据该实施例的半导体器件的配置的等效电路图。图2是示出根据该实施例的半导体器件的配置的平面图。图3是示出根据该实施例的半导体器件的配置的平面图。图4是示意性示出根据该实施例的半导体器件的配置的立体图。图5是沿着图2的线A-A截取的截面图。图6是沿着图2的线B-B截取的截面图。图7是沿着图2的线C-C截取的截面图。图8是沿着图2的线D-D截取的截面图。图9是示出根据该实施例的半导体器件的不完整立体图。图10是沿着图9的线E-E截取的截面图。图11是根据该实施例的半导体器件的布线层的平面图。
图1是配置根据该实施例的半导体器件的2输入NAND电路的等效电路图。2输入NAND电路包括:第一P沟道FET(PT1)和第二P沟道FET(PT2),它们并联耦合在电源电位(第一电源电位)VDD和输出OUT之间;以及第一N沟道FET(NT1)和第二N沟道FET(NT2),它们串联耦合在输出OUT和接地电位(第二电源电位)VSS之间。第一P沟道FET(PT1)的第一P栅电极和第一N沟道FET(NT1)的第一N栅电极耦合至输入IN1,并且第二P沟道FET(PT2)的第二P栅电极和第二N沟道FET(NT2)的第二N栅电极耦合至输入IN2。FET代表场效应晶体管。
串联耦合的第一N沟道FET(NT1)和第二N沟道FET(NT2)之间的点用作节点ND。
图2是示出根据该实施例的半导体器件的配置的平面图。图2示出了形成2输入NAND电路的逻辑电路单元LCU1。在附图中,水平方向被限定为X方向,并且垂直方向被限定为Y方向。Y方向垂直于X方向。
2输入NAND电路包括向其施加电源电位的布线M1(VDD)和向其施加接地电位的布线M1(VSS),其中,两个布线M1(VDD)和M1(VSS)都在X方向上延伸,它们之间具有给定距离。P沟道FET块PB和N沟道FET块NB被设置在布线M1(VDD)和M1(VSS)之间,并且两个块都沿X方向延伸。在P沟道FET块PB中,形成多个P沟道FET(PT1,PT2),并且在N沟道FET块NB中,形成多个N沟道FET(NT1,NT2)。
在P沟道FET块PB中,沿X方向延伸的半导体层(突出部分、鳍、有源区)FP1和FP2被设置为相互平行,并且沿Y方向在它们之间具有给定距离。栅电极G1和G2以及伪栅电极DGp1和DGp2以与半导体层FP1和FP2交叉的方式设置,并且栅电极G1和G2以及伪栅电极DGp1和DGp2沿Y方向延伸。此外,在X方向中,局部布线LIp1、LIp2和LIp3以及伪局部布线DLIp1和DLIp2以分别夹置栅电极G1和G2以及伪栅电极DGp1和DGp2的方式来设置。局部布线LIp1、LIp2和LIp3以及伪局部布线DLIp1和DLIp2沿Y方向延伸。在附图中,伪栅电极DGp1和DGp2以及伪局部布线DLIp1和DLIp2由点划线表示。
如图2所示,P沟道FET(PT1)形成在半导体层FP1和FP2与栅电极G1之间的交叉处,并且P沟道FET(PT2)形成在半导体层FP1和FP2与栅电极G2之间的交叉处。在X方向中,P沟道FET(PT1和PT2)的源极区域和漏极区域在栅电极G1和G2的两端处形成在半导体层FP1和FP2中。P沟道FET(PT1)的源极区域通过局部布线LIp2耦合至布线M1(VDD),并且漏极区域通过局部布线LIp3耦合至布线M1(OUT)。类似地,P沟道FET(PT2)的源极区域通过局部布线LIp1耦合至布线M1(VDD),并且漏极区域通过局部布线LIp3耦合至布线M1(OUT)。
形成在半导体层FP1和FP2中的两个P沟道FET(PT1)并联耦合,并且用作单个P沟道FET(PT1)。类似地,P沟道FET(PT2)包括两个并联耦合的P沟道FET(PT2)。
如图2所示,在X方向中,伪栅电极DGp1和DGp2以夹置配置2输入NAND电路的栅电极G1和G2的方式来设置,并且伪局部布线DLIp1和DLIp2以夹置配置2输入NAND电路的局部布线LIp1、LIp3和LIp2的方式来设置。栅电极或伪栅电极以及局部布线或伪局部布线在X方向上交替设置。
在N沟道FET块NB中,沿X方向延伸的半导体层(突出部分、鳍、有源区)FN1和FN2相互平行设置,在Y方向上在它们之间具有给定距离。栅电极G1和G2以及伪栅电极DGn1和DGn2以与半导体层FN1和FN2交叉的方式设置,并且栅电极G1和G2以及伪栅电极DGn1和DGn2沿Y方向延伸。此外,在X方向上,局部布线LIn1、LIn2和LIn3以及伪局部布线DLIn1和DLIn2以分别夹置栅电极G1和G2以及伪栅电极DGn1和DGn2的方式来设置。局部布线LIn1、LIn2和LIn3以及伪局部布线DLIn1和DLIn2沿Y方向延伸。在附图中,伪栅电极DGn1和DGn2以及伪局部布线DLIn1和DLIn2由点划线表示。
如图2所示,N沟道FET(NT1)形成在半导体层FN1和FN2与栅电极G1之间的交叉处,并且N沟道FET(NT2)形成在半导体层FN1和FN2与栅电极G2之间的交叉处。在X方向中,N沟道FET(NT1和NT2)的源极区域和漏极区域在栅电极G1和G2的两端处形成在半导体层FN1和FN2中。N沟道FET(NT1)的漏极区域通过局部布线LIn2耦合至布线M1(OUT),并且源极区域通过局部布线LIn3耦合至布线M1(R)。类似地,N沟道FET(NT2)的源极区域通过局部布线LIn1耦合至布线M1(VSS),并且漏极区域通过局部布线LIn3耦合至布线M1(R)。
形成在半导体层FN1和FN2中的N沟道FET(NT1)并联耦合,并且用作单个N沟道FET(NT1)。类似地,N沟道FET(NT2)包括两个并联耦合的N沟道FET(NT2)。局部布线LIn3耦合形成在半导体层FN1中的N沟道FET(NT1)的源极区域和形成在半导体层FN2中的N沟道FET(NT1)的源极区域。换句话说,其耦合形成在半导体层FN1中的N沟道FET(NT2)的漏极区域和形成在半导体层FN2中的N沟道FET(NT2)的漏极区域。
N沟道FET(NT1)和N沟道FET(NT2)串联耦合,并且N沟道FET(NT1)的源极区域和N沟道FET(NT2)的漏极区域在半导体层FN1或FN2中配置公共区域,其对应于图1所示的节点ND。
因此,为了组成2输入NAND电路,不需要将布线M1耦合至对应于节点ND的局部布线LIn3。然而,在该实施例中,布线M1(R)耦合至对应于节点ND的局部布线LIn3,使得在半导体层FN1和FN2中生成的热量可以通过布线M1(R)消散。换句话说,局部布线LIn3耦合至配置2输入NAND电路的串联耦合的N沟道FET(NT1和NT2)之间的节点ND,并且又一布线M1(R)耦合至局部布线LIn3,使得增强了N沟道FET(NT1和NT2)的可靠性。
栅电极G1耦合至对应于输入IN1的布线M1(IN1),并且栅电极G2耦合至对应于输入IN2的布线M1(IN2)。P沟道FET(PT1和PT2)的栅电极G1和G2可以分别称为第一P栅电极和第二P栅电极,并且N沟道FET(NT1和NT2)的栅电极G1和G2可以分别称为第一N栅电极和第二N栅电极。
如图2所示,在X方向上,伪栅电极DGn1和DGn2以夹置配置2输入NAND电路的栅电极G1和G2的方式来设置,并且伪局部布线DLIn1和DLIn2以夹置配置2输入NAND电路的局部布线LIn1、LIn2和LIn3的方式来设置。栅电极或伪栅电极以及局部布线或伪局部布线在X方向上交替设置。
图3是示出根据本实施例的半导体器件的配置的平面图。图3示出了一图案,其包括半导体层FP1、FP2、FN1和FN2、栅电极G1和G2、伪栅电极DGp1、DGp2、DGn1和DGn2、局部布线LIp1、LIp2、LIp3、LIn1、LIn2和LIn3、以及伪局部布线DLIp1、DLIp2、DLIn1和DLIn2。
在P沟道FET块PB中,栅电极G1和G2以及伪栅电极DGp1和DGp2均具有宽度W1,并且在X方向上以间距a布置。具体地,相邻栅电极之间的距离等于彼此相邻的栅电极和伪栅电极之间的距离。
局部布线LIp1、LIp2、LIp3以及伪局部布线DLIp1、DLIp2均具有宽度W2,并且在X方向上以间距b布置。具体地,相邻的局部布线之间的距离等于彼此相邻的局部布线和伪局部布线之间的距离。栅电极G1和G2、伪栅电极DGp1和DGp2、局部布线LIp1、LIp2、LIp3以及伪局部布线DLIp1和DLIp2的布置的序列如图3所示。
在N沟道FET块中,栅电极G1和G2与伪栅电极DGn1和DGn2之间的关系与栅电极G1和G2与伪栅电极DGp1和DGp2之间的上述关系相同。局部布线LIn1、LIn2和LIn3与伪局部布线DLIn1和DLIn2之间的关系与局部布线LIn1、LIn2和LIn3与伪局部布线DLIp1和DLIp2之间的上述关系相同。
在图3中,沿Y方向延伸的点划线是虚拟直线IM,并且例如它们是栅电极G1和G2的中心线以及局部布线LIp3或LIn3的中心线。换句话说,在Y方向上布置的局部布线LIp3和LIn3在虚拟直线IM上。此外,伪栅电极DGp1和DGn1在虚拟直线IM上;伪栅电极DGp2和DGn2在虚拟直线IM上;局部布线LIp1和LIn1在虚拟直线IM上;局部布线LIp2和LIn2在虚拟直线IM上;伪局部布线DLIp1和DLIp2在虚拟直线IM上;以及伪局部布线DLIp2和DLIn2在虚拟直线IM上。
尽管该实施例是P沟道FET(PT1)形成在两个半导体层FP1和FP2中的示例,但代替地,半导体层的数量可以是一个或者三个以上。类似地,代替两个半导体层FN1和FN2,半导体层的数量可以是一个或三个以上。
尽管在该实施例中,P沟道FET(PT1)的栅电极和N沟道FET(NT1)的栅电极被集成(作为一个连续的导体层)以形成栅电极G1,但代替地,P沟道FET(PT1)的栅电极和N沟道FET(NT1)的栅电极可以分离。
此外,伪栅电极DGp1和DGn1或者伪栅电极DGp2和DGn2可以被集成(作为一个连续导体层)。此外,伪局部布线DLIp1和DLIn1或者伪局部布线DLIp2和DLIn2可以被集成(作为一个连续导体层)。
伪栅电极DGp1、DGn1、DGp2和DGn2旨在确保对栅电极G1和G2的精确加工,并且伪局部布线DLIp1、DLIn1、DLIp2和DLIn2旨在确保对局部布线LIp1、LIn1、LIp2、LIn2、LIp3和LIn3的精确加工。例如,伪栅电极或伪局部布线的存在可以在光刻步骤或蚀刻步骤中提高对栅电极或局部布线的加工精度(形状、尺寸等)。为此,重要的是,在配置2输入NAND电路的栅电极G1和G2的两侧处,伪栅电极DGp1、DGn1、DGp2和DGn2应该布置有上述间距a。类似地,重要的是,在局部布线LIp1、LIn1、LIp2、LIn2、LIp3和LIn3的两侧处,伪局部布线DLIp1、DLIn1、DLIp2和DLIn2应该布置有上述间距b。
图4是示意性示出根据该实施例的半导体器件的配置的立体图。这里,给出图2所示N沟道FET(NT2)的解释,并且另一N沟道FET(NT1)以及P沟道FET(PT1和PT2)也具有相同的结构。
元件隔离膜STI形成在半导体衬底SUB之上,并且半导体层FN2是形成在半导体衬底SUB之上的突出部分。半导体层FN2穿过元件隔离膜STI,并且从元件隔离膜STI的主表面突出。半导体层FN2在Y方向上具有期望宽度(例如,5至20nm左右),并且沿X方向延伸。半导体衬底SUB例如由单晶硅制成,并且元件隔离膜STI例如是诸如氧化硅膜的绝缘膜。
以跨过半导体层FN2的从元件隔离膜STI突出的部分的方式,栅电极G2沿Y方向延伸。栅电极G2具有金属膜MF1和MF2,并且通过栅极绝缘膜HK设置在半导体层FN2上方。优选地,比氮化硅膜具有更高相对介电常数的高介电常数膜应该被用于栅极绝缘膜HK。例如,HfSiO(硅酸铪)、HfAlON(氮化铝酸铪)或Y2O3(氧化钇)的绝缘膜可用于栅极绝缘膜HK。对于栅电极G2,优选使用金属膜而非多晶硅膜。例如,金属膜MF1可以是TiAl(钛铝)膜,并且金属膜MF2可以是Al(铝)膜。
侧壁绝缘膜SW通过栅极绝缘膜HK形成在栅电极G2的侧壁之上。侧壁绝缘膜SW例如可以是氮化硅膜或者氮化硅膜和氧化硅膜的层压膜。如果其是层压膜,则优选地,氮化硅膜应该以接触栅极绝缘膜HK的方式来设置。栅极绝缘膜HK仅需要位于栅电极G2和半导体层FN2之间,并且不需要形成在栅电极G2的侧壁之上。
在X方向上,用于N沟道FET(PT2)的源极区域和漏极区域形成在栅电极G2和侧壁绝缘膜SW的两端处。源极区域和漏极区域形成在外延层EP中,外延层EP形成在半导体层FN2的表面上。这里,外延层例如由SiP(磷化硅)或SiC(碳化硅)制成。在P沟道FET(PT1和PT2)的情况下,外延层EP例如由SiGe(硅锗)制成。
如图4所示,由金属膜制成的局部布线LIn1和LIn3形成在外延层EP之上。局部布线LIn1和LIn3以跨过外延层EP的方式沿Y方向延伸。
图5是沿着图2的线A-A截取的截面图。P沟道FET(PT2)形成在N型阱区(N型半导体区域)NW中,N型阱区形成在P型半导体衬底SUB中。半导体层FP1是从半导体衬底SUB的主表面Sa突出的突出部分,并且作为突出部分的顶部的半导体层FP1的主表面突出较高,远离元件隔离膜STI的主表面。N型阱区NW形成在该突出部分中,并且到达元件隔离膜STI的底部。
具有金属膜MF1和MF2的栅电极G2通过栅极绝缘膜HK形成在半导体层FP1的主表面上。栅极绝缘膜HK、栅电极G2和侧壁绝缘膜SW如上面参照图4所述。
在栅电极G2的两侧处,用于P沟道FET(PT2)的源极区域S和漏极区域D形成在半导体层FP1中。源极区域S和漏极区域D均包括形成在半导体层FP1中的半导体区域SDP和半导体区域EXP以及形成在半导体层FP1之上的外延层EP。源极区域S和漏极区域D是掺杂有P型杂质的P型半导体区域,并且半导体区域EXP的杂质浓度低于半导体区域SDP和外延层EP的杂质浓度。
硅化物层SL形成在外延层EP的表面之上作为源极区域S,并且由金属膜制成的局部布线LIp1耦合至硅化物层SL,并且局部布线LIp1通过插塞电极PG耦合至布线M1(VDD)。
硅化物层SL形成在外延层EP的表面之上作为漏极区域D,并且由金属膜制成的局部布线LIp3耦合至硅化物层SL,并且局部布线LIp3通过插塞电极PG耦合至布线M1(OUT)。
在X方向上,伪栅电极DGp1和伪局部布线DLIp1被顺序布置,相对于局部布线LIp1与栅电极G2相对。伪栅电极DGp1具有与栅电极G2相同的结构,并且伪局部布线DLIp1具有与局部布线LIp1和LIp3相同的结构。
外延层EP和半导体区域SDP也形成在伪局部布线DLIp1下方。具有伪栅电极DGp1作为栅电极的伪FET形成为与P沟道FET(PT2)相邻。伪栅电极DGp1具有浮置电位,并且伪FET不能导电。伪局部布线DLIp1也具有浮置电位。换句话说,伪栅电极DGp1和伪局部布线DLIp1不耦合至布线M1,并且与2输入NAND电路电隔离。
层间绝缘膜IL1覆盖元件隔离膜STI和外延层EP,并且例如是诸如氧化硅膜的绝缘膜。层间绝缘膜IL1通过侧壁绝缘膜SW和栅极绝缘膜HK覆盖栅电极G2的侧面。
层间绝缘膜IL2形成在层间绝缘膜IL1之上,并且覆盖栅电极G2和伪栅电极DGp1。层间绝缘膜IL2例如是诸如氧化硅膜或氮化硅膜的绝缘膜。局部布线LIp1和LIp3以及伪局部布线DLIp1穿过层间绝缘膜IL2和IL1并且邻接硅化物层SL,并且局部布线LIp1和LIp3以及伪局部布线DLIp1的侧壁接触层间绝缘膜IL2和IL1,并且被层间绝缘膜IL2和IL1环绕。
层间绝缘膜IL3形成在层间绝缘膜IL2之上,并且覆盖局部布线LIp1和LIp3以及伪局部布线DLIp1。层间绝缘膜IL3例如是诸如氧化硅膜的绝缘膜。插塞电极PG穿过层间绝缘膜IL3并邻接局部布线LIp1和LIp3,并且插塞电极PG的侧壁接触层间绝缘膜IL3并被层间绝缘膜IL3环绕。
层间绝缘膜IL4形成在层间绝缘膜IL3之上,并且布线M1(VDD)和M1(OUT)穿过层间绝缘膜IL4并邻接插塞电极PG。布线M1(VDD)和M1(OUT)的侧壁接触层间绝缘膜IL4并且被层间绝缘膜IL4环绕。为了减小布线间电容,层间绝缘膜IL4被形成为具有比层间绝缘膜IL1、IL2和IL3更低的相对介电常数的膜,其被称为低k膜(3.0以下的相对介电常数)。低k膜是氢硅酸盐(SQ)、甲基化硅酸盐(MSQ)和含碳氧化硅膜(SiOC)。
图6是沿着图2的线B-B截取的截面图。这里,给出P沟道FET(PT2)的解释,并且P沟道FET(PT1)具有与P沟道FET(PT2)相同的结构。此外,N沟道FET(NT1,NT2)具有类似结构。具体地,在N沟道FET的情况下,通过半导体区域SDN代替半导体区域SDP,并且通过P型阱区PW来代替N型阱区NW。
如图6所示,半导体层(突出部分、鳍、有源区)FP1和FP2穿过元件隔离膜STI,并且从半导体衬底SUB的主表面Sa突出。在图6中,半导体层FP1和FP2通过矩形表示,但是代替地,它们可具有圆化的上端角或者可以几乎为梯形或三角形,在两侧(侧面、侧壁)具有倾斜的长边。重要的是,半导体层FP1和FP2应该在Y方向上具有期望的宽度、从元件隔离膜STI突出的部分的期望高度、以及沿X方向的期望长度。类似地,半导体层FN1和FN2具有期望宽度、期望高度和期望长度。
如图6所示,在每个半导体层FP1和FP2中,外延层EP形成在从元件隔离膜STI突出的部分中,使得每个半导体层FP1和FP2中从元件隔离膜STI突出的部分、以及外延层EP配置P型半导体区域SDP。半导体区域SDP是P沟道FET(PT2)的源极区域S。
局部布线LIp1以与形成在半导体层FP1和FP2中的两个外延层EP重叠的方式来设置,使得两个外延层EP(源极区域)通过局部布线LIp1电耦合。硅化物层SL形成在两个外延层EP与局部布线LIp1之间的界面中,以减小它们之间的接触电阻。
此外,局部布线LIp1耦合至布线M1(VDD),通过插塞电极PG向布线M1提供电源电位。层间绝缘膜IL1至IL4如前所述。
图7是沿着图2的线C-C截取的截面图。N沟道FET(NT1和NT2)形成在P型阱区(P型半导体区域)PW中,P型阱区PW形成在P型半导体衬底SUB上。N沟道FET(NT1)的栅电极G1和N沟道FET(NT2)的栅电极G2通过栅极绝缘膜HK形成在半导体层FN2的主表面Fu之上。
在每个栅电极G1和G2的两侧处,每个N沟道FET(NT1和NT2)的源极区域S和漏极区域D形成在半导体层FN2中。源极区域S和漏极区域D均包括形成在半导体层FN2中的半导体区域SDN和半导体区域EXN、以及外延层EP。源极区域S和漏极区域D是掺杂有N型杂质的N型半导体区域,并且半导体区域EXN的杂质浓度低于半导体区域SDN和外延层EP的杂质浓度。
如先前参照图2所述,N沟道FET(NT1和NT2)被串联耦合,并且N沟道FET(NT1)的源极区域S和N沟道FET(NT2)的漏极区域D配置公共半导体区域SDN。该公共半导体区域SDN对应于图1所示的节点ND。外延层EP形成在公共半导体区域SDN之上,并且局部布线LIn3通过形成在外延层EP表面上的硅化物层SL而形成在外延层EP之上。此外,用于热量消散的布线M1(R)通过插塞电极PG耦合至局部布线LIn3。
外延层EP还形成在作为N沟道FET(NT1)的漏极区域D的半导体区域SDN之上,并且局部布线LIn2通过形成在外延层EP表面上的硅化物层SL而形成在外延层EP之上。此外,局部布线LIn2通过插塞电极PG耦合至用于输出的布线M1(OUT)。
外延层EP还形成在作为N沟道FET(NT2)的源极区域S的半导体区域SDN之上,并且局部布线LIn1通过形成在外延层EP表面上的硅化物层SL而形成在外延层EP之上。此外,局部布线LIn1通过插塞电极PG耦合至用于接地电位的布线M1(VSS)。与其耦合的布线M1(VSS)和插塞电极PG通过虚线表示,因为它们在图7中没有出现,其中图7示出了沿着图2的线C-C截取的截面图。
栅极绝缘膜HK、金属膜MF1和MF2、以及侧壁绝缘膜SW如上参照图4所述,并且层间绝缘膜IL1至IL4如上参照图5所述。
如前所述,在该实施例中,布线M1(R)耦合至对应于节点ND的局部布线LIn3,使得在半导体层FN1和FN2中生成的热量通过布线M1(R)消散。具体地,局部布线LIn3耦合至位于配置2输入NAND电路的串联耦合的N沟道FET(NT1和NT2)之间的节点ND,并且又一布线M1(R)耦合至局部布线LIn3,使得增强了N沟道FET(NT1和NT2)的可靠性。
图8是沿着图2的线D-D截取的截面图。在Y方向上,半导体层FN1和FN2具有主表面Fu以及两个侧面(侧壁)Fs。以覆盖从单元隔离膜STI露出的半导体层FN1和FN2的方式,沿着主表面Fu和侧面Fs形成栅极绝缘膜HK,并且栅电极G2形成在栅极绝缘膜HK之上。栅电极G2具有层压结构,其包括金属膜MF1和设置于其上方的金属膜MF2。
此外,栅电极G2通过插塞电极PG耦合至用于输入的布线M1(IN2)。
图9是示出根据该实施例的半导体器件的不完整立体图。图10是沿着图9的线E-E截取的截面图。其示出了耦合至局部布线LIn3的热量消散结构。
局部布线LIn3通过插塞电极PG耦合至布线M1(R)。布线M1(R)顺次地耦合至通孔导体层V1、布线M2、通孔导体层V2、布线M3、通孔导体层V3、布线M4(R)和布线M5。从插塞电极PG到布线M5的层压结构是热量消散结构。布线M1(R)、通孔导体层V1、布线M2、通孔导体层V2、布线M3、通孔导体层V3、布线M4(R)和布线M5仅耦合至局部布线LIn3,形成独立的图案,并且它们不耦合至任何其他布线。
如图10所示,如上所述,环绕布线M1(R)的侧面的层间绝缘膜IL4、环绕布线M2和通孔导体层V1的侧面的层间绝缘膜IL5以及环绕布线M3和通孔导体层V2的侧面的层间绝缘膜IL6由低k膜制成。环绕布线M4(R)和通孔导体层V3的侧面的层间绝缘膜IL7以及设置在层间绝缘膜IL7之上的层间绝缘膜IL8由相对介电常数比层间绝缘膜IL4至IL6高且比层间绝缘膜IL1至IL3低的绝缘膜制成。层间绝缘膜IL7和IL8例如由含氟(F)氧化硅膜(SiOF)制成。
在图10中,箭头表示热量消散路径。在半导体层FN1和FN2中生成的热量通过热量消散结构而消散。具体地,由于层间绝缘膜IL7和IL8的导热率大于层间绝缘膜IL4至IL6,所以优选地耦合至局部线LIn3直到布线M4(R)或M5。
这里,插塞电极PG具有层压结构,其包括阻挡导体膜(例如,钛膜、氮化钛膜或者包括这些膜的层压膜)和钨膜等作为主导体膜。具体地,主导体膜被隐埋在杯状阻挡导体膜中。
布线M1(R)是铜布线,并且具有主导体膜(例如,镀铜膜)隐埋在杯状阻挡导体膜(例如,氮化钛膜、钽膜或者氮化钽膜)中的结构。
布线M4(R)和通孔导体层V3例如通过所谓的双镶嵌方法来集成,形成包括在层间绝缘膜IL7和布线M3上邻接的阻挡导体膜(例如,氮化钛膜、钽膜或氮化钽膜)和埋入其中的主导体膜(例如,镀铜膜)的层压结构。此外,布线层M4(R)和层间绝缘膜IL7的主表面被用作铜扩散防止膜的阻挡绝缘膜BL4覆盖。阻挡绝缘膜BL4例如是SiCO膜、SiCN膜等(同样适用于BL1至BL3)。此外,布线M3和通孔导体层V2、以及布线M2和通孔导体层V1具有与布线M4(R)和通孔导体层V3相同的结构。布线M5具有层压结构,其包括阻挡膜(例如,钛膜和氮化钛膜的层压)和设置在阻挡膜之上的主导体膜(铝膜或包含杂质(铜迹线)的铝膜)。
图11是示出根据该实施例的半导体器件的布线层的不完整平面图。具体地,其示出了与布线M4(R)位于相同层中的布线图案。如图11所示,多个布线M4(D)以环绕作为热量消散结构的一部分的布线M4(R)的方式来布置。如图10所示,通过热量消散结构从半导体层FN1和FN2传送到布线M4(R)的热量也从布线M4(D)消散,使得可以提高热量消散效率。布线M4(D)不耦合至任何其他布线,组成独立的布线图案。由于热量还可以通过布线M4(R)的侧面消散,所以可以提高热量消散效率。然而,即使布线M4(D)耦合至另一布线或元件(FET)等的情况下也不存在问题。
变形例1
变形例1是上面的图9所示实施例的变形例的示例。图12是示出根据变形例1的半导体器件的不完整立体图。
如图12所示,局部布线LIn3通过两个插塞电极PG耦合至布线M1(R),并且顺序通过三个通孔导体层V1、V2和V3进一步耦合至布线M2、M3和M4(R)。
由于通过使用两个插塞电极PG以及三个通孔导体层V1、V2和V3提供了从局部布线LIn3到布线M4(R)的热量消散路径,所以可以提高热量消散效率。
变形例2
图13是示出根据变形例2的半导体器件的配置的截面图。如图13所示,热量消散器HD通过绝缘膜IF隐埋在沟槽DP中,沟槽DP穿过层间绝缘膜IL3、IL2和IL1并到达半导体衬底SUB的内侧。热量消散器HD例如由铜膜等制成。
热量消散器HD通过设置在热量消散器HD之上的布线M1、通孔导体层V1、布线M2和通孔导体层V2耦合至布线M3。另一方面,局部布线LIn3耦合至半导体层FN1,并且FN2通过插塞电极PG、布线M1(R)、通孔导体层V1、布线M2和通孔导体层V2耦合至布线M3。
在半导体层FN1和FN2中生成的热量通过插塞电极PG、通孔导体层V1和V2、布线M1(R)、M2、M3和M1传送到热量消散器HD,并且例如消散到半导体衬底SUB等。
变形例3
图14是示出根据变形例3的半导体器件的配置的平面图。图15是示出根据变形例3的半导体器件的不完整立体图。
如图14所示,根据变形例3的半导体器件包括两个2输入NAND电路。2输入NAND电路形成在两个相邻的逻辑电路单元LCU1和LCU2的每一个中。根据上述实施例的热量消散结构耦合至逻辑电路单元LCU1和LCU2的每个逻辑布线LIn3。在根据变形例3的半导体器件中,如图15所示,两个热量消散结构通过布线M3耦合,并且两个热量消散结构共享通孔导体层V3以及耦合至布线M3的布线M4(R)和M5。
具体地,逻辑电路单元LCU1的局部布线LIn3通过插塞电极PG、布线M1(R)、通孔导体层V1、布线M2、通孔导体层V2和布线M3耦合至公共通孔导体层V3和公共布线M4(R)和M5。类似地,逻辑电路单元LCU2的局部布线LIn3通过插塞电极PG、布线M1(R)、通孔导体层V1、布线M2、通孔导体层V2和布线M3耦合至公共通孔导体层V3和公共布线M4(R)和M5。
除了由上述实施例提供的优势效果之外,变形例3提供了可以改进与布线M4(R)和M5同一层级处的布线层的设计自由度的优势效果。
变形例4
变形例4是上述实施例中的图2所示变形例的示例,其中热量消散结构耦合至伪栅电极DGp1和伪局部布线DLIp1。代替地,热量消散结构可以耦合至伪栅电极DGp1或伪局部布线DLIp1。类似地,热量消散结构可以耦合至以下至少之一:伪栅电极DG1、DGn1或DGn2、或者伪局部布线DLIp2、DLIn1或DLIn2。
图16是示出根据变形例4的半导体器件的配置的平面图。图17是沿着图16的线F-F截取的截面图。
如图16和图17所示,用于热量消散的布线M1(R)通过插塞电极PG耦合至伪栅电极DGp1。根据上述实施例的图9和图10所示热量消散结构耦合至伪栅电极DGp1。在该结构中,栅极绝缘膜HK设置在伪栅电极DGp1和半导体层FP1之间,但是栅极绝缘膜HK的厚度约为几纳米,并且在半导体层FP1中生成的热量可以通过伪栅电极DGp1和热量消散结构而消散。
与根据上述实施例的图9和图10所示中一个相同的热量消散结构也耦合至伪局部布线DLIp1。
变形例4可以改进P沟道FET和N沟道FET的热量消散特性,并且增强P沟道FET和N沟道FET的可靠性。此外,其可以改进热量消散特性而不影响逻辑电路。
此外,变形例4可以应用于除2输入NAND电路之外的逻辑电路。例如,作为上述实施例中图2所示的变形例,可以通过省略栅电极G1和局部布线LIp2和LIn2并且将局部布线LIp3和LIn3耦合至输出布线M1(OUT)来制造包括P沟道FET(PT2)和N沟道FET(NT2)的反相器电路。在这种情况下,在P沟道FET块PB中,重要的是,伪栅电极DGp1和DGp2应该以夹置栅电极G2的方式来布置,并且伪局部布线DLIp1和DLIp2应该以夹置局部布线LIp1和LIp3的方式来布置。此外,在N沟道FET块NB中,重要的是,伪栅电极DGn1和DGn2应该以夹置栅电极G2的方式来布置,并且伪局部布线DLIn1和DLIn2应该以夹置局部布线LIn1和LIn3的方式来布置。
至此参照优选实施例(或实施例的变形例)具体解释了由发明人做出的本发明。然而,本发明不限于上述实施例(或其变形例)。明显地,这些细节可以以各种方式来修改,而不背离其精神。例如,本发明包括以下示例。
注解1
一种具有逻辑电路的半导体器件,
该电路包括:
P沟道FET,耦合在第一电源电位布线和输出布线之间;
N沟道FET,耦合在输出布线和第二电源电位布线之间;以及
输入布线,耦合至P沟道FET的P栅电极和N沟道FET的N栅电极;
该半导体器件包括:
半导体衬底,具有主表面;
元件隔离膜,形成在半导体衬底的主表面上;
第一半导体层,穿过元件隔离膜,从半导体衬底的主表面突出,并且在平面图中沿着第一方向延伸;
P栅电极和伪栅电极,通过第一栅极绝缘膜设置在第一半导体层之上,并且沿垂直于第一方向的第二方向延伸;
局部布线,沿第一方向设置在P栅电极和伪栅电极之间,沿第二方向延伸,并且耦合至第一电源电位布线;以及
第一布线,耦合至伪栅电极,
其中伪栅电极和第一布线与逻辑电路电独立,并具有浮置电位。注解2
一种具有逻辑电路的半导体器件,
该电路包括:
P沟道FET,耦合在第一电源电位布线和输出布线之间;
N沟道FET,耦合在输出布线和第二电源电位布线之间;以及
输入布线,耦合至P沟道FET的P栅电极和N沟道FET的N栅电极;
该半导体器件包括:
半导体衬底,具有主表面;
元件隔离膜,形成在半导体衬底的主表面之上;
第一半导体层,穿过元件隔离膜,从半导体衬底的主表面突出,并且在平面图中沿第一方向延伸;
P栅电极和伪栅电极,通过第一栅极绝缘膜设置在第一半导体层之上,并且沿垂直于第一方向的第二方向延伸;
局部布线,沿第一方向设置在P栅电极和伪栅电极之间,沿第二方向延伸且耦合至第一电源电位布线;
伪局部布线,沿第一方向设置为相对于伪栅电极与局部布线相对,与第一半导体层交叉,并且沿第二方向延伸;
第一层间绝缘膜,形成在半导体衬底的主表面之上,覆盖P栅电极和伪栅电极,并且邻接在伪局部布线的侧壁上;
第二层间绝缘膜,设置在第一层间绝缘膜之上;以及
第一布线,耦合至伪局部布线并且设置在第二层间绝缘膜之上,
其中伪局部布线与逻辑电路电独立,并具有浮置电位。
Claims (19)
1.一种半导体器件,包括2输入NAND电路,所述2输入NAND电路包括:
第一P沟道FET和第二P沟道FET,并联耦合在第一电源电位布线和输出布线之间;
第一N沟道FET和第二N沟道FET,串联耦合在所述输出布线和第二电源电位布线之间;
第一输入布线,耦合至所述第一P沟道FET的第一P栅电极和所述第一N沟道FET的第一N栅电极;以及
第二输入布线,耦合至所述第二P沟道FET的第二P栅电极和所述第二N沟道FET的第二N栅电极,包括:
半导体衬底,具有主表面;
元件隔离膜,形成在所述半导体衬底的所述主表面上;
第一半导体层,穿过所述元件隔离膜,从所述半导体衬底的所述主表面突出,并且在平面图中沿第一方向延伸;
所述第一N栅电极和所述第二N栅电极,通过第一栅极绝缘膜设置在所述第一半导体层之上,并且沿垂直于所述第一方向的第二方向延伸;
第一局部布线,沿所述第一方向设置在所述第一N栅电极和所述第二N栅电极之间,并且沿所述第二方向延伸;
第二局部布线,沿所述第一方向设置为相对于所述第二N栅电极与所述第一局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸,其中所述第二局部布线耦合至所述第二电源电位布线;
第三局部布线,沿所述第一方向设置为相对于所述第一N栅电极与所述第一局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸,其中所述第三局部布线耦合至所述输出布线,
第一层间绝缘膜,形成在所述半导体衬底的所述主表面之上,覆盖所述第一N栅电极和所述第二N栅电极,露出所述第一局部布线的主表面并邻接在其侧壁上;
第二层间绝缘膜,设置在所述第一层间绝缘膜之上;以及
第一布线,耦合至所述第一局部布线并且设置在所述第二层间绝缘膜之上,
其中所述第一N沟道FET的漏极区域通过所述第三局部布线耦合至所述输出布线,并且所述第一N沟道FET的源极区域通过所述第一局部布线耦合至另一布线,并且
其中所述第二N沟道FET的源极区域通过所述第二局部布线耦合至所述第二电源电位布线,并且所述第二N沟道FET的漏极区域通过所述第一局部布线耦合至所述另一布线。
2.根据权利要求1所述的半导体器件,还包括:
第一半导体区域,形成在所述第一半导体层中并耦合至所述第一局部布线;
第二半导体区域,形成在所述第一半导体层中并耦合至所述第二局部布线;以及
第三半导体区域,形成在所述第一半导体层中并耦合至所述第三局部布线。
3.根据权利要求1所述的半导体器件,还包括:
第二半导体层,穿过所述元件隔离膜,从所述半导体衬底的所述主表面突出,并且沿所述第一方向延伸且在平面图中沿所述第二方向与所述第一半导体层隔开,
其中所述第一P栅电极和所述第二P栅电极通过第二栅极绝缘膜设置在所述第二半导体层之上,并且沿所述第二方向延伸,
其中所述第一P栅电极和所述第一N栅电极设置在沿所述第二方向延伸的虚拟第一直线上,并且
其中所述第二P栅电极和所述第二N栅电极设置在沿所述第二方向延伸的虚拟第二直线上。
4.根据权利要求3所述的半导体器件,还包括:
第四局部布线,沿所述第一方向设置在所述第一P栅电极和所述第二P栅电极之间,并且沿所述第二方向延伸;
第五局部布线,沿所述第一方向设置为相对于所述第二P栅电极与所述第四局部布线相对,与所述第二半导体层交叉,并且沿所述第二方向延伸;以及
第六局部布线,沿所述第一方向形成为相对于所述第一P栅电极与所述第四局部布线相对,与所述第二半导体层交叉,并且沿所述第二方向延伸,
其中所述第四局部布线耦合至所述输出布线,并且
其中所述第五局部布线和所述第六局部布线耦合至所述第一电源电位布线。
5.根据权利要求4所述的半导体器件,
其中所述第一局部布线和所述第四局部布线设置在沿所述第二方向延伸的虚拟第三直线上,
其中所述第二局部布线和所述第五局部布线设置在沿所述第二方向延伸的虚拟第四直线上,并且
其中所述第三局部布线和所述第六局部布线设置在沿所述第二方向延伸的虚拟第五直线上。
6.根据权利要求5所述的半导体器件,其中所述第一局部布线至所述第六局部布线沿所述第一方向布置为具有相等节距。
7.根据权利要求1所述的半导体器件,还包括:
第三层间绝缘膜,邻接在所述第一布线的侧壁上并且在平面图中环绕所述第一布线;
第二布线,耦合至所述第一布线并且设置在所述第三层间绝缘膜之上;以及
第四层间绝缘膜,邻接在所述第二布线的侧壁上并且在平面图中环绕所述第二布线,
其中所述第四层间绝缘膜的相对介电常数小于所述第三层间绝缘膜的相对介电常数。
8.根据权利要求7所述的半导体器件,还包括:
多条第三布线,设置在所述第三层间绝缘膜之上并且在平面图中设置在所述第二布线周围,
其中所述多条第三布线的侧壁邻接在所述第四层间绝缘膜上,并且
其中所述第四层间绝缘膜在平面图中环绕每条所述第三布线。
9.根据权利要求1所述的半导体器件,还包括:
第一插塞电极,在平面图中由所述第二层间绝缘膜环绕,并且耦合所述第一局部布线与所述第一布线。
10.根据权利要求9所述的半导体器件,还包括:
第二插塞电极,在平面图中由所述第二层间绝缘膜环绕,并且耦合所述第一局部布线与所述第一布线。
11.根据权利要求1所述的半导体器件,还包括:
金属层,所述金属层通过从所述半导体衬底的所述主表面朝向其背表面形成的沟槽中的绝缘膜而形成,
其中所述金属层耦合至所述第一布线。
12.一种半导体器件,包括2输入NAND电路,所述2输入NAND电路包括:
第一P沟道FET和第二P沟道FET,并联耦合在第一电源电位布线和输出布线之间;
第一N沟道FET和第二N沟道FET,串联耦合在所述输出布线和第二电源电位布线之间;
第一输入布线,耦合至所述第一P沟道FET的第一P栅电极和所述第一N沟道FET的第一N栅电极;以及
第二输入布线,耦合至所述第二P沟道FET的第二P栅电极和所述第二N沟道FET的第二N栅电极,包括:
半导体衬底,具有主表面;
元件隔离膜,形成在所述半导体衬底的所述主表面上;
第一半导体层,穿过所述元件隔离膜,从所述半导体衬底的所述主表面突出,并且在平面图中沿第一方向延伸;
所述第一P栅电极和所述第二P栅电极,通过第一栅极绝缘膜设置在所述第一半导体层之上,并且沿垂直于所述第一方向的第二方向延伸;
第一局部布线,沿所述第一方向设置在所述第一P栅电极和所述第二P栅电极之间,并且沿所述第二方向延伸且耦合至所述输出布线;
第二局部布线,沿所述第一方向设置为相对于所述第一P栅电极与所述第一局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸且耦合至所述第一电源电位布线;
第三局部布线,沿所述第一方向设置为相对于所述第二P栅电极与所述第一局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸且耦合至所述第一电源电位布线;
伪栅电极,沿所述第一方向设置为相对于所述第三局部布线与所述第二P栅电极相对,与所述第一半导体层交叉,沿所述第二方向延伸且通过第二栅极绝缘膜设置在所述第一半导体层之上;
第一层间绝缘膜,形成在所述半导体衬底的所述主表面之上并且覆盖所述第一P栅电极、所述第二P栅电极和所述伪栅电极;以及
第一布线,耦合至所述伪栅电极并且设置在所述第一层间绝缘膜之上,
其中所述伪栅电极和所述第一布线与所述2输入NAND电路电独立,并且具有浮置电位。
13.根据权利要求12所述的半导体器件,还包括:
插塞电极,在平面图中由所述第一层间绝缘膜环绕,并且耦合所述伪栅电极与所述第一布线。
14.根据权利要求12所述的半导体器件,其中在所述第一方向上,所述第一P栅电极和所述第二P栅电极之间的第一距离等于所述第二P栅电极和所述伪栅电极之间的第二距离。
15.一种半导体器件,包括2输入NAND电路,所述2输入NAND电路包括:
第一P沟道FET和第二P沟道FET,并联耦合在第一电源电位布线和输出布线之间;
第一N沟道FET和第二N沟道FET,串联耦合在所述输出布线和第二电源电位布线之间;
第一输入布线,耦合至所述第一P沟道FET的第一P栅电极和所述第一N沟道FET的第一N栅电极;以及
第二输入布线,耦合至所述第二P沟道FET的第二P栅电极和所述第二N沟道FET的第二N栅电极,包括:
半导体衬底,具有主表面;
元件隔离膜,形成在所述半导体衬底的所述主表面上;
第一半导体层,穿过所述元件隔离膜,从所述半导体衬底的所述主表面突出,并且在平面图中沿第一方向延伸;
所述第一P栅电极和所述第二P栅电极,通过第一栅极绝缘膜设置在所述第一半导体层之上,并且沿垂直于所述第一方向的第二方向延伸;
第一局部布线,沿所述第一方向设置在所述第一P栅电极和所述第二P栅电极之间,沿所述第二方向延伸,并且耦合至所述输出布线;
第二局部布线,沿所述第一方向设置为相对于所述第一P栅电极与所述第一局部布线相对,与所述第一半导体层交叉,沿所述第二方向延伸且耦合至所述第一电源电位布线;
第三局部布线,沿所述第一方向设置为相对于所述第二P栅电极与所述第一局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸且耦合至所述第一电源电位布线;
伪栅电极,沿所述第一方向设置为相对于所述第三局部布线与所述第二P栅电极相对,与所述第一半导体层交叉,沿所述第二方向延伸且通过第二栅极绝缘膜设置在所述第一半导体层之上;
第四局部布线,沿所述第一方向设置为相对于所述伪栅电极与所述第三局部布线相对,与所述第一半导体层交叉,并且沿所述第二方向延伸;
第一层间绝缘膜,形成在所述半导体衬底的所述主表面之上,覆盖所述第一P栅电极、所述第二P栅电极和所述伪栅电极,并且邻接在所述第四局部布线的侧壁上;
第二层间绝缘膜,设置在所述第一层间绝缘膜之上;以及
第一布线,耦合至所述第四局部布线并设置在所述第二层间绝缘膜之上,
其中所述伪栅电极与所述2输入NAND电路电独立,并且具有浮置电位。
16.根据权利要求15所述的半导体器件,其中所述第四局部布线与所述2输入NAND电路电独立,并且具有浮置电位。
17.根据权利要求15所述的半导体器件,还包括:
插塞电极,在平面图中由所述第二层间绝缘膜环绕,并且耦合所述第四局部布线与所述第一布线。
18.根据权利要求15所述的半导体器件,其中在所述第一方向上,所述第一P栅电极和所述第二P栅电极之间的第一距离等于所述第二P栅电极和所述伪栅电极之间的第二距离。
19.根据权利要求15所述的半导体器件,其中在所述第一方向上,所述第三局部布线与所述第一局部布线之间的第三距离等于所述第四局部布线和所述第三局部布线之间的第四距离。
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JP2003332429A (ja) * | 2002-05-09 | 2003-11-21 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
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US7403094B2 (en) | 2005-04-11 | 2008-07-22 | Texas Instruments Incorporated | Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating |
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JP5712579B2 (ja) | 2010-11-30 | 2015-05-07 | 富士通セミコンダクター株式会社 | 半導体装置 |
US9472483B2 (en) | 2014-12-17 | 2016-10-18 | International Business Machines Corporation | Integrated circuit cooling apparatus |
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US20060145347A1 (en) * | 2005-01-06 | 2006-07-06 | Kazuhiko Aida | Semiconductor device and method for fabricating the same |
US20120146186A1 (en) * | 2010-12-08 | 2012-06-14 | International Business Machines Corporation | Thermally controlled refractory metal resistor |
US20160190138A1 (en) * | 2013-09-04 | 2016-06-30 | Socionext Inc. | Semiconductor device |
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