CN108628579A - The multivalue mutual excitation for quantifying logic quantifies register - Google Patents
The multivalue mutual excitation for quantifying logic quantifies register Download PDFInfo
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- CN108628579A CN108628579A CN201710205918.3A CN201710205918A CN108628579A CN 108628579 A CN108628579 A CN 108628579A CN 201710205918 A CN201710205918 A CN 201710205918A CN 108628579 A CN108628579 A CN 108628579A
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- multivalue
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The multivalue mutual excitation quantization register of quantization logic is that the multivalue width adaptability in tactics benefit device quantified by patent application with two described in the multivalue width adaptability in tactics benefit device of logic forms, it is characterised in that：Two multivalue width adaptability in tactics are mended device and are set up in parallel, the input terminal that the multivalue width adaptability in tactics mends device 1 is R, output end is Q1, the input terminal that the multivalue width adaptability in tactics mends device 2 is S, output end is Q2, the input terminal R for multivalue width adaptability in tactics being mended device 1 is connected on the output end Q2 of multivalue width adaptability in tactics benefit device 2, the input terminal S for multivalue width adaptability in tactics being mended device 2 is connected on the output end Q1 of multivalue width adaptability in tactics benefit device 1, the multivalue width adaptability in tactics mends the input terminal R that 1 multivalue width adaptability in tactics of device mends device 2, S is the Complementary input structure excitation end of register, the multivalue width adaptability in tactics mends the output end Q1 that 1 multivalue width adaptability in tactics of device mends device 2, Q2 is the complementary output end of register.
Description
Technical field
The present invention relates to field of computer technology, specifically realize one of underlying hardware of multivalue computer " quantization logic
Multivalue mutual excitation quantify register "
Technical background
Computers all so far and its relevant digital display circuit are all two-values, and multivalue is calculated in spite of many excellent
Point, but because of the key hardware without supporting multi-value operation, so development is extremely slow, it may be said that and multivalue computer is especially
The realization of decade computer is almost nil, and in light of this situation, I has proposed a kind of simple and effective multivalue and calculate in fact
Circuit is applied to be especially the effective ways of ten values calculating and be especially the adding of ten values with two-value hardware realization multivalue, subtract, multiply, the calculation removed
The Key Circuit of art operation and its logical operation is called " quantization logic " and its circuit, referring specifically to patent application
(201710023530.1201710023529.9201710023528.4201710024248.5201710024246.6201710
024247.0), there are two types of information patterns for quantization logic tool itself, and one is positions to weigh information pattern, and one is width to weigh information pattern,
Physical circuit under two kinds of information patterns also has bigger difference, is then that position power information and width power information are converted mutually in real work
The chief is respectively used, the numerical operation in relation to multilevel information weighs information dependent on position, but the performance of natural information is simulation letter mostly
Breath, then the position power of acquisition standard and width power information will be the key that circuit trend is substantially applied, moreover width weighs the multivalue of information
Storage method is also that we are desired.
Invention content
" quantization logic " is that the label information generated after being quantified with analog information carries out logical operation as operator, is deduced,
The flogic system of judgement
Quantify the simple understanding of logic
The method that mark value continuous, fuzzy, after chaos information quantization carries out logical operation as input and output is just named
Quantization logic is done, realizes that the circuit of its operation is just called quantization logic circuit, then quantifies the input preamble part of logic circuit
Most of is quantizer or the weights line being quantized.Postposition output par, c is that quantization weight line or quantization width weigh line.
Quantization logic has used the basic thought of two-valued function and multi valued logic or even fuzzy logic, and with simple and effective
Be orientated circuit with two-value and realize the Key Circuit of multivalue and its fuzzy logic so that be only limited to simple two in logic original paper
It is same to form multivalue and its fuzzy logical operation circuit in the case of kind state, especially quantify the compatible operation of logic
Fundamentally solve the problems, such as multi-value operation, deposit with the method for quantization deposit, to open computing device of new generation
Update level road.The bustling various operation method of quantization logic can provide effective hardware support to the development of artificial intelligence.
Quantify logic circuit for two-valued function circuit, structure is more complicated, but I believe that in ultra-large collection
At under the support of circuit engineering, the machine that is more than two-value computing device by being continuing effort to may be implemented performance.
Quantifying logic circuit, there are two types of circuit implementing methods, and one is transported as input/output information with amplitude weights
" width power type quantifies logic circuit " calculated, another kind are that as input/output information, " position power type quantifies logic with position weight
Circuit " can be " width power type " in practice, can also be " position power type ", can also be " mixed type ".
The numerical value representation method of position power type quantization logic
It is called position power table with one group of method that spatially position weight of the line of parallel arranged or point indicates numerical values recited
Show that method, position indication have the property that：
1, the quantity of spatial parallelism arranging line is identical with using magnitude carry system, and binary number is indicated with two lines, three into
System indicates with three lines ... quinary indicates with five lines ... the decimal systems indicate that N systems are indicated with N line with ten lines.
2, the voltage on line is that high level is effective, and low level or 0 level indicate invalid.Vice versa.
3, uniquely there was only a line in one group of line at any time, remaining line is locked into invalid state for high level.
Width power type quantifies logic value representation method
1, it is that amplitude information is quantized into multiple isolated numerical value with equal difference attribute and indicates to weigh with the value that width, which weighs information,
I.e. one arithmetic progression of composition is sized in width weights by the amplitude information of weight
2, the ordered series of numbers maxitem of its Quantitatively Selecting of width power information indicates scale.
3, general natural number 0,1,2 ... it is the optimal selection that weight indicates
Quantifying the essential characteristic of logic is
1：It is that logic " state " and information " power " are detached first to quantify logic, and the combination form of logic ensures that logic is closed
Be is complete correct, and the weights of information are attached in logic state and not by logic state restrict, are believed with abundant displaying
Colourful combination performance relationship is ceased, this method actually people are using but are being the failure to detach, such as：Pick up certain
One analog information first has to detection with or without information (logic detection), then just evaluates and tests metric width weights.Obvious information
Whether there is or not being logic judgment, and the magnitude of information is then numerical metric, and the meaning of the two is different.Once presentation of information " having " is patrolled
The state of collecting, i.e., to complete logical operation, and the colorful variation of information amplitude later is not limited by logic state " having ".
2：Operation is carried out using " having " "None" Information sign, " having " "None" Information sign is different from the high and low of two value informations
Information, most apparent difference is that two value informations take two logical symbols 0 and 1 of height, 0 indicates low, and 1 indicates high, and two kinds of shapes of height
State is both logic state and binary number value information, and quantifies logic and indicate logic state, " having " and two with " having " and "None"
There is information in corresponding display position of height of value logic, and to show its scale numerical value weights, and "None" then shows that the position does not have
Information does not show weights, and information 0 and 1 is to indicate information weights rather than logic state in quantifying logic, and 0 and 1 as with dividend right letter
Breath respectively have oneself occupy " weights line " or " range value ", indicate information when 0 with dividend right line is got higher, show the position have weights 0. in
It is that 0 bit line is got higher, shows that its information weights is 0, display is without information when which is lower.Weights 0 are not shown, rather than tradition is anticipated
Zero or low in justice.
3：The value of information is indicated with range value and position power
With the amplification value of information carrier indicate information state and weighted value method we make width weigh method, when information is any
The amplification value at quarter is just called width weights, and information is just called width weighted code in the list of all sample magnitude weights of certain period.
With the position weight of information carrier indicate information state and numerical values recited method we make position weigh method, information
The weight of carrier any position is just called a weights, and the spatial information that position weights are rearranged by prescription order is just called position power
Code.
4：Quantization logic fetter by logical relation therefore has abundant operation relation and output, can be take greatly, take it is small,
Different value with, with value and, different value or together value or compared with, add, subtract, multiplication and division, many way of outputs such as side by side, different output sides
Method determines the different function of logic circuit.The different function of same circuit can judge that offer is efficiently various to the evaluation and test of information and sentence
Determine tool.
5：The computing circuit of position power type quantization logic does not need dedicated tandem circuit design, is with traditional logic circuit
It simple, effective, reliable can realize multi valued logic operation and multi-system arithmetic operator, especially be easy to modular circuit framework
Implementation particularly suitable for current large scale integrated circuit.
6：Width power type quantization logic circuit needs the design of tandem circuit, so generating a series of and two-valued function completely not
Same basic circuit.
The multivalue mutual excitation quantization register of this part invention quantization logic is to utilize the similar excitation side with two-value trigger
Method realizes that the multivalue width of multilevel information storage weighs information register part.
The multivalue mutual excitation quantization register for quantifying logic is with two by patent application " quantify the multivalue width adaptability in tactics of logic
Mend the multivalue width adaptability in tactics described in device and mend device " composition, it is characterised in that：Two multivalue width adaptability in tactics are mended device and are set up in parallel, and described is more
The input terminal that value width adaptability in tactics mends device 1 is R, and output end is Q1, and the input terminal that the multivalue width adaptability in tactics mends device 2 is S, and output end is
Q2, the input terminal R for multivalue width adaptability in tactics being mended device 1 are connected on the output end Q2 of multivalue width adaptability in tactics benefit device 2, and multivalue width adaptability in tactics is mended device
2 input terminal S is connected to multivalue width adaptability in tactics and mends on the output end Q1 of device 1, and the multivalue width adaptability in tactics mends 1 multivalue width adaptability in tactics of device and mends device
2 input terminal R, S is the Complementary input structure excitation end of register, and the multivalue width adaptability in tactics mends 1 multivalue width adaptability in tactics of device and mends the defeated of device 2
Outlet Q1, Q2 are the complementary output ends of register.
The multivalue width adaptability in tactics for quantifying logic based on patent application mends the multivalue feature of device, and mending device with multivalue width adaptability in tactics is formed
Three value mutual excitation multivalue registers, four value mutual excitation multivalue registers, five value mutual excitation multivalue registers, six value mutual excitations are more
Value register, seven value mutual excitation multivalue registers, eight value mutual excitation multivalue registers, nine value mutual excitation multivalue registers, ten values
Mutual excitation multivalue register, N value mutual excitation multivalue registers.
Position power quantizer involved by the application of this part refers to application：
(1) " quantization logic multivalue highly resistance make an uproar position power quantizer "
(2) " quantizer is weighed in the pervasive position of multivalue of quantization logic "
(3) " quantizer is weighed in the wide type position of multivalue tune of quantization logic "
The circuit.
Width power quantizer involved by the application of this part refers to application：
(1) " quantization logic multivalue highly resistance make an uproar width power quantizer "
(2) " the pervasive width of multivalue of quantization logic weighs quantizer "
(3) " the wide type width of multivalue tune of quantization logic weighs quantizer "
The circuit.
Description of the drawings
Fig. 1 is that device is mended in the change described in application " the multivalue width adaptability in tactics of quantization logic mends device "
Fig. 2 is the connection method of multivalue mutual excitation multivalue register
Five value mutual excitation multivalue registers of Fig. 3
Fig. 4 is ten value mutual excitation multivalue registers
Fig. 5 is the symbol description figure used in each application documents, mainly illustrates the meaning of symbol and the specific application come from
Physical circuit corresponding to file and symbol.
Embodiment
With reference to Fig. 3, two five value width adaptability in tactics to be mended device 1 and 2 and are set up in parallel, the input terminal that five value width adaptability in tactics mend device 1 is R,
Output end is Q1, and the input terminal that five value width adaptability in tactics mend device 2 is S, and output end is Q2, and the input terminal R for five value width adaptability in tactics being mended device 1 connects
On the output end Q2 for mending device 2 to five value width adaptability in tactics, the input terminal S for five value width adaptability in tactics being mended device 2 is connected to five value width adaptability in tactics benefit device 1
On output end Q1, mends device 1 with five value width adaptability in tactics and five value width adaptability in tactics mend the Complementary input structure of input terminal R, S as register of device 2
End is encouraged, the complementary output end of output end Q1, Q2 as register that 1 five value width adaptability in tactics of device mends device 2 is mended with five value width adaptability in tactics.I.e.
Constitute five value mutual excitation registers.
With reference to Fig. 4, two ten value width adaptability in tactics to be mended device 1 and 2 and are set up in parallel, the input terminal that ten value width adaptability in tactics mend device 1 is R,
Output end is Q1, and the input terminal that ten value width adaptability in tactics mend device 2 is S, and output end is Q2, and the input terminal R for ten value width adaptability in tactics being mended device 1 connects
On the output end Q2 for mending device 2 to ten value width adaptability in tactics, the input terminal S for ten value width adaptability in tactics being mended device 2 is connected to ten value width adaptability in tactics benefit device 1
On output end Q1, mends device 1 with ten value width adaptability in tactics and ten value width adaptability in tactics mend the Complementary input structure of input terminal R, S as register of device 2
End is encouraged, the complementary output end of output end Q1, Q2 as register that 10 value width adaptability in tactics of device mends device 2 is mended with ten value width adaptability in tactics.I.e.
Constitute ten value mutual excitation registers.
With reference to Fig. 4, two N value width adaptability in tactics are mended device 1 and 2 and are set up in parallel, the input terminal that N value width adaptability in tactics mends device 1 is R, defeated
Outlet is Q1, and the input terminal that N value width adaptability in tactics mends device 2 is S, and output end is Q2, and the input terminal R for N value width adaptability in tactics being mended device 1 is connected to N
It is worth width adaptability in tactics to mend on the output end Q2 of device 2, the input terminal S for N value width adaptability in tactics being mended device 2 is connected to the output end that N value width adaptability in tactics mends device 1
On Q1, mends device 1 with N value width adaptability in tactics and N value width adaptability in tactics mends the Complementary input structure excitation end of input terminal R, S as register of device 2, use
N value width adaptability in tactics mends device 1, and N value width adaptability in tactics mends the complementary output end of output end Q1, Q2 as register of device 2.It is mutual to constitute N values
Encourage register.
Claims (2)
1. the multivalue mutual excitation quantization register of quantization logic is the multivalue width adaptability in tactics benefit for quantifying logic by patent application with two
Multivalue width adaptability in tactics described in device mends device composition, it is characterised in that：Two multivalue width adaptability in tactics are mended device and are set up in parallel, the multivalue width
The input terminal that adaptability in tactics mends device 1 is R, and output end is Q1, and the input terminal that the multivalue width adaptability in tactics mends device 2 is S, and output end is Q2,
The input terminal R for multivalue width adaptability in tactics being mended device 1 is connected on the output end Q2 of multivalue width adaptability in tactics benefit device 2, and multivalue width adaptability in tactics is mended device 2
Input terminal S is connected to multivalue width adaptability in tactics and mends on the output end Q1 of device 1, and the multivalue width adaptability in tactics mends 1 multivalue width adaptability in tactics of device and mends device 2
Input terminal R, S are the Complementary input structure excitation ends of register, and the multivalue width adaptability in tactics mends the output that 1 multivalue width adaptability in tactics of device mends device 2
Q1 is held, Q2 is the complementary output end of register.
2. according to claim 1, it is characterised in that：The multivalue width adaptability in tactics for quantifying logic based on patent application mends the multivalue spy of device
Sign mends the three value mutual excitation multivalue registers that device is formed, four value mutual excitation multivalue registers with multivalue width adaptability in tactics, and five values mutually swash
Encourage multivalue register, six value mutual excitation multivalue registers, seven value mutual excitation multivalue registers, eight value mutual excitation multivalue registers,
Nine value mutual excitation multivalue registers, ten value mutual excitation multivalue registers, N value mutual excitation multivalue registers.
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| CN201710205918.3A CN108628579A (en) | 2017-03-24 | 2017-03-24 | The multivalue mutual excitation for quantifying logic quantifies register |
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| CN201710205918.3A CN108628579A (en) | 2017-03-24 | 2017-03-24 | The multivalue mutual excitation for quantifying logic quantifies register |
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