CN108628586A - Quantify the multivalue high stability width weight register of logic - Google Patents

Abstract

The multivalue high stability width weight register of quantization logic is to weigh quantizer by position, and a width weighs quantizer, multiple two-value register groups at, it is characterised in that：Position is weighed the position power output 0,1,2 of quantizer ... the power output of each position of n is preserved with two value register Q, has several positions power lines just to use several two value registers, every position power line one two value register of connection, N items position power N number of two value register of line, i.e.,：Position power line 0 is connected to the data input pin of the 0th two value registers, position power line 1 is connected to the data input pin of the 1st two value registers, ... position power line n is connected to the data input pin of n-th of two value registers, the data output end Q0 of two value registers, Q1, Q2, ... Qn is sequentially connected to the position power input line 0 of width power quantizer, 1,2, ... on .n, input terminal of the simulation width power input terminal as width weight register of quantizer is weighed in the position, and the width weighs output end of the width power output end as width weight register of quantizer.

Description

Quantify the multivalue high stability width weight register of logic

Technical field

The present invention relates to field of computer technology, specifically realize one of underlying hardware of multivalue computer " quantization logic Multivalue high stability width weight register "

Technical background

Computers all so far and its relevant digital display circuit are all two-values, and multivalue is calculated in spite of many excellent Point, but because of the key hardware without supporting multi-value operation, so development is extremely slow, it may be said that and multivalue computer is especially The realization of decade computer is almost nil, and in light of this situation, I has proposed a kind of simple and effective multivalue and calculate in fact Circuit is applied to be especially the effective ways of ten values calculating and be especially the adding of ten values with two-value hardware realization multivalue, subtract, multiply, the calculation removed The Key Circuit of art operation and its logical operation is called " quantization logic " and its circuit, referring specifically to patent application (201710023530.1 201710023529.9 201710023528.4 201710024248.5 201710024246.6 201710024247.0), there are two types of information patterns for quantization logic tool itself, and one is positions to weigh information pattern, and one is width power to believe Breath pattern, the physical circuit under two kinds of information patterns also have bigger difference, are then position power information and width power information in real work Convert mutually it is each use the chief, the numerical operation in relation to multilevel information is dependent on position power information, but the performance of natural information is most It is analog information, the position for then obtaining standard is weighed and width power information will be the key that circuit trend is substantially applied, moreover width power is believed The multilevel storage method of breath is also that we are desired.

Invention content

" quantization logic " is that the label information generated after being quantified with analog information carries out logical operation as operator, is deduced, The flogic system of judgement

Quantify the simple understanding of logic

The method that mark value continuous, fuzzy, after chaos information quantization carries out logical operation as input and output is just named Quantization logic is done, realizes that the circuit of its operation is just called quantization logic circuit, then quantifies the input preamble part of logic circuit Most of is quantizer or the weights line being quantized.Postposition output par, c is that quantization weight line or quantization width weigh line.

Quantization logic has used the basic thought of two-valued function and multi valued logic or even fuzzy logic, and with simple and effective Be orientated circuit with two-value and realize the Key Circuit of multivalue and its fuzzy logic so that be only limited to simple two in logic original paper It is same to form multivalue and its fuzzy logical operation circuit in the case of kind state, especially quantify the compatible operation of logic Fundamentally solve the problems, such as multi-value operation, deposit with the method for quantization deposit, to open computing device of new generation Update level road.The bustling various operation method of quantization logic can provide effective hardware support to the development of artificial intelligence.

Quantify logic circuit for two-valued function circuit, structure is more complicated, but I believe that in ultra-large collection At under the support of circuit engineering, the machine that is more than two-value computing device by being continuing effort to may be implemented performance.

Quantifying logic circuit, there are two types of circuit implementing methods, and one is transported as input/output information with amplitude weights " width power type quantifies logic circuit " calculated, another kind are that as input/output information, " position power type quantifies logic with position weight Circuit " can be " width power type " in practice, can also be " position power type ", can also be " mixed type ".

The numerical value representation method of position power type quantization logic

It is called position power table with one group of method that spatially position weight of the line of parallel arranged or point indicates numerical values recited Show that method, position indication have the property that：

1, the quantity of spatial parallelism arranging line is identical with using magnitude carry system, and binary number is indicated with two lines, three into System indicates with three lines ... quinary indicates with five lines ... the decimal systems indicate that N systems are indicated with N line with ten lines.

2, the voltage on line is that high level is effective, and low level or 0 level indicate invalid.Vice versa.

3, uniquely there was only a line in one group of line at any time, remaining line is locked into invalid state for high level.

Width power type quantifies logic value representation method

1, it is that amplitude information is quantized into multiple isolated numerical value with equal difference attribute and indicates to weigh with the value that width, which weighs information, I.e. one arithmetic progression of composition is sized in width weights by the amplitude information of weight

2, the ordered series of numbers maxitem of its Quantitatively Selecting of width power information indicates scale.

3, general natural number 0,1,2 ... it is the optimal selection that weight indicates

Quantifying the essential characteristic of logic is

1：It is that logic " state " and information " power " are detached first to quantify logic, and the combination form of logic ensures that logic is closed Be is complete correct, and the weights of information are attached in logic state and not by logic state restrict, are believed with abundant displaying Colourful combination performance relationship is ceased, this method actually people are using but are being the failure to detach, such as：Pick up certain One analog information first has to detection with or without information (logic detection), then just evaluates and tests metric width weights.Obvious information Whether there is or not being logic judgment, and the magnitude of information is then numerical metric, and the meaning of the two is different.Once presentation of information " having " is patrolled The state of collecting, i.e., to complete logical operation, and the colorful variation of information amplitude later is not limited by logic state " having ".

2：Operation is carried out using " having " "None" Information sign, " having " "None" Information sign is different from the high and low of two value informations Information, most apparent difference is that two value informations take two logical symbols 0 and 1 of height, 0 indicates low, and 1 indicates high, and two kinds of shapes of height State is both logic state and binary number value information, and quantifies logic and indicate logic state, " having " and two with " having " and "None" There is information in corresponding display position of height of value logic, and to show its scale numerical value weights, and "None" then shows that the position does not have Information does not show weights, and information 0 and 1 is to indicate information weights rather than logic state in quantifying logic, and 0 and 1 as with dividend right letter Breath respectively have oneself occupy " weights line " or " range value ", indicate information when 0 with dividend right line is got higher, show the position have weights 0. in It is that 0 bit line is got higher, shows that its information weights is 0, display is without information when which is lower.Weights 0 are not shown, rather than tradition is anticipated Zero or low in justice.

3：The value of information is indicated with range value and position power

With the amplification value of information carrier indicate information state and weighted value method we make width weigh method, when information is any The amplification value at quarter is just called width weights, and information is just called width weighted code in the list of all sample magnitude weights of certain period.

With the position weight of information carrier indicate information state and numerical values recited method we make position weigh method, information The weight of carrier any position is just called a weights, and the spatial information that position weights are rearranged by prescription order is just called position power Code.

4：Quantization logic fetter by logical relation therefore has abundant operation relation and output, can be take greatly, take it is small, Different value with, with value and, different value or together value or compared with, add, subtract, multiplication and division, many way of outputs such as side by side, different output sides Method determines the different function of logic circuit.The different function of same circuit can judge that offer is efficiently various to the evaluation and test of information and sentence Determine tool.

5：The computing circuit of position power type quantization logic does not need dedicated tandem circuit design, is with traditional logic circuit It simple, effective, reliable can realize multi valued logic operation and multi-system arithmetic operator, especially be easy to modular circuit framework Implementation particularly suitable for current large scale integrated circuit.

6：Width power type quantization logic circuit needs the design of tandem circuit, so generating a series of and two-valued function completely not Same basic circuit.

The multivalue high stability width weight register of this part invention quantization logic is deposited using the high stability of two value registers The device that energy storage power stores width power information.

The multivalue high stability width weight register of quantization logic is to weigh quantizer by a position, and a width weighs quantizer, more A two-value register group at, it is characterised in that：Position is weighed the position power output 0,1,2 of quantizer ... each position power output of n It is preserved with two value register Q, has several position power lines just with several two value registers, every position is weighed one two-value of line connection and posted N number of two value register of line is weighed in storage, N items position, i.e.,：Position power line 0 is connected to the data input pin of the 0th two value registers, position Power line 1 is connected to the data input pin of the 1st two value registers ... position power line n is connected to the number of n-th of two value registers According to input terminal, data output end Q0, Q1, the Q2 of two value registers ... Qn is sequentially connected to the position power input of width power quantizer Line 0,1,2 ... on .n, input terminal of the simulation width power input terminal as width weight register of quantizer is weighed in the position, described Width weighs output end of the width power output end as width weight register of quantizer.

The multivalue feature that quantizer and multivalue width weigh quantizer is weighed based on multivalue position, and quantizer and more is weighed in the multivalue position Three value high stability width weight registers of the multivalue high stability width weight register that value width power quantizer is formed, four value high stables Property width weight register, five value high stability width weight registers, six value high stability width weight registers, seven value high stability width power post Storage, eight value high stability width weight registers, nine value high stability width weight registers, ten value high stability width weight registers, N values High stability width weight register.

Position power quantizer involved by the application of this part refers to application：

(1) " quantization logic multivalue highly resistance make an uproar position power quantizer "

(2) " quantizer is weighed in the pervasive position of multivalue of quantization logic "

(3) " quantizer is weighed in the wide type position of multivalue tune of quantization logic "

The circuit.

Width power quantizer involved by the application of this part refers to application：

(1) " quantization logic multivalue highly resistance make an uproar width power quantizer "

(2) " the pervasive width of multivalue of quantization logic weighs quantizer "

(3) " the wide type width of multivalue tune of quantization logic weighs quantizer "

The circuit.

Description of the drawings

Fig. 1 is three value high stability width weight registers

Fig. 2 is four value high stability width weight registers

Fig. 3 is five value high stability width weight registers

Fig. 4 is six value high stability width weight registers

Fig. 5 is ten value high stability width weight registers

Embodiment

Referring to Fig.1, three value high stability width weight registers are to weigh quantizer, a three value width power quantization by a three value positions Device, three two-value register groups are at each position power for position being weighed the position power output 0,1,2 of quantizer exports two value registers Q is preserved, i.e., three value positions is weighed three output 0,1,2 three two value registers Q0, Q1, the Q2 of quantizer, stored, Q0, The output of Q1, Q2 are connected to three positions power input terminal of width power quantizer, and the input terminal that quantizer is weighed with position is defeated as register Enter end, the output end of quantizer is weighed as output with width.

With reference to Fig. 2, referring to Fig.1, four value high stability width weight registers are to weigh quantizer, four values by a four value positions Width weighs quantizer, and four two-value register groups are at each position power output for position being weighed the position power output 0,1,2,3 of quantizer is used Two value register Q are preserved, i.e., four value positions are weighed four output 0,1,2,3 three two value registers Q0, the Q1 of quantizer, Q2, Q3 are stored, Q0, Q1, and the output of Q2, Q3 are connected to four positions power input terminal of width power quantizer, and the defeated of quantizer is weighed with position Enter end as register input terminal, the output end of quantizer is weighed as output with width.

With reference to Fig. 3, five value high stability width weight registers are to weigh quantizer, a five value width power quantization by a five value positions Device, five two-value register groups are at each position power output for position being weighed the position power output 0,1,2,3,4 of quantizer is posted with two-value Storage Q is preserved, i.e., five value positions is weighed five output 0,1,2,3,4 five two value registers Q0, Q1, the Q2 of quantizer, Q3, Q4 are stored, Q0, Q1, Q2, Q3, and the output of Q4 is connected to five positions power input terminal of width power quantizer, and quantizer is weighed with position Input terminal weighs the output end of quantizer as output as register input terminal, with width.

With reference to Fig. 4, six value high stability width weight registers are to weigh quantizer, a six value width power quantization by a six value positions Device, six two-value register groups are at output two-value is weighed in each position for position being weighed the position power output 0,1,2,3,4,5 of quantizer Register Q is preserved, i.e., six value positions is weighed six output 0,1,2,3,4,5 six two value registers Q0, the Q1 of quantizer, Q2, Q3, Q4, Q5 are stored, Q0, Q1, Q2, Q3, and the output of Q4, Q5 are connected to six positions power input terminal of width power quantizer, with position The input terminal of quantizer is weighed as register input terminal, the output end of quantizer is weighed as output with width.

With reference to Fig. 4, ten value high stability width weight registers are to weigh quantizer, a ten value width power quantization by a ten value positions Device, ten two-value register groups are at each position power for position being weighed the position power output 0,1,2,3,4,5,6,7,8,9 of quantizer is defeated Go out and preserved with two value register Q, i.e., ten outputs 0,1,2,3,4,5,6,7,8,9 of quantizer is weighed with ten in ten value positions Two value register Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9 storages, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8's, Q9 is defeated Go out to be connected to a position power input terminal of width power quantizer, the input terminal for weighing quantizer with position is weighed as register input terminal with width The output end of quantizer is as output.

Claims (2)

1. the multivalue high stability width weight register of quantization logic is to weigh quantizer by a position, a width weighs quantizer, multiple Two-value register group at, it is characterised in that：Position is weighed the position power output 0,1,2 of quantizer ... each position power output of n is used Two value register Q are preserved, and have several position power lines just with several two value registers, every position one two-value deposit of power line connection N number of two value register of line is weighed in device, N items position, i.e.,：Position power line 0 is connected to the data input pin of the 0th two value registers, position power Line 1 is connected to the data input pin of the 1st two value registers ... position power line n is connected to the data of n-th of two value registers Input terminal, data output end Q0, Q1, the Q2 of two value registers ... Qn is sequentially connected to the position power input line of width power quantizer 0,1,2 ... on .n, the simulation width that quantizer is weighed in the position weighs input terminal as the input terminal of width weight register, the width Weigh output end of the width power output end as width weight register of quantizer.

2. according to claim 1, it is characterised in that：Quantizer is weighed based on multivalue position and multivalue width weighs the multivalue feature of quantizer, Three values of the multivalue high stability width weight register that the multivalue position power quantizer and multivalue width power quantizer is formed are high steady Qualitative width weight register, four value high stability width weight registers, five value high stability width weight registers, six value high stability width power Register, seven value high stability width weight registers, eight value high stability width weight registers, nine value high stability width weight registers, Ten value high stability width weight registers, N value high stability width weight registers.