CN108270433A

CN108270433A - The output design and assignment method of multivalue quantizer

Info

Publication number: CN108270433A
Application number: CN201710024246.6A
Authority: CN
Inventors: 胡五生
Original assignee: Individual
Current assignee: Individual
Priority date: 2017-01-03
Filing date: 2017-01-03
Publication date: 2018-07-10

Abstract

" the output design and assignment method of multivalue quantizer " it is characterized in that：With several PNP triodes Q0, Q1, Q2, ... Qn is as output driving pipe, Q0, Q1, Q2 ... the emitter of Qn driving tubes and the claim 5 of patent 00105165.2,00105162.8 claim 3, each output terminal F1, F2, F3 described in 00105164.4 claim 4, ... ..Fn connects, Q0, Q1, Q2, ... the base stage of Qn driving tubes interconnects and accesses the anode+ref of reference power source, Q0, Q1, Q2, ... each collector of Qn forms open collector output, OC0, OC1, OC2....OCn output are formed successively.OC0, OC1, OC2....OCn.Output line rearranges one group of output line group with serial number by its serial number, its " weight " value is demarcated with the continuous sequentially number of line group, so that serial number calibration weighted value and line group position belonging to weighted value overlap, described one group of line be exactly standard " position power " export.

Description

The output design and assignment method of multivalue quantizer

Technical field

The present invention relates to field of computer technology, specifically realize that " multivalue quantifies one of underlying hardware of multivalue computer The output design and assignment method of device "

Technical background

Computers all so far and its relevant digital display circuit are all two-values, and multivalue is calculated in spite of many excellent Point, but because of the key hardware without supporting multi-value operation, so development is extremely slow, it may be said that and multivalue computer is particularly The realization of decade computer is almost nil, and in light of this situation, it is real that the present invention proposes that a kind of simple and effective multivalue calculates Circuit is applied to be particularly the effective ways of ten values calculating and be particularly the adding of ten values with two-value hardware realization multivalue, subtract, multiply, the calculation removed Art operation and its Key Circuit of logical operation are called " quantization logic " and its circuit.

Invention content

" quantization logic " is that the label information generated after being quantified with analog information carries out logical operation as operator, is deduced, The flogic system of judgement

Quantify the simple understanding of logic

The method that mark value continuous, fuzzy, after chaos information quantization carries out logical operation as input and output is just named Quantization logic is done, realizes that the circuit of its operation is just called quantization logic circuit, then quantifies the input preamble part of logic circuit Most of weights lines for being quantizer or being quantized.Postposition output par, c weighs line for quantization weight line or quantization width.

Quantization logic has used the basic thought of two-valued function and multi valued logic or even fuzzy logic, and with simple and effective There is two-value orientation circuit to realize the Key Circuit of multivalue and its fuzzy logic so that be only limited to simple two in logic original paper It is similary to form multivalue and its fuzzy logical operation circuit in the case of kind state, particularly quantify the compatible operation of logic Fundamentally solve the problems, such as multi-value operation, deposit with the method for quantization deposit, so as to open computing device of new generation Update level road.The bustling various operation method of quantization logic can provide effective hardware support to the development of artificial intelligence.

Quantify logic circuit for two-valued function circuit, structure is more complicated, but I believe that in ultra-large collection Into under the support of circuit engineering, it can realize that performance is more than the machine of two-value computing device by being continuing effort to.

Quantifying logic circuit, there are two types of circuit implementing methods, and one kind is to be transported with amplitude weights as input/output information " width power type quantifies logic circuit " calculated, another kind are that as input/output information, " position power type quantifies logic with position weight Circuit ",

Can be " width power type " or " position power type " or " mixed type " in practice.

The numerical value representation method of position power type quantization logic

It is called position power table with one group of method that spatially position weight of the line of parallel arranged or point represents numerical values recited Show method, position indication has the property that：

1, the quantity of spatial parallelism arranging line is identical with using magnitude carry system, and binary number is represented with two lines, three into System represents with three lines ... quinary represents with five lines ... the decimal systems represent that N systems are represented with N line with ten lines.

2, the voltage on line is effective for high level, and low level or 0 level represent invalid.Vice versa.

3, uniquely there was only a line in one group of line at any time, remaining line is locked into invalid state for high level.

Quantifying the essential characteristic of logic is

1：It is that logic " state " and information " power " are detached first to quantify logic, and the combination form of logic ensures that logic is closed Be is complete correct, and the weights of information are attached in logic state and not by logic state restrict, are believed with abundant displaying Colourful combination performance relationship is ceased, this method actually people are using but are being the failure to detach, such as：Pick up certain One analog information first has to detection with or without information (logic detection), then just evaluates and tests metric width weights.Obvious information It is logic judgment to whether there is, and the magnitude of information is then numerical metric, and the meaning of the two is different.Once presentation of information " having " is patrolled The state of collecting, i.e., to complete logical operation, and the colorful variation of information amplitude later is not limited by logic state " having ".

2：Operation is carried out using " having " "None" Information sign, " having " "None" Information sign is different from the high and low of two value informations Information, most apparent difference is that two value informations take two logical symbols 0 and 1,0 of height to represent low, 1 represents high, and two kinds of shapes of height State is both logic state and binary number value information, and quantifies logic and represent logic state, " having " and two with " having " and "None" There is information in corresponding display position of height of value logic, and so as to show its scale numerical value weights, and "None" then shows that the position does not have Information does not show weights, and information 0 and 1 is to represent information weights rather than logic state in logic is quantified, and 0 and 1 as with dividend right letter Breath respectively have oneself occupy " weights line " or " range value ", indicate information when 0 with dividend right line increases, show the position have weights 0. in It is that 0 bit line increases, it is 0 to show its information weights, and display is without information when which is lower.Not aobvious weights 0 rather than tradition meaning Zero or low in justice.

3：The value of information is represented with range value and position power

With the amplification value of information carrier represent information state and weighted value method we width is made to weigh method, when information is any The amplification value at quarter is just called width weights, and information is just called width weighted code in the list of all sample magnitude weights of certain period.

With the position weight of information carrier represent information state and numerical values recited method we position is made to weigh method, information The weight of carrier any position is just called a weights, and the spatial information that position weights are rearranged by prescription order is just called position power Code.

4：Quantization logic fetter by logical relation therefore has abundant operation relation and output, can be take greatly, take it is small, Different value with, with value and, different value or together value or compared with, add, subtract, multiplication and division, many way of outputs such as side by side, different output sides Method determines the different function of logic circuit.The different function of same circuit can judge that offer is efficiently various to the evaluation and test of information and sentence Determine tool.

5：Quantization logic circuit does not need to the design of dedicated tandem circuit, with traditional logic circuit can simply, it is effective, It is reliable to realize multi valued logic operation and multi-system arithmetic operator, particularly it is easy to modular circuit framework particularly suitable for working as The implementation of modern large scale integrated circuit.

All analog informations are converted to digital information by quantizer, most of operations based on analog information originally Operation can be carried out with digital information, quantizer can be quantized into analog information multilevel information more than two-value and two-value, For these multilevel informations by certain regularly arranged and artificial imparting standard and value, thus can become multi-value operation can Energy.

Of the invention " the output design and assignment method of multivalue quantizer " it is characterized in that：With several PNP triodes Q0, Q1, Q2 ... Qn is as output driving pipe, Q0, Q1, Q2 ... the emitter of Qn driving tubes and the right of patent 00105165.2 It is required that 5,00105162.8 claim 3, each output terminal F1, F2, F3 described in 00105164.4 claim 4, ... ..Fn connects, Q0, Q1, Q2 ... the base stage of Qn driving tubes interconnects and accesses anode+ref, Q0, the Q1 of reference power source, Q2 ... each collector of Qn forms open collector output, forms OC0, OC1, OC2....OCn output successively.OC0, OC1, OC2....OCn.Output line rearranges one group of output line group with serial number by its serial number, continuous suitable with line group Secondary number demarcates its " weight " value so that and the weighted value belonging to the weighted value of serial number calibration and line group position overlaps, and described one Group line is exactly that " the position power " of standard exports, Q0, Q1, the Q2 ... each collector of Qn is sequentially ingressed into R0, R1, R2 ... ..Rn, Q0, Q1, Q2 ... the collector of Qn respectively and R0, R1, R2 ... one end of ..Rn connects, R0, R1, R2 ... the ..Rn other ends are grounded, respectively from Q0, Q1, Q2 ... the collector of Qn and R0, R1, R2 ... the tie point of ..Rn draws Go out and export OC0, OC1, OC2....OCn.The OC0, OC1, OC2....OCn.Output line rearranges one by its serial number Output line group of the group with serial number demarcates its " weight " value so that the power of serial number calibration with the continuous sequentially number of line group Weighted value belonging to weight values and line group position overlaps, and described one group of line is exactly " position power " output of standard.

The carry-out bit power line group individual segmentation is formed the line that one group of remaining with unique high state is low state Group or point group, one group of line or point represent a number, the item number of line or the number of point are identical with used operation scale, two into System two lines or two parallel arrangeds represent (a0, a1), ternary represented with three lines or three parallel arrangeds (a0, A1, a2) ... quinary represents (a0, a1, a2, a3, a4) with five lines or five parallel arrangeds ... the decimal systems are used Ten lines or ten parallel arrangeds represent (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9), and so on, line or point can Number positional numbers represent its weights, and the weight of high state line represents effective weights of this group of line, remaining low state line in one group of line Invalid state is locked into, every position power line can carry pull down resistor.

The hair of threshold test in three kinds of quantizers described in patent 00105165.2 00105162.8 00105164.4 Emitter resistance 31,32......3n are changed to constant-current supply A0, A1, A2.....An.

Collector output electricity in three kinds of quantizers described in patent 00105165.2 00105162.8 00105164.4 Resistance 91,92 ... ..9n is changed to constant-current supply I0, I1, I2....In.

" the output design and assignment method of multivalue quantizer " of the invention and patent application " quantization logic circuit and its operation Method " " multivalue register "." multi-system arithmetic unit assigns meaning fractal algorithm circuit "." multi-system arithmetic unit marks generative circuit ". " multi-system arithmetic operator device ".And patent and application 00105165.2.00105162.8.00105164.4.00102057.9. Composition multi-system computer particularly decade computer Key Circuit together

Description of the drawings

Fig. 1, Fig. 4 are the output improvement figures of patent 00105165.2.

Fig. 2, Fig. 5 are the output improvement figures of patent 00105162.8.

Fig. 3, Fig. 6 are the output improvement figures of patent 00105164.4.

Fig. 7 is quantizer quantization assignment graph and symbol.

Fig. 8 is two-value to ten value assignment quantization line group picture and represents graphical diagram.

Embodiment

With reference to Fig. 1, with several PNP triodes Q0, Q1, Q2 ... Qn is as output driving pipe, Q0, Q1, Q2 ... Qn F1, F2, F3 in 00105165.2 Fig. 8 of emitter and patent of driving tube ... ..Fn connects, Q0, Q1, Q2 ... Qn drives The base stage of pipe interconnects and accesses anode+ref, Q0, Q1, the Q2 of reference power source ... each collector of Qn forms collector and opens Road exports, and forms OC0, OC1, OC2....OCn output successively.

With reference to Fig. 2, with several PNP triodes Q0, Q1, Q2 ... Qn is as output driving pipe, Q0, Q1, Q2 ... Qn F1, F2, F3 in 00105162.8 Fig. 8 of emitter and patent of driving tube ... ..Fn connects, Q0, Q1, Q2 ... Qn drives The base stage of pipe interconnects and accesses anode+ref, Q0, Q1, the Q2 of reference power source ... each collector of Qn forms collector and opens Road exports, and forms OC0, OC1, OC2....OCn output successively.

With reference to Fig. 3, with several PNP triodes Q0, Q1, Q2 ... Qn is as output driving pipe, Q0, Q1, Q2 ... Qn F1, F2, F3 in 00105164.4 Fig. 8 of emitter and patent of driving tube ... ..Fn connects, Q0, Q1, Q2 ... Qn drives The base stage of pipe interconnects and accesses anode+ref, Q0, Q1, the Q2 of reference power source ... each collector of Qn forms collector and opens Road exports, and forms OC0, OC1, OC2....OCn output successively.

With reference to Fig. 4, Fig. 5, Fig. 6, Q0, Q1, the Q2 ... each collector of Qn is sequentially ingressed into R0, R1, R2 ... ..Rn, Q0, Q1, Q2 ... the collector of Qn respectively and R0, R1, R2 ... one end of ..Rn connects, R0, R1, R2 ... the ..Rn other ends are grounded, respectively from Q0, Q1, Q2 ... the collector of Qn and R0, R1, R2 ... the tie point of ..Rn draws Go out and export OC0, OC1, OC2....OCn；

With reference to Fig. 7, whole output lines of quantizer are divided and are proposed, form one group of independent lines group with scale, and right Line group is numbered successively：A0, a1, a2 ... an, wherein n+1 are scales, the digital number of every line and its line Position weight overlaps, and an only line is high level in one group of line, remaining is all low level.The position weight of high level line is exactly Effective weights of this group of line.

The binary system defined according to the method for Fig. 7 with reference to Fig. 8, ternary, the quaternary, quinary, senary, seven into System, octal system, novenary, decimal digit power line and its symbol.

Claims

Of the invention 1. " improvement of multivalue quantizer and standard output method " it is characterized in that：With several PNP triodes Q0, Q1, Q2 ... Qn is as output driving pipe, Q0, Q1, Q2 ... the emitter of Qn driving tubes and the right of patent 00105165.2 It is required that 5,00105162.8 claim 3, each output terminal F1, F2, F3 described in 00105164.4 claim 4, ... ..Fn connects, Q0, Q1, Q2 ... the base stage of Qn driving tubes interconnects and accesses anode+ref, Q0, the Q1 of reference power source, Q2 ... each collector of Qn forms open collector output, forms OC0, OC1, OC2....OCn output successively.OC0, OC1, OC2....OCn.Output line rearranges one group of output line group with serial number by its serial number, continuous suitable with line group Secondary number demarcates its " weight " value so that and the weighted value belonging to the weighted value of serial number calibration and line group position overlaps, and described one Group line is exactly " position power " output of standard；Q0, Q1, the Q2 ... each collector of Qn is sequentially ingressed into R0, R1, R2 ... ..Rn, Q0, Q1, Q2 ... the collector of Qn respectively and R0, R1, R2 ... one end of ..Rn connects, R0, R1, R2 ... the ..Rn other ends are grounded, respectively from Q0, Q1, Q2 ... the collector of Qn and R0, R1, R2 ... the tie point of ..Rn draws Go out and export OC0, OC1, OC2....OCn；The OC0, OC1, OC2....OCn.Output line rearranges one by its serial number Output line group of the group with serial number demarcates its " weight " value so that the power of serial number calibration with the continuous sequentially number of line group Weighted value belonging to weight values and line group position overlaps, and described one group of line is exactly " position power " output of standard.
2. according to claim 1：Carry-out bit described in claim 1 power line group individual segmentation, which is formed one group, has unique high shape Remaining of state is the line group of low state or point group, and one group of line or point represent a number, the item number of line or the number of point and used Operation scale it is identical, binary system two lines or two parallel arrangeds represent i.e.：A0, a1, three lines of ternary or Three parallel arrangeds represent：A0, a1, a2 ... quinary is represented i.e. with five lines or five parallel arrangeds：A0, a1, A2, a3, a4 ... the decimal systems are represented i.e. with ten lines or ten parallel arrangeds：A0, a1, a2, a3, a4, a5, a6, a7, A8, a9, and so on N systems represented i.e. with N line：A0, a1, a2, a3......an；There are two types of desirable for each line or point tool The denumerable positional number of state, high state and low state, line or point represents its weights, and the weight of high state line represents in one group of line Effective weights of this group of line, remaining low state line are locked into invalid state, and every position power line can carry pull down resistor.