CN108270432A - Multi-system arithmetic unit marks generative circuit - Google Patents

Multi-system arithmetic unit marks generative circuit Download PDF

Info

Publication number
CN108270432A
CN108270432A CN201710023530.1A CN201710023530A CN108270432A CN 108270432 A CN108270432 A CN 108270432A CN 201710023530 A CN201710023530 A CN 201710023530A CN 108270432 A CN108270432 A CN 108270432A
Authority
CN
China
Prior art keywords
values
logic
quantization
entirely
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710023530.1A
Other languages
Chinese (zh)
Inventor
胡五生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201710023530.1A priority Critical patent/CN108270432A/en
Publication of CN108270432A publication Critical patent/CN108270432A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

Multi-system arithmetic unit label generative circuit is that (two-value is a0 each weights of two groups of position weighted codes with identical scale,A1 and b0,b1,Three values are a0,a1,A2 and b0,b1,B2... that ten values is a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,And b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,And so on),Respectively with traditional logic and logic gates y00,y01,The input of y02....ynn is attached combination,The input terminal and position weights a0b0 of y00 connects,The input terminal and a0b1 of y01 connects,The defeated and a0b2 of y02 connects,And so on until the input terminal of ynn and anbn connects,N+1 values are used scales,Form " quantization logic " full combinational logic array circuit,The logic circuit output is " label " information a0b0,a0b1,a0bn..a1b0,a1b1,...anbn.

Description

Multi-system arithmetic unit marks generative circuit
Technical field
The present invention relates to field of computer technology, specifically realize that one of underlying hardware of multivalue computer " transport by multi-system Calculate device label generative circuit "
Technical background
Computers all so far and its relevant digital display circuit are all two-values, and multivalue is calculated in spite of many excellent Point, but because of the key hardware without supporting multi-value operation, so development is extremely slow, it may be said that and multivalue computer is particularly The realization of decade computer is almost nil, and in light of this situation, it is real that the present invention proposes that a kind of simple and effective multivalue calculates Circuit is applied to be particularly the effective ways of ten values calculating and be particularly the adding of ten values with two-value hardware realization multivalue, subtract, multiply, the calculation removed Art operation and its Key Circuit of logical operation are called " quantization logic " and its circuit.
Invention content
" quantization logic " is that the label information generated after being quantified with analog information carries out logical operation as operator, is deduced, The flogic system of judgement
Quantify the simple understanding of logic
The method that mark value continuous, fuzzy, after chaos information quantization carries out logical operation as input and output is just named Quantization logic is done, realizes that the circuit of its operation is just called quantization logic circuit, then quantifies the input preamble part of logic circuit Most of weights lines for being quantizer or being quantized.Postposition output par, c weighs line for quantization weight line or quantization width.
Quantization logic has used the basic thought of two-valued function and multi valued logic or even fuzzy logic, and with simple and effective There is two-value orientation circuit to realize the Key Circuit of multivalue and its fuzzy logic so that be only limited to simple two in logic original paper It is similary to form multivalue and its fuzzy logical operation circuit in the case of kind state, particularly quantify the compatible operation of logic Fundamentally solve the problems, such as multi-value operation, deposit with the method for quantization deposit, so as to open computing device of new generation Update level road.The bustling various operation method of quantization logic can provide effective hardware support to the development of artificial intelligence.
Quantify logic circuit for two-valued function circuit, structure is more complicated, but I believe that in ultra-large collection Into under the support of circuit engineering, it can realize that performance is more than the machine of two-value computing device by being continuing effort to.
Quantifying logic circuit, there are two types of circuit implementing methods, and one kind is to be transported with amplitude weights as input/output information " width power type quantifies logic circuit " calculated, another kind are that as input/output information, " position power type quantifies logic with position weight Circuit ",
Can be " width power type " or " position power type " or " mixed type " in practice.
The numerical value representation method of position power type quantization logic
It is called position power table with one group of method that spatially position weight of the line of parallel arranged or point represents numerical values recited Show method, position indication has the property that：
1, the quantity of spatial parallelism arranging line is identical with using magnitude carry system, and binary number is represented with two lines, three into System represents with three lines ... quinary represents with five lines ... the decimal systems represent that N systems are represented with N line with ten lines.
2, the voltage on line is effective for high level, and low level or 0 level represent invalid.Vice versa.
3, uniquely there was only a line in one group of line at any time, remaining line is locked into invalid state for high level.
Quantifying the essential characteristic of logic is
1：It is that logic " state " and information " power " are detached first to quantify logic, and the combination form of logic ensures that logic is closed Be is complete correct, and the weights of information are attached in logic state and not by logic state restrict, are believed with abundant displaying Colourful combination performance relationship is ceased, this method actually people are using but are being the failure to detach, such as：Pick up certain One analog information first has to detection with or without information (logic detection), then just evaluates and tests metric width weights.Obvious information It is logic judgment to whether there is, and the magnitude of information is then numerical metric, and the meaning of the two is different.Once presentation of information " having " is patrolled The state of collecting, i.e., to complete logical operation, and the colorful variation of information amplitude later is not limited by logic state " having ".
2：Operation is carried out using " having " "None" Information sign, " having " "None" Information sign is different from the high and low of two value informations Information, most apparent difference is that two value informations take two logical symbols 0 and 1,0 of height to represent low, 1 represents high, and two kinds of shapes of height State is both logic state and binary number value information, and quantifies logic and represent logic state, " having " and two with " having " and "None" There is information in corresponding display position of height of value logic, and so as to show its scale numerical value weights, and "None" then shows that the position does not have Information does not show weights, and information 0 and 1 is to represent information weights rather than logic state in logic is quantified, and 0 and 1 as with dividend right letter Breath respectively have oneself occupy " weights line " or " range value ", indicate information when 0 with dividend right line increases, show the position have weights 0. in It is that 0 bit line increases, it is 0 to show its information weights, and display is without information when which is lower.Not aobvious weights 0 rather than tradition meaning Zero or low in justice.
3：The value of information is represented with range value and position power
With the amplification value of information carrier represent information state and weighted value method we width is made to weigh method, when information is any The amplification value at quarter is just called width weights, and information is just called width weighted code in the list of all sample magnitude weights of certain period.
With the position weight of information carrier represent information state and numerical values recited method we position is made to weigh method, information The weight of carrier any position is just called a weights, and the spatial information that position weights are rearranged by prescription order is just called position power Code.
4：Quantization logic fetter by logical relation therefore has abundant operation relation and output, can be take greatly, take it is small, Different value with, with value and, different value or together value or compared with, add, subtract, multiplication and division, many way of outputs such as side by side, different output sides Method determines the different function of logic circuit.The different function of same circuit can judge that offer is efficiently various to the evaluation and test of information and sentence Determine tool.
5：Quantization logic circuit does not need to the design of dedicated tandem circuit, with traditional logic circuit can simply, it is effective, It is reliable to realize multi valued logic operation and multi-system arithmetic operator, particularly it is easy to modular circuit framework particularly suitable for working as The implementation of modern large scale integrated circuit.
A kind of multi-system arithmetic unit label generative circuit weighs line by input bit and conventional logic circuit forms, position power Line is made of one group of line or point, this weighs the output that line can directly be quantizer or converter, can also be had by one group Remaining of unique high state is the line of low state or point composition, and one group of line or point represent a number, the item number of line or the number of point Identical with used operation scale, binary system two lines or two parallel arrangeds represent (a0, a1), and ternary is with three Bar line or three parallel arrangeds represent (a0, a1, a2) ... quinary represented with five lines or five parallel arrangeds (a0, A1, a2, a3, a4), the .. decimal systems represented with ten lines or ten parallel arrangeds (a0, a1, a2, a3, a4, a5, a6, a7, a8, A9), and so on, the denumerable positional number of high state line or point represents effective weights of this group of line, other power in low state Value line is pulled down resistance and clamps to invalid state,
The multi-system arithmetic unit label generative circuit is each weights two groups of position weighted codes with identical scale (two-value is a0, a1 and b0, b1, and three values are a0, a1, a2 and b0, and ten value of b1, b2... is a0, a1, a2, a3, a4, a5, A6, a7, a8, a9 and b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, and so on), respectively with traditional logic and logic The input of gate circuit y00, y01, y02....ynn are attached combination, and the input terminal and position weights a0b0 of y00 connect, y01's Input terminal and a0b1 connect, and the defeated and a0b2 of y02 connects, and so on until the input terminal of ynn and anbn connects, n+1 values are Used scale, composition " quantization logic " full combinational logic array circuit, logic circuit output is " mark Note " information a0b0, a0b1, a0bn..a1b0, a1b1 ... anbn, two-value to ten value label information such as following tables：
Two-value combines quantization logic output token table entirely
a0 a1
b0 a0b0 a1b0
b1 a0b1 a1b1
Three values combine quantization logic output token table entirely
a0 a1 a2
b0 a0b0 a1b0 a2b0
b1 a0b1 a1b1 a2b1
b2 a0b2 a1b2 a2b2
Four values combine quantization logic output token table entirely
a0 a1 a2 a3
b0 a0b0 a1b0 a2b0 a3b0
b1 a0b1 a1b1 a2b1 a3b1
b2 a0b2 a1b2 a2b2 a3b2
b3 a0b3 a1b3 a2b3 a3b3
Five value total heads combination quantization logic output token table
a0 a1 a2 a3 a4
b0 a0b0 a1b0 a2b0 a3b0 a4b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4
Six values combine quantization logic output token table entirely
a0 a1 a2 a3 a4 a5
b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4
b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5
Seven values combine quantization logic output token table entirely
a0 a1 a2 a3 a4 a5 a6
b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4
b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5
b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6
Eight values combine quantization logic output token table entirely
a0 a1 a2 a3 a4 a5 a6 a7
b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4
b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5
b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6
b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7
Nine values combine quantization logic output token table entirely
a0 a1 a2 a3 a4 a5 a6 a7 a8
b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0 a8b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4 a8b4
b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5 a8b5
b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6 a8b6
b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7 a867
b8 a0b8 a1b8 a2b8 a3b8 a4b8 a5b8 a6b8 a7b8 a8b8
Ten values combine quantization logic output token table entirely
a0 a1 a2 a3 a4 a5 a6 a7 a8 a9
b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0 a8b0 a9b0
b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1 a9b1
b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2 a9b2
b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3 a9b3
b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4 a8b4 a9b4
b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5 a8b5 a9b5
b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6 a8b6 a9b6
b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7 a8b7 a9b7
b8 a0b8 a1b8 a2b8 a3b8 a4b8 a5b8 a6b8 a7b8 a8b8 a9b8
b9 a0b9 a1b9 a2b9 a3b9 a4b9 a5b9 a6b9 a7b9 a8b9 a9b9
The logic array show two-value, three values, four values, five values, six values, seven values, eight values, nine values, ten values, to arbitrary value Logic array.
The present invention " multi-system arithmetic unit marks generative circuit " and patent application " quantization logic circuit and its operation method ". " the output design and assignment method of multivalue quantizer "." multivalue register "." multi-system arithmetic unit assigns meaning fractal algorithm circuit ". " multi-system arithmetic operator device ".And patent and application 00105165.2.00105162.8.00105164.4.00102057.9. Composition multi-system computer particularly decade computer Key Circuit together.
Description of the drawings
The full combinational logic label generative circuit of Fig. 1 two-values.
The full combinational logic label generative circuit of tri- values of Fig. 2.
The full combinational logic label generative circuit of tetra- values of Fig. 3.
The full combinational logic label generative circuit of ten values of Fig. 4.
Embodiment
With reference to Fig. 1, two-value position weighted code a0, a1 and b0, whole the combination a0b0, a0b1, a1b0 of b1, a1b1 is respectively with four The input connection of a two-value and door,
So that a0 connects an input of Y00, b0 connects another input of Y00.Y00 output tokens a0b0
So that a0 connects an input of Y01, b1 connects another input of Y01.Y01 output tokens a0b1
So that a1 connects an input of Y02, b0 connects another input of Y02.Y02 output tokens a1b0
So that a1 connects an input of Y03, b1 connects another input of Y03.Y03 output tokens a1b1
With reference to Fig. 2, three value position weighted code a0, a1, a2 and b0, b1, b2, it is whole combine a0b0, a0b1, a0b2, The input of a1b0, a1b1, a1b2, a2b0, a2b1, a2b2 respectively with nine two-values and door connects
So that a0 connects an input of Y00, b0 connects another input of Y00.Y00 output tokens a0b0
So that a0 connects an input of Y01, b1 connects another input of Y01.Y01 output tokens a0b1
So that a0 connects an input of Y02, b2 connects another input of Y02.Y02 output tokens a0b2
So that a1 connects an input of Y03, b0 connects another input of Y03.Y03 output tokens a1b0
So that a1 connects an input of Y04, b1 connects another input of Y04.Y04 output tokens a1b1
So that a1 connects an input of Y05, b2 connects another input of Y05.Y05 output tokens a1b2
So that a2 connects an input of Y06, b0 connects another input of Y06.Y06 output tokens a2b0
So that a2 connects an input of Y07, b1 connects another input of Y07.Y07 output tokens a2b1
So that a2 connects an input of Y08, b2 connects another input of Y08.Y08 output tokens a2b2
With reference to Fig. 3, Fig. 4, four values formed with above-mentioned same connection mode, five values, six values, seven values, eight values, nine values, Ten values and N value combinational logic circuits, it is used to be with door quantity：Four values are 16, five value positions 25, and six values are 36, seven values Position 49, eight value positions 64, nine value positions 81, ten values are 100, and N values are N*N.The label such as list of four to ten values output, Other multi-mark sets cannot be listed one by one.

Claims (2)

1. a kind of multi-system arithmetic unit label generative circuit weighs line by input bit and conventional logic circuit forms, position power line It is made of one group of line described in application " quantization logic circuit and its operation method " or point；
The multi-system arithmetic unit label generative circuit is each weights two-value two groups of position weighted codes with identical scale Be a0, a1 and b0, b1,
Three values are a0, a1, a2 and b0, b1, b2；
Four values are a0, a1, a2, a3 and b0, b1, b2, b3；
Five values are a0, a1, a2, a3, a4 and b0, b1, b2, b3, b4
Six values are a0, a1, a2, a3, a4, a5 and b0, b1, b2, b3, b4, b5
Seven values are a0, a1, a2, a3, a4, a5, a6 and b0, b1, b2, b3, b4, b5, b6
Eight values are a0, a1, a2, a3, a4, a5, a6, a7 and b0, b1, b2, b3, b4, b5, b6, b7
Nine values are a0, a1, a2, a3, a4, a5, a6, a7, a8 and b0, b1, b2, b3, b4, b5, b6, b7, b8
Ten values are a0, a1, a2, a3, a4, a5, a6, a7, a8, a9 and b0, b1, b2, b3, b4, b5, b6, b7, b8, b9,
N values and so on；Respectively with traditional logic and logic gates y00, the input of y01, y02....ynn connected It connects, the input terminal and position weights a0b0 of y00 connect, and the input terminal and a0b1 of y01 connect, and the defeated and a0b2 of y02 connects, successively class Push away until the input terminal of ynn and anbn connects, y00, y01, y02....ynn, whole output a0b0, a0b1, A0bn..a1b0, a1b1 ... anbn, the output of composition " entirely with " logic, n+1 values are used scales, by different carries The position power input of system forms " entirely with " logic circuit of " quantization logic " of different value, described " entirely with ", and logic circuit output is equal For " label " information a0b0, a0b1, a0bn..a1b0, a1b1 ... anbn, two-value to ten value output token information such as following tables：
Two-value quantization logic " entirely with " output token table
a0 a1 b0 a0b0 a1b0 b1 a0b1 a1b1
The quantization of three values logic " entirely with " output token table
a0 a1 a2 b0 a0b0 a1b0 a2b0 b1 a0b1 a1b1 a2b1 b2 a0b2 a1b2 a2b2
The quantization of four values logic " entirely with " output token table
a0 a1 a2 a3 b0 a0b0 a1b0 a2b0 a3b0 b1 a0b1 a1b1 a2b1 a3b1 b2 a0b2 a1b2 a2b2 a3b2 b3 a0b3 a1b3 a2b3 a3b3
The quantization of five values logic " entirely with " output token table
a0 a1 a2 a3 a4 b0 a0b0 a1b0 a2b0 a3b0 a4b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4
The quantization of six values logic " entirely with " output token table
a0 a1 a2 a3 a4 a5 b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5
The quantization of seven values logic " entirely with " output token table
a0 a1 a2 a3 a4 a5 a6 b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6
The quantization of eight values logic " entirely with " output token table
a0 a1 a2 a3 a4 a5 a6 a7 b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4 b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5 b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6 b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7
The quantization of nine values logic " entirely with " output token table
a0 a1 a2 a3 a4 a5 a6 a7 a8 b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0 a8b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4 a8b4 b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5 a8b5 b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6 a8b6 b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7 a8b7 b8 a0b8 a1b8 a2b8 a3b8 a4b8 a5b8 a6b8 a7b8 a8b8
The quantization of ten values logic " entirely with " output token table
a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 b0 a0b0 a1b0 a2b0 a3b0 a4b0 a5b0 a6b0 a7b0 a8b0 a9b0 b1 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1 a9b1 b2 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2 a9b2 b3 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3 a9b3 b4 a0b4 a1b4 a2b4 a3b4 a4b4 a5b4 a6b4 a7b4 a8b4 a9b4 b5 a0b5 a1b5 a2b5 a3b5 a4b5 a5b5 a6b5 a7b5 a8b5 a9b5 b6 a0b6 a1b6 a2b6 a3b6 a4b6 a5b6 a6b6 a7b6 a8b6 a9b6 b7 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7 a8b7 a9b7 b8 a0b8 a1b8 a2b8 a3b8 a4b8 a5b8 a6b8 a7b8 a8b8 a9b8 b9 a0b9 a1b9 a2b9 a3b9 a4b9 a5b9 a6b9 a7b9 a8b9 a9b9 。
2. according to claim 1：The logic array show two-value, three values, four values, five values, six values, seven values, eight values, nine values, Ten values, to arbitrary value " entirely with " logic array.
CN201710023530.1A 2017-01-03 2017-01-03 Multi-system arithmetic unit marks generative circuit Pending CN108270432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710023530.1A CN108270432A (en) 2017-01-03 2017-01-03 Multi-system arithmetic unit marks generative circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710023530.1A CN108270432A (en) 2017-01-03 2017-01-03 Multi-system arithmetic unit marks generative circuit

Publications (1)

Publication Number Publication Date
CN108270432A true CN108270432A (en) 2018-07-10

Family

ID=62771599

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710023530.1A Pending CN108270432A (en) 2017-01-03 2017-01-03 Multi-system arithmetic unit marks generative circuit

Country Status (1)

Country Link
CN (1) CN108270432A (en)

Similar Documents

Publication Publication Date Title
Morris Some theorems on sorting
Shao et al. First digit distribution of hadron full width
Cui et al. A parallel decimal multiplier using hybrid binary coded decimal (BCD) codes
CN108268241A (en) Multi-system arithmetic operator device
CN108270432A (en) Multi-system arithmetic unit marks generative circuit
Liu et al. Hiding multiple solutions in a hard 3-SAT formula
CN108270431A (en) Quantify logic circuit and its operation method
CN108268239A (en) Multi-system arithmetic unit assigns meaning fractal algorithm circuit
CN101349967B (en) CBSA hardware adder of addition and subtraction non-difference paralleling calculation and design method thereof
CN108268240A (en) Multivalue register
Koç A Tutorial on p-adic Arithmetic
CN108628586A (en) Quantify the multivalue high stability width weight register of logic
CN108628579A (en) The multivalue mutual excitation for quantifying logic quantifies register
Krepkiy The sandpile groups of chain-cyclic graphs
Nowak et al. Nuclear operators on Cb (X, E) and the strict topology
Qi et al. Novel parity-preserving designs of reversible 4-bit comparator
Xue et al. Number of proper paths in edge-colored hypercubes
Hallberg et al. An order-invariant real-to-integer conversion sum
CN108628582A (en) Quantify the multivalue width power and position power compatible type quantizer of logic, become and mend device, register
Li A mirror theorem between Landau–Ginzburg models
CN108631770A (en) The multivalue width adaptability in tactics for quantifying logic mends device
CN108270433A (en) The output design and assignment method of multivalue quantizer
Gou et al. Weak solutions for fractional differential equations via Henstock–Kurzweil–Pettis integrals
Harikrishna et al. Compressors Using Modified Sorting and Parallel Counting
CN108628583A (en) Weigh transmitter in the multivalue position for quantifying logic

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination