CN101349967B - CBSA hardware adder of addition and subtraction non-difference paralleling calculation and design method thereof - Google Patents

Abstract

The invention discloses a plug-minus indifferent parallel operation adder and a design method thereof. The adder is composed of a single-bit logic parallel operation unit adder modules, wherein each unit adder module comprises xi, yi, zi, xi, yi, zi registers; (xi^yi)v(xi^zi)v(yi^zi) logic operation units, a xiyiz logic operation unit, a xiyizi logic operation unit, a (xi^yi)v(xi^zi)v(yi^zi) logicoperation unit, and a (-(s1i^(-s0i))) logic operation unit, four logic OR gates connected with logic units for attaining data ci, si, s, c, and output bit registers connected with each logic AND gate. The plug-minus indifferent parallel operation adder has the advantages of improved calculation efficiency and physical attach resistance.

Description

The CBSA hardware adder and the method for designing of the parallel computation of plus-minus method indifference

Technical field

The present invention relates in the digital processing system, realize having the addition of overlength position and the parallel design method of subtraction simultaneously, particularly relate to hardware adder and method for designing thereof that addition and subtraction are carried out the indifference parallel computation.

Background technology

In many digital processing systems, need have the addition and the subtraction (position and bit have identical meanings) of overlength position herein.For example, the public-key encryptosystem in the information safety system, as RSA and ECC algorithm, its realization relates to the hundreds of position even arrives several kilobits above addition and subtraction.And the basic processing unit of CPU has only tens (as 8,16,32 etc.) in the common computer, and the addition or the subtraction that utilize them to handle so big number will be very slow, obviously can not satisfy the quick response requirement in the application.Therefore,, need design to have the addition of overlength position and the hardware adder of subtraction, utilize it to assist to finish the realization of High Speed of public-key encryptosystem in order to improve system handles speed.Improve system handles speed, utilize hardware component to realize the calculating of complicated algorithm usually.In the reality, the algorithm computing finally all is converted into addition and fundamental operation such as subtraction repeatedly.Totalizer is one of core component of computing machine, and the speed of totalizer processing plus-minus method is determining the operational performance of computing machine.And the calculated performance of any totalizer all depends on its employed computing method.

The additional calculation of utilizing hardware adder to come realization of High Speed overlength position is often used the bit parallel computing technique.Realize the totalizer that parallel addition calculates at present, refer in particular to carry save adder (Carry Save Adders), below brief note is for CSA, and basic thought is by simple logic Parallel Implementation repeatedly add operations of signless integer arbitrarily such as bit distance, " or " and " with ".Two data are all exported in each CSA computing, a carry information C who contains everybody, and another contains everybody XOR information S.Because CSA has realized exempting to link carry addition, be particularly suitable for the hardware adder design of ultra-long data.If normally used processor unit is the m bit, carry out the CSA computing of L bit length, then its speed is to use more than L/m times of common addition process device.

If use mark '

Operation that ' expression step-by-step ' XOR ' operation, ' ∧ ' represent step-by-step ' with ', ' ∨ ' represent step-by-step ' or ' operate.To the nonnegative integer X of input, Y, Z, carry out CSA calculate CSA (X, Y, Z)=(C S), is output as C and S, satisfies 2C+S=X+Y+Z, and then the computing formula of CSA is:

C＝(X∧Y)∨(X∧Z)∨(Y∧Z)， $S=X\⊕Y\⊕Z.$

As seen, each arithmetic operation in more than calculating all can step-by-step (promptly by bit) parallel mode carry out from formula, and the CSA addition of three nonnegative integers of bit length can be finished calculating in one claps arbitrarily.For carrying out the operation of addition many times repeatedly, can finish efficiently by CSA; Its shortcoming is the parallel addition that can only be used for signless integer, can't carry out bit parallel to signed number and calculate, and promptly can't do subtraction.

In addition, be to guarantee the safety of public-key encryptosystem, should manage to reduce or avoid its implementation procedure information leakage (such as, utilize time, the energy information revealed in the calculating process, can analyze key).And operations such as the comparison in the computation process, carry, borrow, usually victim is used to the time of carrying out, the energy information analysis is used.Public-key encryptosystem is realized, relates to addition and subtraction, can not be finished by CSA merely.Therefore, in the existing accelerator hardware of public-key encryptosystem realizes,, inevitably in computation process, introduced operations such as comparison, carry, borrow, brought the adverse effect of secure context for being suitable for subtraction.For this reason, seek, design, realize highly-parallel, unified addition and subtraction, overlength position totalizer hardware, can effectively avoid the information leakage of computation process, become the target that people yearn for.

The unified universal method that realizes addition and subtraction, the common addition that is to use the complementary operation rule to carry out, but it is not a parallel method.The better method that another attempts parallel processing addition and subtraction is Radix-2Signed Digit method, below abbreviates it as SD2, and it is that to utilize radix be 2 signed number word code technology, realizes the limited parallel work-flow of addition and subtraction.SD2 uses digital collection

Wherein Expression-1.A SD2 integer A=[a _N-1... a ₁a ₀] $(a_i\∈\left\{\widetilde{1,}\mathrm{0,}1\right\})$ Value be ∑ _{I=0 ..., n-1}a _i2 ⁱIf B=[b _N-1... b ₁b ₀], S=[s _N-1... s ₁s ₀], calculate S=A+B.When any two SD2 count A and B and carry out addition, each the digital s among the output result _iAll need search a rule list obtains.Rely on this rule list, each digital s _iCan be according to being operated preceding two digital a in the number _I-2And a _I-1And b _I-2And b _I-1Calculate.Because this forward direction dependence, the SD2 method is not the parallel method of step-by-step or bit computing.

In addition, can unify to realize that the method for addition and subtraction also has the RSD method, but it not a parallel method.Its thought is: an integer X is expressed as two positive integer x ₊And x _-, and X=x is arranged ₊-x _-If X=is (x ₊, x _-), Y=(y ₊, y _-), X-Y=(x then ₊, x _-)-(y ₊, y _-)=(x ₊, x _-)+(y _-, y ₊), X+Y=(x ₊, x _-)+(y ₊, y _-).The RSD method can be according to x ₊And x _-Most significant digit directly carry out the comparison of two integers, saved subtrahend and mend to have handled problems, and do not worried carry and borrow problem in the operating process.Its shortcoming is, must be to two positive integer x of division ₊And x _-Carry out positive negative flag, when carrying out addition and subtraction process repeatedly, data need constantly compare and transform between positive negative flag.If utilize the CSA concurrent technique to realize RSD, then each positive negative flag needs two migrations of independently carrying out big flow between the CSA processing module, and its hardware implementation efficiency is very low.

Summary is got up, and the SD2 method has the limited dependence of forward direction bit (need introduce table look-up etc.), has reduced hardware parallel processing efficient, has increased hardware and has realized difficulty; And complementary operation method and RSD method do not have concurrency.The analysis showed that by above, be used for unifying to realize the whole bag of tricks and the hardware adder thereof of addition and subtraction at present, is not truly addition and design of subtraction indifference and the strict parallel computation of being undertaken by bit.How realizing that the without differences of addition and subtraction handle, and strictly carry out parallel computation by bit, can satisfy the randomness of computation process again, promptly is the technical barrier that the present invention will solve.

Summary of the invention

The objective of the invention is to: totalizer and method for designing thereof for the user provides the parallel computation of a kind of plus-minus method indifference, realize addition and subtraction indifference are handled and parallel computation.This totalizer strictness realizes the addition and the subtraction of arbitrary integer by the bit parallel mode, and the randomness of computation process can be provided.Be applicable in the information safety system public-key encryptosystem, relate to the plus-minus method supercomputing of overlength position, reach the ability that improves system's operation efficiency and security simultaneously.

The objective of the invention is to realize by the enforcement following technical proposals:

The CBSA hardware adder of plus-minus method indifference parallel computation is characterized in that: be made up of the unit adder Module of the single-bit logical calculated of 64 bit parallels at least; Wherein every bit location adder Module includes following logical organization:

Input bit is respectively

3 unsigned number registers,

Input bit is respectively

3 redundant digit registers,

Respectively with 3 The unsigned number register connects, carries out

Logical operation, export this carry information Logical block-1,

Respectively with 3

The unsigned number register connects, carries out

Logical operation, export this XOR information

Logical block-2,

Respectively with 3 The redundant digit register connects, carries out

Logical operation, export this XOR information ${s1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$ Logical block-3,

Respectively with 3

The redundant digit register connects, carries out

Logical operation, export this carry information Logical block-4,

Be connected with logical block-3 with logical block-2 respectively, with the input s0 _iWith s1 _iCarry out (～(s1 _i∧ (～s0 _i))) logical operation, output result be t _i=(～(s1 _i∧ (～s0 _i))) logical block-5,

Be connected with logical block-5 with logical block-1 respectively, with the input c0 _iWith t _iCarry out the logical computing, obtain

Logical AND gate-1,

Be connected with logical block-5 with logical block-2 respectively, with the input s0 _iWith t _iCarry out the logical computing, obtain

Logical AND gate-2,

Be connected with logical block-5 with logical block-3 respectively, with the input s1 _iWith t _iCarry out the logical computing, obtain

Logical AND gate-3,

Be connected with logical block-5 with logical block-4 respectively, with the input c1 _iWith t _iCarry out the logical computing, obtain

Logical AND gate-4,

The output bit that is connected with logical AND gate-1 is Register,

The output bit that is connected with logical AND gate-2 is

Register,

The output bit that is connected with logical AND gate-3 is

Register,

And the output bit that is connected with logical AND gate-4 is Register;

Described Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) unsigned number $\stackrel{`}{X}=({\stackrel{`}{x}}_{n-1}...{\stackrel{`}{x}}_1{\stackrel{`}{x}}_0),\stackrel{`}{Y}=({\stackrel{`}{y}}_{n-1}...{\stackrel{`}{y}}_1{\stackrel{`}{y}}_0),\stackrel{`}{Z}=({\stackrel{`}{z}}_{n-1}...{\stackrel{`}{z}}_1{\stackrel{`}{z}}_0)$ The i bit, wherein ${\stackrel{`}{x}}_i\∈\left\{\mathrm{0,1}\right\},{\stackrel{`}{y}}_i\∈\left\{\mathrm{0,1}\right\},{\stackrel{`}{z}}_i\∈\left\{\mathrm{0,1}\right\};$ I=0,1 ..., n-1, n are any positive integer greater than 64; Described unsigned number

Be the numerical table formula after all signs of removing each digital front in corresponding X, Y, the Z binary number;

Described

Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) redundant digit $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0),\tilde{Y}=({\tilde{y}}_{n-1}...{\tilde{y}}_1{\tilde{y}}_0),\tilde{Z}=({\tilde{z}}_{n-1}...{\tilde{z}}_1{\tilde{z}}_0)$ The i bit, wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\},{\tilde{y}}_i\∈\left\{\mathrm{0,1}\right\},{\tilde{z}}_i\∈\left\{\mathrm{0,1}\right\};$ I=0,1 ..., n-1, n are any positive integer greater than 64; Described redundant digit

For being 1 for negative bit labeling, otherwise be labeled as 0 to each the digital previous symbol in corresponding X, Y, the Z binary number, and the numerical table formula;

Operational symbol wherein ' ∧ ' expression step-by-step logic ' with ' computing, ' ∨ ' expression step-by-step logic ' or ' computing,

Expression step-by-step logic ' XOR ' computing, "～" expression step-by-step logic ' negate ' computing (being 1=～0,0=～1).

Other totalizer of utilizing described CBSA hardware adder to constitute:

1. the realization modular multiplication computing unit (T+a that utilizes described CBSA hardware adder to constitute _iB+q _iFour advancing two and go out totalizer N)=(T1+T2+X1+X2) includes:

4 difference stored data T1, T2, X1, the output register of X2,

Respectively with output register T1, T2, the first order CBSA hardware adder that X1 connects,

The second level CBSA hardware adder that is connected with first order CBSA hardware adder two output terminals and X2 output register respectively,

Stored data T1 that is connected with second level CBSA hardware adder two output terminals and the output register unit of stored data T2 (T1, T2),

And control output register unit (T1, clk clock signal of system T2) and rst totalizer reset signal.

2. the realization modular multiplication computing unit (T1+T2+a that utilizes described CBSA hardware adder to constitute _iB1+a _iB2+q _iFive advancing two and go out totalizer N) includes:

5 difference stored data T1, T2, a _iB1, a _iB2, q _iThe output register of N,

Respectively with output register T1, T2, a _iThe first order CBSA hardware adder that B1 connects,

Respectively with first order CBSA hardware adder two output terminals and a _iThe second level CBSA hardware adder that the B2 output register connects,

Respectively with second level CBSA hardware adder two output terminals and q _iThe third level CBSA hardware adder that the N output register connects,

Stored data T1 that is connected with third level CBSA hardware adder two output terminals and the output register unit of stored data T2 (T1, T2),

And control output register unit (T1, clk clock signal of system T2) and rst totalizer reset signal.

Realize the method for designing of the CBSA hardware adder of plus-minus method indifference of the present invention parallel computation, following steps arranged:

The first step is determined the design object of CBSA totalizer, be realize calculating CBSA (X, Y, Z)=(C S), and satisfies C+S=X+Y+Z, for this reason:

1. arbitrary integer X, Y, Z is shown as X=(± x with 2 system numerical tables _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀), x wherein _i∈ 0,1}, y _i∈ 0,1}, z _i∈ 0,1}, and the X=∑ is arranged _{I=0 ..., n-1}(± x _i2 ⁱ), the Y=∑ _{I=..., n-1}(± y _i2 ⁱ), the Z=∑ _{I=0 ..., n-1}(± z _i2 ⁱ);

2. count X=(± x for three 2 systems of any input _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀) and Z=(± z _N-1... ± z ₁± z ₀), (C is that 2 systems are counted C=(± c S) to its output result equally after CBSA calculates _N-1... ± c ₁± c ₀) and S=(± s _N-1... ± s ₁± s ₀);

In second step, binary number unsigned number tabular form and redundant digit tabular form are set

1) binary number unsigned number tabular form is set

To any bigit X=(± x _N-1... ± x ₁± x ₀), remove all signs of each digital front, obtain the unsigned number tabular form of X, it is designated as , wherein

2) the redundant digit tabular form of binary number is set to any bigit X=(± x _N-1... ± x ₁± x ₀), x _iEach digital previous symbol be 1 for negative bit labeling, otherwise be labeled as 0, then obtain the redundant digit tabular form of X, and be designated as $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0),$ Wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\};$

In the 3rd step, to importing any long integer X in position, Y and Z carry out CBSA and calculate

With any long bigit X in position of input, Y, the unsigned number tabular form of Z and redundant digit tabular form are designated as respectively

CBSA (X, Y, Z)=(C, calculating process S) is as follows:

(1) at first parallel computation

With

CSA is the computing of the carry save adder known, obtains:

C0＝(c0 _n-1...c0 ₁c0 ₀)，S0＝(s0 _n-1...s0 ₁s0 ₀)，c0 _i，s0 _i∈{0，1}；

C1＝(c1 _n-1...c1 ₁c1 ₀)，S1＝(s1 _n-1...s1 ₁s1 ₀)，c1 _i，s1 _i∈{0，1}；

(2) provide CBSA (X, Y, Z)=(C, S) result's unsigned number tabular form and redundant digit tabular form are designated as respectively

With

And

With

Wherein:

$\tilde{C}=({\tilde{c}}_{n-1}...{\tilde{c}}_1{\tilde{c}}_0),$ $\tilde{S}=({\tilde{s}}_{n-1}...{\tilde{s}}_1{\tilde{s}}_0),$ ${\tilde{c}}_i,{\tilde{s}}_i\∈\left\{\mathrm{0,1}\right\}$

(3) C0 as a result that utilizes above-mentioned calculating process (1) to obtain, S0, C1, each digital bit of S1 is by the following output that calculates CBSA

Each digital bit:

i＝0，...，n-1.

Wherein operational symbol '～' is represented the step-by-step logic ' negate ' (being 1=～0,0=～1), ' ∧ ' expression step-by-step logic ' with, operation; Consider in the information safety system public-key encryptosystem that relate to the plus-minus method supercomputing needs of overlength position, positive integer n gets 64 at least; As seen, in CBSA calculated, the computing in (3) step was undertaken by the bit method is parallel fully, a CBSA computing, and each single-bit logical block can be finished in a beat simultaneously.

In the 4th step, the recovery of CBSA output data is handled

In fact, system utilizes its last result of calculation after carrying out limited number of time CBSA calculating

Recover C=(± c as follows _N-1... ± c ± c ₀) and S=(± s _N-1... ± s ₁± s ₀):

(1) $c_i={\stackrel{`}{c}}_i,s_i={\stackrel{`}{s}}_i,$ i＝0，...，n-1.

(2) judge symbol: if ${\tilde{c}}_i=0,$ C then _iThe symbol of front is '+', otherwise c _iThe symbol of front is '-'; If ${\tilde{s}}_i=0,$ S then _iThe symbol of front is '+', otherwise s _iThe symbol of front is '-'.

By the method for the 4th step (1), promptly obtain CBSA (X, Y, Z) output C and S with (2);

(3) utilize usual method to obtain net result W=C+S again.

Can obviously find out from above respectively going on foot: realization CBSA (X, Y Z) calculate, and key is to carry out following simple logic computing by the method in the 3rd step:

${s0}_i={\stackrel{`}{x}}_i\⊕{\stackrel{`}{y}}_i\⊕{\stackrel{`}{z}}_i$

${s1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$

t _i＝(～(s1 _i∧(～s0 _i)))

i＝0，...，n-1.

i＝0，...，n-1.

i＝0，...，n-1.

i＝0，...，n-1.

Wherein preceding 5 computings are according to the 3rd step

Each input bit

With the 3rd step (1) respectively export bit c0 _i, s0 _i, c1 _i, s1 _iGiven simple logic computing, can carry out the design of following CBSA hardware adder according to these 9 logical operations:

1. according to the input data of calculating The design relevant register;

The difference stored data

Three registers be called the unsigned number register, stored data respectively

Three registers be called the redundant digit register;

2. according to the input data

, carry out

Logical operation, output data c0 _i, design is called the simple logic circuit structure of logical block-1, and sets up

Register is connected with logical block-1, obtain logical block-1 respectively with

Three circuit structures that register connects;

3. according to the input data

, carry out

Logical operation, output data s0 _i, design is called the simple logic circuit structure of logical block-2, and sets up

Register is connected with logical block-2, obtain logical block-2 respectively with

Three circuit structures that register connects;

4. according to the input data

Carry out

Logical operation, output data s1 _i, design is called the simple logic circuit structure of logical block-3, and sets up

Register is connected with logical block-3, obtain logical block-3 respectively with

Three circuit structures that register connects;

5. according to the input data

Carry out

Logical operation, output data c1 _i, design is called the simple logic circuit structure of logical block-4, and sets up

Register is connected with logical block-4, obtain logical block-4 respectively with

Three circuit structures that register connects;

6. according to input data s0 _iAnd s1 _i, carry out (～(s1 _i∧ (～s0 _i))) logical operation, output data t _i, design is called the simple logic circuit structure of logical block-5, and set up logical block-5 respectively with being connected of logical block-2 and logical block-3, obtain the circuit structure that logical block-5 is connected with logical block-3 with logical block-2 respectively;

7. according to input data c0 _iAnd t _i, carry out c0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

, design is called the simple logic circuit structure of logical AND gate-1, and set up logical AND gate-1 respectively with being connected of logical block-1 and logical block-5, obtain the circuit structure that logical AND gate-1 is connected with logical block-5 with logical block-1 respectively;

8. according to input data s0 _iAnd t _i, carry out s0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

, design is called the simple logic circuit structure of logical AND gate-2, and set up logical AND gate-2 respectively with being connected of logical block-2 and logical block-5, obtain the circuit structure that logical AND gate-2 is connected with logical block-5 with logical block-2 respectively;

9. according to input data s1 _iAnd t _i, carry out s1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

, design is called the simple logic circuit structure of logical AND gate-3, and set up logical AND gate-3 respectively with being connected of logical block-3 and logical block-5, obtain the circuit structure that logical AND gate-3 is connected with logical block-5 with logical block-3 respectively;

10. according to input data c1 _iAnd t _i, carry out c1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

, design is called the simple logic circuit structure of logical AND gate-4, and set up logical AND gate-4 respectively with being connected of logical block-4 and logical block-5, obtain the circuit structure that logical AND gate-4 is connected with logical block-5 with logical block-4 respectively;

According to logical AND gate-1 output data

, logical AND gate-2 output data , logical AND gate-3 output data

, logical AND gate-4 output data , the output bit register of storing these data respectively is set;

Finish these steps, just obtained realizing the CBSA hardware adder of plus-minus method indifference parallel computation.

Find out by this adder structure: to importing any long integer X in position, Y and Z, carrying out plus-minus method indifference parallel C BSA calculates, be exactly in fact the logical operation that utilizes the step-by-step of scale-of-two input data to carry out, the unit adder Module of the n that obtains walking abreast a single-bit logical calculated, the hardware circuit composition of each unit adder Module is provided by Fig. 1, and Fig. 2 has provided the adder Module structural drawing that the n bit parallel calculates.

Outstanding advantage of the present invention is:

The indifference processing and the parallel computation of addition and subtraction have been realized.Its characteristics can be summarized as: strictness realizes the addition and the subtraction of arbitrary integer by the bit parallel mode, and the randomness of computation process can be provided.Be specially adapted to carry out the digital processing system that overlength position plus-minus method calculates, as utilize totalizer of the present invention to assist to finish the safety high speed realization of public-key encryptosystem, can improve efficient and security that public key cryptography is realized greatly.

Particularly, hardware adder and method for designing thereof that addition and subtraction are carried out the indifference parallel computation that the present invention provides, its major advantage has:

(1) but the addition and the subtraction of overlength integer are carried out in the indifference strange land, adapt to any integer as input, the high-speed parallel that carries out addition and subtraction with simple logic calculates.Carry out in a large number in the arithmetic processing system of addition and subtraction at needs,, then need the subtraction that runs into is carried out individual processing, will lower parallel efficiency calculation significantly if utilize CSA to carry out parallel computation.CBSA of the present invention carries out parallel computation with the plus-minus method unification, has avoided the translation process between the plus-minus method, its operation efficiency can be improved significantly.

(2), unsigned number tabular form and the redundant digit tabular form that provide among the present invention about data, can select different unsigned numbers and redundant digit at random.Select for different unsigned numbers and redundant digit, will obtain the various combination of two output valves of CBSA, this makes the assailant accurately to survey or the relevant information of acquisition algorithm in calculating process.Therefore, the CBSA totalizer that provides among the present invention can provide the randomness of computation process.

(3), utilize CBSA totalizer of the present invention, carry out addition and the computing of subtraction indifference and random paralleling computing power, exempt operations such as comparison between common additive operation and subtraction, carry, borrow, condition control, can significantly improve the anti-physical attacks ability of hardware adder.

Description of drawings

Fig. 1 is the unit totalizer meter building-block of logic of single-bit logical calculated of the present invention.

Fig. 2 is the totalizer composition diagram that n bit parallel of the present invention calculates.

Fig. 3 carries out calling computing unit (T+a repeatedly in the overlength bit Montgomery Algorithm _iB+q _iN)=(T1+T2+a _iB1+a _iB2+q _i5 advancing 2 and go out the adder designs block diagram N).

Fig. 4 is used for calculating (T+a _iB+q _i4 advancing 2 and go out the adder designs block diagram N)=(T1+T2+X1+X2).

Embodiment

The CBSA hardware adder of a kind of plus-minus method indifference parallel computation is made up of the unit adder Module of the single-bit logical calculated of 64 bit parallels at least; Wherein every bit location adder Module has following logical organization:

Input bit is respectively

3 unsigned number registers,

Input bit is respectively

3 redundant digit registers,

Respectively with 3

The unsigned number register connects, carries out

Logical operation, export this carry information

Logical block-1,

Respectively with 3

The unsigned number register connects, carries out

Logical operation, export this XOR information Logical block-2,

Respectively with 3

The redundant digit register connects, carries out Logical operation, export this XOR information ${s1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$ Logical block-3,

Respectively with 3

The redundant digit register connects, carries out

Logical operation, export this carry information

Logical block-4,

Be connected with logical block-3 with logical block-2 respectively, with the input data s0 _iWith s1 _iCarry out (～(s1 _i∧ (～s0 _i))) logical operation, output result data be t _i=(～(s1 _i∧ (～s0 _i))) logical block-5,

Be connected with logical block-5 with logical block-1 respectively, with the input data c0 _iWith t _iCarry out the logical computing, obtain result data Logical AND gate-1,

Be connected with logical block-5 with logical block-2 respectively, with the input data s0 _iWith t _iCarry out the logical computing, obtain result data Logical AND gate-2,

Be connected with logical block-5 with logical block-3 respectively, with the input data s1 _iWith t _iCarry out the logical computing, obtain result data

Logical AND gate-3,

Be connected with logical block-5 with logical block-4 respectively, with the input data c1 _iWith t _iCarry out the logical computing, obtain result data

Logical AND gate-4,

The output bit that is connected with logical AND gate-1

Register,

The output bit that is connected with logical AND gate-2

Register,

The output bit that is connected with logical AND gate-3 Register,

And the output bit that is connected with logical AND gate-4

Register;

Described

Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) unsigned number

The i bit, wherein

I=0,1 ..., n-1, n are any positive integer greater than 64; Described unsigned number

Be the numerical table formula after all signs of removing each digital front in corresponding X, Y, the Z binary number;

Described Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) redundant digit $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0),$ $\tilde{Y}=({\tilde{y}}_{n-1}...{\tilde{y}}_1{\tilde{y}}_0),$ $\tilde{Z}=({\tilde{z}}_{n-1}...{\tilde{z}}_1{\tilde{z}}_0)$ The i bit, wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\tilde{y}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\tilde{z}}_i\∈\left\{\mathrm{0,1}\right\};$ I=0,1 ..., n-1, n are any positive integer greater than 64; Described redundant digit

For being 1 for negative bit labeling, otherwise be labeled as 0 to each the digital previous symbol in corresponding X, Y, the Z binary number, and the numerical table formula;

Operational symbol wherein ' ∧ ' expression step-by-step logic ' with ' computing, ' ∨ ' expression step-by-step logic ' or ' computing, '

' expression step-by-step logic ' XOR ' computing, "～" expression step-by-step logic ' negate ' computing (being 1=～0,0=～1).

The method for designing of plus-minus method indifference parallel computation totalizer of the present invention has following steps:

The first step is determined the design object of CBSA totalizer, be realize calculating CBSA (X, Y, Z)=(C S), satisfies C+S=X+Y+Z, for this reason:

1. arbitrary integer X, Y, Z becomes X=(± x with 2 system numerical table formulas _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀), x wherein _i∈ 0,1}, y _i∈ 0,1}, z _i∈ 0,1}, and the X=∑ is arranged _{I=0 ..., n-1}(± x _i2 ⁱ), the Y=∑ _{I=0 ..., n-1}(± y _i2 ⁱ), the Z=∑ _{I=0 ..., n-1}(± z _i2 ⁱ);

2. count X=(± x for three 2 systems of any input _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀) and Z=(± z _N-1... ± z ₁± z ₀), its output result is that 2 systems are counted C=(± c equally after CBSA calculates _N-1... ± c ₁± c ₀) and S=(± s _N-1... ± s ₁± s ₀);

In second step, binary number unsigned number tabular form and redundant digit tabular form are set

1) binary number unsigned number tabular form is set

To any bigit X=(± x _N-1... ± x ₁± x ₀), remove all signs of each digital front, obtain the unsigned number tabular form of X, it is designated as

Wherein

2) the redundant digit tabular form of binary number is set

To any bigit X=(± x _N-1... ± x ₁± x ₀), x _iEach digital previous symbol be 1 for negative bit labeling, otherwise be labeled as 0, then obtain the redundant digit tabular form of X, and be designated as $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0),$ Wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\};$

In the 3rd step, to importing any long integer X in position, Y and z carry out CBSA and calculate

With any long integer X in position of input, Y, the unsigned number tabular form of Z and redundant digit tabular form are designated as respectively

CBSA (X, Y, Z)=(C, calculating process S) is as follows:

(1) at first parallel computation

With

CSA is the computing of the carry save adder known, obtains:

C0＝(c0 _n-1...c0 ₁c0 ₀)，S0＝(s0 _n-1...s0 ₁s0 ₀)，c0 _i，s0 _i∈{0，1}；

C1＝(c1 _n-1...c1 ₁c1 ₀)，S1＝(s1 _n-1...s1 ₁s1 ₀)，c1 _i，s1 _i∈{0，1}；

(2) provide CBSA (X, Y, Z)=(C, S) result's unsigned number tabular form and redundant digit tabular form are designated as respectively

With

And

With

Wherein:

$\tilde{C}=({\tilde{c}}_{n-1}...{\tilde{c}}_1{\tilde{c}}_0),$ $\tilde{S}=({\tilde{s}}_{n-1}...{\tilde{s}}_1{\tilde{s}}_0),$ ${\tilde{c}}_i,{\tilde{s}}_i\∈\left\{\mathrm{0,1}\right\}$

(3) C0 as a result that utilizes above-mentioned calculating process (1) to obtain, S0, C1, each digital bit of S1 is by the following output that calculates CBSA

Each digital bit:

Wherein operational symbol '～' expression step-by-step ' negate ' (being 1=～0,0=～1), ' ∧ ' represent step-by-step ' with ' operate; Consider in the information safety system public-key encryptosystem that relate to the plus-minus method supercomputing needs of overlength position, n gets 64 at least; As seen, in CBSA calculated, the computing of step 3 was undertaken by the bit method is parallel fully, and a CBSA computing can be finished in a beat simultaneously.

In the 4th step, the recovery of CBSA output data is handled

In fact, system utilizes its last result of calculation after carrying out limited number of time CBSA calculating Recover C=(± c as follows _N-1... ± c ± c ₀) and S=(± s _N-1... ± s ₁± s ₀):

(2) judge symbol: if ${\tilde{c}}_i=0,$ C then _iThe symbol of front is '+', otherwise c _iThe symbol of front is '-'; If ${\tilde{s}}_i=0,$ S then _iThe symbol of front is '+', otherwise s _iThe symbol of front is '-'.

Obtain CBSA (X, Y, Z) output C and S above;

(3) utilize usual method to obtain net result W=C+S again.

Can obviously find out from above respectively going on foot: realization CBSA (X, Y Z) calculate, and key is to carry out following simple logic computing by the method in the 3rd step:

${s1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$

t _i＝(～(s1 _i∧(～s0 _i)))

According to these logical operations, can carry out the design of following CBSA hardware adder:

1. according to the input data of calculating

The design relevant register; The difference stored data

Three registers be called the unsigned number register, stored data respectively

Three registers be called the redundant digit register;

2. according to the input data

Carry out

Logical operation, output data c0 _i, design is called the simple logic circuit structure of logical block-1, and sets up

The annexation of register and logical block-1, obtain logical block-1 respectively with

Three circuit structures that register connects;

3. according to the input data

Carry out

Logical operation, output data s0 _i, design is called the simple logic circuit structure of logical block-2, and sets up Register is connected with logical block-2, obtain logical block-2 respectively with

Three circuit structures that register connects;

4. according to the input data Carry out

Logical operation, output data s1 _i, design is called the simple logic circuit structure of logical block-3, and sets up

Register is connected with logical block-3, obtain logical block-3 respectively with

Three circuit structures that register connects;

5. according to the input data

Carry out

Logical operation, output data c1 _i, design is called the simple logic circuit structure of logical block-4, and sets up Register is connected with logical block-4, obtain logical block-4 respectively with Three circuit structures that register connects;

6. according to input data s0 _iAnd s1 _i, carry out (～(s1 _i∧ (～s0 _i))) logical operation, output data t _i, design is called the simple logic circuit structure of logical block-5, and set up logical block-5 respectively with being connected of logical block-2 and logical block-3, obtain the circuit structure that logical block-5 is connected with logical block-3 with logical block-2 respectively;

7. according to input data c0 _iAnd t _i, carry out c0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

, design is called the simple logic circuit structure of logical AND gate-1, and set up logical AND gate-1 respectively with being connected of logical block-1 and logical block-5, obtain the circuit structure that logical AND gate-1 is connected with logical block-5 with logical block-1 respectively;

8. according to input data s0 _iAnd t _i, carry out s0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-2, and set up logical AND gate-2 respectively with being connected of logical block-2 and logical block-5, obtain the circuit structure that logical AND gate-2 is connected with logical block-5 with logical block-2 respectively;

9. according to input data s1 _iAnd t _i, carry out s1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-3, and set up logical AND gate-3 respectively with being connected of logical block-3 and logical block-5, obtain the circuit structure that logical AND gate-3 is connected with logical block-5 with logical block-3 respectively;

10. according to input data c1 _iAnd t _i, carry out c1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-4, and set up logical AND gate-4 respectively with being connected of logical block-4 and logical block-5, obtain the circuit structure that logical AND gate-4 is connected with logical block-5 with logical block-4 respectively;

According to logical AND gate-1 output data

Logical AND gate-2 output data

Logical AND gate-3 output data , logical AND gate-4 output data

The output bit register of storing these data respectively is set;

Finish these steps, just obtained realizing the CBSA hardware adder of plus-minus method indifference parallel computation.

Provide CBSA hardware adder specification among the present invention below in conjunction with accompanying drawing 1 and accompanying drawing 2.

The unit totalizer of single-bit logical calculated of the present invention shown in Figure 1, mark 100～105 are 6 input bits of the single-bit computational logic of this totalizer

Register, wherein Register is the unsigned number register,

Register is the redundant digit register; 106 is logical block 1, and this unit will

The unsigned number of register output

Carry out

Logical operation, output data c0 _i107 is logical block 2, and this unit will

The unsigned number of register output

Carry out

Logical operation, output data s0 _i108 is logical block 3, and this unit will

The redundant digit of redundant digit register output

Carry out

Logical operation, output data s1 _i109 is logical block 4, and this unit will The redundant digit of redundant digit register output Carry out

Logical operation, output data c1 _i111 is logical block 5, and this unit is with the s0 of logical block-2 and logical block-3 output _iWith s1 _iCarry out (～(s1 _i∧ (～s0 _i))) logical operation, output data t _i=(～(s1 _i∧ (～s0 _i))); 112～115 is logic ' with ' door, wherein 112 is logic ' with ' door 1, it is with the c0 of logical block-1 and logical block-5 output _iWith t _iCarry out the logical computing, obtain data

113 is logical AND gate-2, and it is with the s0 of logical block-2 and logical block-5 output _iWith t _iCarry out the logical computing, obtain data

114 is logical AND gate-3, and it is with the s1 of logical block-3 and logical block-5 output _iWith t _iCarry out the logical computing, obtain data

115 is logical AND gate-4, and it is with the c1 of logical block-4 and logical block-5 output _iWith t _iCarry out the logical computing, obtain data

116～119 is 4 output bits of the single-bit computational logic of this totalizer

Register; Wherein, operational symbol ' ∧ ' presentation logic ' with ' computing, operational symbol ' ∨ ' presentation logic ' or ' computing, operational symbol '

' presentation logic ' XOR ' computing, operational symbol "～" presentation logic ' negate ' computing.

Fig. 2 is the totalizer composition diagram that n bit parallel of the present invention calculates, and is particularly suitable for the plus-minus method indifference parallel computation of overlength position, mark among the figure: 200～203 is three inputs of CBSA hardware adder data X, Y, n arranged side by side the input bit unit of Z; 204～207 is the bit unsigned number and the redundant digit register of n arranged side by side input bit unit; 208～211 is n arranged side by side CBSA single-bit computational logic, and its input is provided by 204～207 each register cell, and output is provided by 212～215 each register cell; 212～215 is the output of n arranged side by side CBSA single-bit computational logic; 216～219 is two output data C of CBSA hardware adder, n arranged side by side the output bit cell of S.

As shown in Figure 2, the CBSA hardware adder of plus-minus method indifference of the present invention parallel computation, unit adder Module by n single-bit logical calculated as shown in Figure 1 arranged side by side is formed, 200,204,208,212,216 have constituted the wherein unit adder Module of first single-bit logical calculated, 201,205,209,213,217 have constituted the wherein unit adder Module of second single-bit logical calculated, the rest may be inferred, and 203,207,211,215,219 have constituted the wherein unit adder Module of n piece single-bit logical calculated; Because each module arithmetic is independent fully, thereby the strictness of CBSA hardware adder realizes the addition and the subtraction of arbitrary integer by the bit parallel mode.Because the input data of 208～211 n CBSA single-bit computational logic are unsigned number and redundant digit, but arbitrary combination, so the CBSA hardware adder can provide the randomness of computation process.

Below, we further provide the present invention about CBSA hardware adder composite design and application note.

Its main operational unit of public-key encryptosystem is the big digital-to-analogue multiplication module of carrying out the overlength Bit data, and operand length is at least more than the hundreds of bit.For example, more than 200 bits, the data operation length in the RSA Algorithm is at least more than 1024 bits at least for the data operation length of ECC algorithm.

The Montgomery algorithm that utilization is known carries out modular multiplication.If fixedly modulus is N, the input data of establishing modular multiplication are A and B, and output data is T, wherein A=(a _N-1... a ₁a ₀).Then depend on each bit value a _iAnd parameter q _i, the modular multiplication process need be called computing unit (T+a repeatedly n time _iB+q _iN)/2, a wherein _i, q _i∈ 1,0,1}, q _iBe the value of T lowest order, T is an output unit, initial value T=0.With original input data B and T all random splitting become two part: B=B1+B2, T=T1+T2 then can design and advance 2 by 5 of three CBSA totalizers combinations and go out totalizer (as shown in Figure 3), is used for calculating (T+a _iB+q _iN)=(T1+T2+a _iB1+a _iB2+q _iN), wherein T1 and T2 enter the 2 output register unit that go out totalizer as 5.

Mark among Fig. 3: 300～304 is 5 to advance 2 and go out 5 of totalizer input data cell T1, T2, a _iB1, a _iB2, q _iN; 305～307 is three identical CBSA adder units; 308 be 5 advance the 2 output register unit that go out totalizer (T1, T2); Clk is a clock signal of system, and rst 5 advances 2 and goes out the totalizer reset signal.Utilize 5 to advance 2 and go out adder designs, can in the single clock period, realize once (T+a _iB+q _iN)/2 computing.System repeatedly calls 5 and advances 2 when going out totalizer, and then (T1, data T1 T2) and T2 will feed back to 5 and enter 2 importations that go out totalizer register cell; Get T1=0, T2=0 when initial.

Carry out (T+a _iB+q _iN) calculate, if precompute (X1, X2)=CBSA (a _iB1, a _iB2, q _iN), then can design and advance 2 by 4 of two CBSA totalizers combination and go out totalizer (as shown in Figure 4), be used for calculating (T+a _iB+q _iN)=(T1+T2+X1+X2), wherein T1 and T2 enter the 2 output register unit that go out totalizer as 4.System repeatedly calls 4 and advances 2 when going out totalizer, and then (T1, data T1 T2) and T2 will feed back to 4 and enter 2 importations that go out totalizer register cell; Get T1=0, T2=0 when initial.

Mark among Fig. 4: 400～403 is 4 to advance 2 and go out 4 of totalizer input data cell T1, T2, X1, X2; 404～405 is two identical CBSA adder units; 406 be 4 advance the 2 output register unit that go out totalizer (T1, T2); Clk is a clock signal of system, and rst 4 advances 2 and goes out the totalizer reset signal.Utilize 4 to advance 2 and go out adder designs, and precomputation CBSA (a _iB1, a _iB2, q _iN) value X1 and X2 can realize once (T+a in the single clock period _iB+q _iN)/2 computing.

With 5 advance 2 and go out totalizer relatively, 4 advance 2 goes out totalizer and uses 1 CBSA adder logic arithmetic unit less, thus operation once the clock period of cost will lack.

In the past about (T+a _iB+q _iN)/2 calculate, all parameters wherein can only be got nonnegative integer.That uses that the present invention provides 5 advances 2 and goes out totalizer or 4 and advance 2 and go out totalizer, and all parameters wherein can be any integers, have strengthened the adaptability and the security of computing.Utilize 4 to advance 2 and go out totalizer or 5 and advance 2 and go out totalizer and can in a timeticks, finish two to three times CBSA additive operation, save the time more than at least 1 times than two to three CBSA totalizer computings of simple recursive call.When if hardware resource enriches relatively, can consider to use 4 to advance 2 and go out totalizer or 5 and advance 2 and go out totalizer.

Claims (4)

1. the CBSA hardware adder of plus-minus method indifference parallel computation is characterized in that: be made up of the unit adder Module of the single-bit logical calculated of 64 bit parallels at least; Wherein every bit location adder Module includes following circuit structure:

Input bit is respectively

3 unsigned number registers,

Input bit is respectively

3 redundant digit registers,

Respectively with 3

The unsigned number register connects, carries out Logical operation, output information are

Logical block-1,

Respectively with 3 The unsigned number register connects, carries out

Logical operation, output information are $s{0}_i={\stackrel{`}{x}}_i\⊕{\stackrel{`}{y}}_i\⊕{\stackrel{`}{z}}_i$ Logical block-2,

Respectively with 3

The redundant digit register connects, carries out Logical operation, output information are $s{1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$ Logical block-3,

Respectively with 3

The redundant digit register connects, carries out

Logical operation, output information are

Logical block-4,

Be connected with logical block-3 with logical block-2 respectively, with the input s0 _iWith s1 _iCarry out (～(s1 _i∧ (～s0 _i))) logical operation, output information be t _i=(～(s1 _i∧ (～s0 _i))) logical block-5,

Be connected with logical block-5 with logical block-1 respectively, with the input c0 _iWith t _iCarry out the logical computing, obtain information

Logical AND gate-1,

Be connected with logical block-5 with logical block-2 respectively, with the input s0 _iWith t _iCarry out the logical computing, obtain information

Logical AND gate-2,

Be connected with logical block-5 with logical block-3 respectively, with the input s1 _iWith t _iCarry out the logical computing, obtain information

Logical AND gate-3,

Be connected with logical block-5 with logical block-4 respectively, with the input c1 _iWith t _iCarry out the logical computing, obtain information

Logical AND gate-4,

The output bit that is connected with logical AND gate-1 is

Register,

The output bit that is connected with logical AND gate-2 is

Register,

The output bit that is connected with logical AND gate-3 is

Register,

The output bit that is connected with logical AND gate-4 is

Register;

Described

Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) unsigned number $\stackrel{`}{X}=({\stackrel{`}{x}}_{n-1}...{\stackrel{`}{x}}_1{\stackrel{`}{x}}_0),$ $\stackrel{`}{Y}=({\stackrel{`}{y}}_{n-1}...{\stackrel{`}{y}}_1{\stackrel{`}{y}}_0),$ $\stackrel{`}{Z}=({\stackrel{`}{z}}_{n-1}...{\stackrel{`}{z}}_1{\stackrel{`}{z}}_0)$ The i item, wherein ${\stackrel{`}{x}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\stackrel{`}{y}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\stackrel{`}{z}}_i\∈\left\{\mathrm{0,1}\right\};$

Described Be any bigit X=(± x _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀) redundant digit $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0),$ $\tilde{Y}=({\tilde{y}}_{n-1}...{\tilde{y}}_1{\tilde{y}}_0),$ $\tilde{Z}=({\tilde{z}}_{n-1}...{\tilde{z}}_1{\tilde{z}}_0)$ The i item, wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\tilde{y}}_i\∈\left\{\mathrm{0,1}\right\},$ ${\tilde{z}}_i\∈\left\{\mathrm{0,1}\right\};$

N is any positive integer greater than 64;

Described operator ' ∧ ' expression step-by-step logic ' with ' computing, operator ' ∨ ' expression step-by-step logic ' or ' computing, operator

Expression step-by-step logic ' XOR ' computing, operator "～" expression step-by-step logic ' negate ' computing.

2. the realization modular multiplication computing unit (T+a that uses the described CBSA hardware adder of claim 1 to constitute _iB+q _iFour advancing two and go out totalizer N)=(T1+T2+X1+X2) includes:

4 difference stored data T1, T2, X1, the output register of X2,

Respectively with output register T1, T2, the first order CBSA hardware adder that X1 connects,

The second level CBSA hardware adder that is connected with first order CBSA hardware adder two output terminals and X2 output register respectively,

Stored data T1 that is connected with second level CBSA hardware adder two output terminals and the output register unit of stored data T2 (T1, T2),

And control output register unit (T1, clk clock signal of system T2) and rst totalizer reset signal,

Here: (T+a _iB+q _iN) computing unit that need call repeatedly for the modular multiplication process, wherein T is the output data of modular multiplication, and B is the input data of modular multiplication, and N is the fixedly modulus of modular multiplication, a _iBe the bit value of modular multiplication input data A, q _iSignificant bits value for modular multiplication output data T.

3. the realization modular multiplication computing unit (T1+T2+a that uses the described CBSA hardware adder of claim 1 to constitute _iB1+a _iB2+q _iFive advancing two and go out totalizer N) includes:

5 difference stored data T1, T2, a _iB1, a _iB2, q _iThe output register of N,

Respectively with output register T1, T2, a _iThe first order CBSA hardware adder that B1 connects,

Respectively with first order CBSA hardware adder two output terminals and a _iThe second level CBSA hardware adder that the B2 output register connects,

Respectively with second level CBSA hardware adder two output terminals and q _iThe third level CBSA hardware adder that the N output register connects,

Stored data T1 that is connected with third level CBSA hardware adder two output terminals and the output register unit of stored data T2 (T1, T2),

And control output register unit (T1, clk clock signal of system T2) and rst totalizer reset signal.

4. method for designing that realizes the described CBSA hardware adder of claim 1 has following steps:

The first step is determined the design object of CBSA totalizer, be realize calculating CBSA (X, Y, Z)=(C S), and satisfies C+S=X+Y+Z, for this reason:

1. arbitrary integer X, Y, Z is shown as X=(± x with 2 system numerical tables _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀), Z=(± z _N-1... ± z ₁± z ₀), x wherein _i∈ 0,1}, y _i∈ 0,1}, z _i∈ 0,1}, and the X=∑ is arranged _{I=0 ..., n-1}(± x _i2 ⁱ), the Y=∑ _{I=0 ..., n-1}(± y _i2 ⁱ), the Z=∑ _{I=0 .., n-1}(± z _i2 ⁱ);

2. count X=(± x for three 2 systems of any input _N-1... ± x ₁± x ₀), Y=(± y _N-1... ± y ₁± y ₀) and Z=(± z _N-1... ± z ₁± z ₀), (C is that 2 systems are counted C=(± c S) to its output result equally after CBSA calculates _N-1... ± c ₁± c ₀) and S=(± s _N-1... ± s ₁± s ₀);

In second step, binary number unsigned number tabular form and redundant digit tabular form are set

1) binary number unsigned number tabular form is set

To any bigit X=(± x _N-1... ± x ₁± x ₀), remove all signs of each digital front, obtain the unsigned number tabular form of X, it is designated as $\stackrel{`}{X}=({\stackrel{`}{x}}_{n-1}...{\stackrel{`}{x}}_1{\stackrel{`}{x}}_0),$ Wherein ${\stackrel{`}{x}}_i\∈\left\{\mathrm{0,1}\right\};$

2) the redundant digit tabular form of binary number is set

To any bigit X=(± x _N-1... ± x ₁± x ₀), x _iEach digital previous symbol be 1 for negative bit labeling, otherwise be labeled as 0, then obtain the redundant digit tabular form of X, and be designated as $\tilde{X}=({\tilde{x}}_{n-1}...{\tilde{x}}_1{\tilde{x}}_0)$ Wherein ${\tilde{x}}_i\∈\left\{\mathrm{0,1}\right\};$

In the 3rd step, to importing any long integer X in position, Y and Z carry out CBSA and calculate

With any long bigit X in position of input, Y, the unsigned number tabular form of Z and redundant digit tabular form are designated as respectively

CBSA (X, Y, Z)=(C, calculating process S) is as follows:

(1) at first parallel computation $(C0,S0)=\mathrm{CSA}(\stackrel{`}{X},\stackrel{`}{Y},\stackrel{`}{Z})$ With $(C1,S1)=\mathrm{CSA}(\tilde{X},\tilde{Y},\tilde{Z}),$ CSA is the computing of the carry save adder known, obtains:

C0＝(c0 _n-1...c0 ₁c0 ₀)，S0＝(s0 _n-1...s0 ₁s0 ₀)，c0 _i，s0 _i∈{0，1}；

C1＝(c1 _n-1...c1 ₁c1 ₀)，S1＝(s1 _n-1...s1 ₁s1 ₀)，c1 _i，s1 _i∈{0，1}；

(2) provide CBSA (X, Y, Z)=(C, S) result's unsigned number tabular form and redundant digit tabular form are designated as respectively

With

And

With

Wherein:

$\stackrel{`}{C}=({\stackrel{`}{c}}_{n-1}...{\stackrel{`}{c}}_1{\stackrel{`}{c}}_0),$ $\stackrel{`}{S}=({\stackrel{`}{s}}_{n-1}...{\stackrel{`}{s}}_1{\stackrel{`}{s}}_0),$ ${\stackrel{`}{c}}_i,{\stackrel{`}{s}}_i\∈\left\{\mathrm{0,1}\right\}$

$\tilde{C}=({\tilde{c}}_{n-1}...{\tilde{c}}_1{\tilde{c}}_0),$ $\tilde{S}=({\tilde{s}}_{n-1}...{\tilde{s}}_1{\tilde{s}}_0),$ ${\tilde{c}}_i,{\tilde{s}}_i\∈\left\{\mathrm{0,1}\right\}$

(3) C0 as a result that utilizes above-mentioned calculating process (1) to obtain, S0, C1, each digital bit of S1 is by the following output that calculates CBSA

Each digital bit:

Operational symbol '～' expression step-by-step logic wherein ' negate ', i.e. 1=～0,0=～1; ' ∧ ' expression step-by-step logic ' with ' operation; N is any positive integer greater than 64;

The 4th step is according to the 3rd step

Each input bit

With the 3rd step (1) respectively export bit c0 _i, s0 _i, c1 _i, s1 _i, provide following simple logic computing:

$s{0}_i={\stackrel{`}{x}}_i\⊕{\stackrel{`}{y}}_i\⊕{\stackrel{`}{z}}_i$

${s1}_i={\tilde{x}}_i\⊕{\tilde{y}}_i\⊕{\tilde{z}}_i$

t _i＝(～(s1 _i∧(～s0 _i)))

Here ' ∨ ' expression step-by-step logic ' or ' operation, Expression step-by-step logic ' XOR ' operation, go on foot 4 logical operations that (3) provide in conjunction with the 3rd:

Carry out the design of following CBSA hardware adder:

1. according to the input data of calculating

The design relevant register;

2. according to the input data Carry out

Logical operation, output data c0 _i, design is called the simple logic circuit structure of logical block-1, and sets up

The annexation of register and logical block-1;

3. according to the input data

Carry out

Logical operation, output data s0 _i, design is called the simple logic circuit structure of logical block-2, and sets up

The annexation of register and logical block-2;

4. according to the input data

Carry out Logical operation, output data s1 _i, design is called the simple logic circuit structure of logical block-3, and sets up

The annexation of register and logical block-3;

5. according to the input data

Carry out

Logical operation, output data c1 _i, design is called the simple logic circuit structure of logical block-4, and sets up

The annexation of register and logical block-4;

6. according to input data s0 _iAnd s1 _i, carry out (～(s1 _i∧ (～s0 _i))) logical operation, output data t _i, design is called the simple logic circuit structure of logical block-5, and set up logical block-5 respectively with the annexation of logical block-2 and logical block-3;

7. according to input data c0 _iAnd t _i, carry out c0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-1, and set up logical AND gate-1 respectively with the annexation of logical block-1 and logical block-5;

8. according to input data s0 _iAnd t _i, carry out s0 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-2, and set up logical AND gate-2 respectively with the annexation of logical block-2 and logical block-5;

9. according to input data s1 _iAnd t _i, carry out s1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-3, and set up logical AND gate-3 respectively with the annexation of logical block-3 and logical block-5;

10. according to input data c1 _iAnd t _i, carry out c1 _i∧ (～(s1 _i∧ (～s0 _i))) logical operation, output data

Design is called the simple logic circuit structure of logical AND gate-4, and set up logical AND gate-4 respectively with the annexation of logical block-4 and logical block-5;

According to logical AND gate-1 output data

Logical AND gate-2 output data

Logical AND gate-3 output data

Logical AND gate-4 output data

The output bit register of storing these data respectively is set; Finish these steps, just obtained realizing the CBSA hardware adder of plus-minus method indifference parallel computation.

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