CN113010145B - Digital operation component, digital calculator and electronic equipment - Google Patents

Digital operation component, digital calculator and electronic equipment Download PDF

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CN113010145B
CN113010145B CN202110300296.9A CN202110300296A CN113010145B CN 113010145 B CN113010145 B CN 113010145B CN 202110300296 A CN202110300296 A CN 202110300296A CN 113010145 B CN113010145 B CN 113010145B
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cluster
half sub
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CN113010145A (en
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周艳
李晓光
赵月雷
李双
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Chinese University of Hong Kong Shenzhen
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/383Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

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Abstract

The application relates to a digital operation component, a digital calculator and electronic equipment, wherein a topological magnetic structure (namely a double-half sub-cluster) existing in an in-plane magnetization material system is used as a multi-bit data information carrier to realize information calculation, the combination of a first double-half sub-cluster and a second double-half sub-cluster is utilized to simulate and realize addition operation of data, annihilation of the first double-half sub-cluster and the second double-half sub-cluster can simulate and realize subtraction operation of data, and the degree of polymerization of a new double-half sub-cluster finally formed represents the operation result of addition operation or subtraction operation. Through the scheme, the double half sub-clusters are used as the multi-bit data information carrier to realize information calculation, and the size of the device is in the micron order, so that the device has a simple structure, low power consumption and small volume, and meanwhile, the density of the operation logic unit can be effectively improved.

Description

Digital operation component, digital calculator and electronic equipment
Technical Field
The present disclosure relates to digital computing technology, and more particularly, to a digital computing device, a digital calculator, and an electronic apparatus.
Background
Adder and subtracter are important components of arithmetic logic unit, and are widely used in various electronic devices, bringing great convenience to production and life of people. However, conventional adders and subtractors are generally prepared based on diodes and transistors, and need to be composed of a cascade of a plurality of and, or, not and exclusive or gates, while multi-bit adders or subtractors need to be composed of a plurality of full-adder circuit units. The adder and subtractor circuit of this form is complex in structure, high in power consumption, and has a high delay.
Disclosure of Invention
Based on this, it is necessary to provide a novel nonvolatile digital operation component, a digital calculator and an electronic device for solving the problems of complex circuit structure, high power consumption and high delay of the conventional adder and subtractor.
A digital computing assembly, comprising: a metal layer; an antiferromagnetic layer covering the surface of the metal layer and having a first region for carrying a first double half-cluster; a second region for carrying a second binary cluster; when the part of the metal layer corresponding to the first region and the part of the metal layer corresponding to the second region are driven by the input voltage at the same time, the first double-half sub-cluster and the second double-half sub-cluster are combined or annihilated to form a third region; and a fourth region for reading the degree of polymerization of the new bipartite cluster formed after the third region is merged or annihilated.
In one embodiment, the metal layer has a thickness of 0.5 nm to 20 nm.
In one embodiment, the metal layer is at least one of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium.
In one embodiment, the antiferromagnetic layer is an antiferromagnetic layer having an in-plane magnetization easy axis or a type having a thin film plane as a magnetization easy plane.
In one embodiment, the antiferromagnetic layer has a thickness of 0.5 nm to 5 nm.
In one embodiment, the antiferromagnetic layer is a manganese-based alloy layer, a transition metal oxide layer, or a polycrystalline perovskite thin film layer.
In one embodiment, the antiferromagnetic layer is IrMn, ptMn, niMn, niO, coO, cr 2 O 3 、SrMnO 3 、CaMnO 3 、KMnF 3 、KNiF 3 、KCrF 3 At least one of them.
In one embodiment, the digital computation element is T-shaped.
A digital calculator comprises an output device and the digital operation component, wherein the output device is connected with a fourth area of the digital operation component.
An electronic device comprises the digital operation component.
The digital operation component, the digital calculator and the electronic equipment adopt a polymerized magnetic structure (namely, a double-half sub-cluster) existing in an in-plane magnetized material system as a multi-bit data information carrier to realize information calculation, store a first double-half sub-cluster in a first area of an antiferromagnetic layer, store a second double-half sub-cluster in a second area, enable the first double-half sub-cluster and the second double-half sub-cluster to move to a third area of the antiferromagnetic layer when voltage is applied to metal layers corresponding to the first area and the second area at the same time, merge or annihilate in the third area to form a new double-half sub-cluster, drive the new double-half sub-cluster to a fourth area and read the polymerization degree of the new double-half sub-cluster in the fourth area. The combination of the first double-half sub-cluster and the second double-half sub-cluster is utilized to simulate and realize the addition operation of data, the annihilation of the first double-half sub-cluster and the second double-half sub-cluster can simulate and realize the subtraction operation of data, and finally, the degree of polymerization of the formed new double-half sub-cluster represents the operation result of the addition operation or the subtraction operation. Through the scheme, the double-half sub-cluster is adopted as a multi-bit data information carrier to realize information calculation, the size of a device is in the micrometer level, and the digital operation assembly is simple in structure, low in power consumption and low in delay, and meanwhile, the density of operation logic units can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a digital computing device in one embodiment;
FIG. 2 is a schematic diagram of a two-half sub-cluster in one embodiment;
FIG. 3 is a schematic diagram of a two-half cluster merge in one embodiment;
FIG. 4 is a schematic diagram of two-half cluster annihilation in one embodiment;
FIG. 5 is a schematic top view of a digital computing device according to an embodiment;
FIG. 6 is a schematic diagram of an addition operation of a digital operation component in one embodiment;
FIG. 7 is a schematic diagram of a subtraction operation of a digital operation unit in an embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Referring to fig. 1, a digital operation device includes: a metal layer 10; an antiferromagnetic layer 20 covering the surface of the metal layer 10 and having a first region for carrying a first double half-cluster; a second region for carrying a second binary cluster; a third region where the first double-half sub-cluster and the second double-half sub-cluster merge or annihilate when the portion of the metal layer 10 corresponding to the first region and the portion of the metal layer 10 corresponding to the second region are simultaneously driven by the input voltage; and a fourth region for reading the degree of polymerization of the new bipartite cluster formed after the third region is merged or annihilated.
In particular, with the development of science and technology, magnetic cassia seed (magnetic skyrmion) has been studied more widely. The spin structure can exist stably in a magnetic material system with perpendicular anisotropy and Dzyaloshinsky-Moriya (DM) interaction, has a size of nanometer to micrometer, can be effectively controlled by various excitation mechanisms such as current, electric field, microwave and the like, and is an ideal information carrier.
Magnetic bipoles (magnetic bimerons) are a class of magnetic quasi-particles that exist in an in-plane magnetized material system. This type of structure is topologically equivalent to magnetic spinners, but exhibits distinct statics and dynamics from magnetic spinners. The gemini and the cluster thereof can stably exist in the magnetic film with interfacial DM interaction and in-plane magnetic anisotropy, and the magnetic quasi-particles can be effectively controlled by self-rotational flow. However, unlike magnetic spinners, their dynamics, such as velocity, deformation, etc., show a strong dependence on spin flow polarization direction. Furthermore, attraction exists between the magnetic dipole halve and the dipole halve, and the dipole halve cluster with the polymerization degree can be spontaneously formed. Based on the characteristics, the antiferromagnetic double halves can be used as an information carrier for creating, transmitting, storing and calculating unified multi-bit data, provide a brand new design thought and approach for a spintronic device, and realize the storage and basic logic processing of the multi-bit data in a physical layer.
Referring to fig. 2 in combination, a diagram of a structure of a binary half sub-cluster with a degree of polymerization from +2 to +6 is shown, wherein the binary half sub-soliton with a degree of polymerization of +1 is formed. The same dipole solitons have attractive interaction forces between them, which can bond in a direction perpendicular to the easy axis, thereby forming dipole clusters of different degrees of polymerization. Like the bipartite solitons, bipartite clusters can also be driven by electric current. As the degree of polymerization of the bi-half clusters increases, the speed of movement of the bi-half clusters driven by the in-plane polarized current increases, while the speed of movement of the bi-half clusters driven by the out-of-plane polarized current decreases.
When a voltage is applied to the metal layer 10, a current flows through the metal layer 10, and the spin hall effect caused by spin-orbit coupling causes electrons having the same direction spin to accumulate at the interface between the antiferromagnetic layer 20 and the metal, and a spin polarized current is formed in the vertical direction, thereby driving the bi-half clusters in the antiferromagnetic layer 20 to start moving.
The merging and annihilation process of the double half-clusters in the current driven antiferromagnetic layer 20 is similar to a simple addition and subtraction operation. Referring to fig. 3 in combination, for the merging process of the binary half sub-clusters, the binary half sub-soliton with the polymerization degree of +1 and the binary half sub-cluster with the polymerization degree of +3 move under the driving of current, and finally the soliton and the binary half sub-cluster are converged into a new binary half sub-cluster with the polymerization degree of +4, and the polymerization degree of the newly formed binary half sub-cluster is the sum of the original polymerization degrees. Referring to fig. 4 in combination, for the annihilation process of the double-half sub-cluster, the soliton with the polymerization degree of-1 and the double-half sub-cluster with the polymerization degree of +2 are driven by polarized current to move in opposite directions, and finally only the soliton with the polymerization degree of +1 remains, wherein the polymerization degree is the difference between the polymerization degrees of the original soliton and the double-half sub-cluster.
The double half sub-clusters with the same polymerization degree are combined into a new double half sub-cluster under the drive of current, and the polymerization degree is the sum of the original polymerization degrees; annihilation occurs between the binary clusters with different polymerization degrees, and the final polymerization degree is the difference of the original polymerization degrees. The degree of polymerization of the double half-clusters can be regulated by current-driven double half-clusters combining or annihilation, and the characteristic makes the double half-clusters ideal multi-bit data information carriers.
It should be noted that, the antiferromagnetic layer 20 is a carrier of the double-half sub-clusters, the method of obtaining the first double-half sub-clusters of the first region and the second double-half sub-clusters of the second region of the antiferromagnetic layer 20 is not the only method, in one embodiment, after the double-half sub-clusters of the required polymerization degree are generated by the external device, the first and second regions of the antiferromagnetic layer 20 are respectively transported to the first region and the second region of the antiferromagnetic layer 20 by the external device when the digital operation is needed, and then only voltages are applied to the metal layer 10 corresponding to the first region and the metal layer 10 corresponding to the second region at the same time, so that the first double-half sub-clusters and the second double-half sub-clusters can be driven to move to the third region for merging or annihilation, thereby realizing the addition and subtraction operation.
In another embodiment, the first double half-clusters and the second double half-clusters may also be generated directly in the antiferromagnetic layer 20. At this time, only a current with vertical polarization needs to be locally injected into the first region or the second region of the antiferromagnetic layer 20, so that the magnetic moment is inverted, and finally, a double half-child soliton with a polymerization degree of +1 is formed. When the binary cluster with the polymerization degree larger than +1 is needed to be obtained, at least two binary solitons with the polymerization degree of +1 are generated in the corresponding area, and then voltage is applied to the area so that the binary solitons are mutually attracted and combined into the binary cluster with the polymerization degree larger than +1, namely, the binary cluster is combined or annihilated at the input part.
When the first double-half sub-cluster of the first area and the second double-half sub-cluster of the second area are driven by current and move to the third area to finish merging or annihilation, the formed new double-half sub-cluster continues to move under the driving of the current and finally moves to the fourth area of the antiferromagnetic layer 20, and the degree of polymerization of the double-half sub-clusters in the fourth area can be read out by utilizing anisotropic magnetic resistance caused by the planar hall effect, namely, the obtained operation result is shown.
Compared with a data processing unit using high and low levels as an information carrier, the scheme uses magnetic double half sub-clusters as a multi-bit information carrier, and the single-bit information element size is in the order of 10nm, so that the area of the data processing unit can be effectively reduced. In addition, compared with the method for using the ferromagnetic material film, the method for using the antiferromagnetic material as the binary cluster medium can effectively improve the migration efficiency of clusters, thereby reducing the power consumption of the device.
It should be noted that the thickness of the metal layer 10 is not exclusive, and in one embodiment, the thickness of the metal layer 10 is 0.5 nm to 20 nm.
Specifically, in the digital operation device, the metal layer 10 is a spin hall channel, and when a current flows through the metal layer 10, the spin hall effect caused by spin-orbit coupling causes electrons having the same direction spin to accumulate at the interface between the antiferromagnetic layer 20 and the metal layer 10 and form a spin polarized current in the vertical direction, thereby driving the movement of the double half clusters in the antiferromagnetic layer 20. The thickness of the metal layer 10 is not unique, and the thickness of the metal layer 10 is set to 0.5 nm to 20 nm, that is, any thickness between 0.5 nm, 20 nm, and 0.5 nm to 20 nm, as long as the driving of the first and second double-half sub-clusters can be ensured.
Likewise, the particular type of metal employed for the metal layer 10 is not exclusive, and in one implementation, the metal layer 10 is a heavy metal layer.
In particular, the embodiment adopts a heavy metal layer as the materialIs a spin Hall channel with a spin Hall angle theta SH >0.03, thereby effectively polarizing the current and ensuring better driving effect.
Further, in one embodiment, the metal layer 10 is at least one of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium.
Specifically, the metal layer 10 may be a thin layer made of a single metal, or may be an alloy layer formed of two or more metals, so that the polarization direction and the polarization intensity of the current are modulated to realize the driving operation of the double half-clusters when a voltage is applied. The specific form of the metal layer 10 is not exclusive, and may be a metal layer formed of one of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium, or an alloy layer formed of at least one of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium with other metal, or even an alloy layer formed of at least two of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium, or the like, as long as the driving operation of the double-half-clusters can be ensured when a voltage is applied.
In one embodiment, the antiferromagnetic layer 20 is an antiferromagnetic layer 20 having an in-plane magnetization easy axis or a thin film plane as the magnetization easy plane type.
Specifically, in this embodiment, in order to ensure that the antiferromagnetic layer 20 can form a double half-cluster, it is ensured that the antiferromagnetic layer 20 needs to have an in-plane magnetization easy axis or a thin film plane as the magnetization easy plane. It will be appreciated that in other embodiments, when the bi-half sub-clusters are input by an external device, the antiferromagnetic layer 20 may be of other types as long as it is capable of carrying the bi-half sub-clusters.
In one embodiment, the antiferromagnetic layer 20 has a thickness of 0.5 nm to 5 nm.
Specifically, in order to form the double half-clusters, the antiferromagnetic layer 20 needs to have an in-plane easy axis of magnetization or a thin film plane as an easy plane of magnetization. The thickness of the antiferromagnetic layer 20 is not the only one, and the thickness of the antiferromagnetic layer 20 is set to 0.5 nm to 5 nm, that is, any thickness between 0.5 nm, 5 nm, and 0.5 nm to 5 nm is possible in this embodiment.
In one embodiment, antiferromagnetic layer 20 is a manganese-based alloy layer, a transition metal oxide layer, or a polycrystalline perovskite thin film layer.
Specifically, the Mn-based alloy layer is a thin film layer formed of an alloy of Mn metal and other metals, such as IrMn, ptMn, niMn, and the transition metal oxide layer is a thin film layer formed of an oxide of transition metal, such as NiO, coO, cr 2 O 3 While the polycrystalline perovskite thin film layer is a thin film layer composed of polycrystalline perovskite, such as SrMnO 3 、CaMnO 3 、KMnF 3 、KNiF 3 、KCrF 3 . In this embodiment, the antiferromagnetic layer 20 may be any one of a manganese-based alloy layer, a transition metal oxide layer, and a polycrystalline perovskite thin film layer, and all of them have an in-plane magnetization easy axis or a thin film plane is used as a magnetization easy plane, so that a double half cluster can be formed.
It should be noted that in one embodiment, to form a magnetic double half-cluster, the interface of the antiferromagnetic layer 20 and the metal layer 10 needs to form a DM (dzyaloshinsky-Moriya) exchange of sufficient strength, i.e., a DM exchange coefficient D >0.1mJ/m2.
In one embodiment, the digital computation element is T-shaped.
Specifically, referring to fig. 5 in combination, when the digital operation component performs addition/subtraction of data, a voltage is applied to the input terminal (i.e. the first area 21 and the second area 22), and the reading terminal (i.e. the fourth area 24) is grounded. Under the spin orbit, the double half sub-cluster of the input region moves toward the operation region (i.e., the third region 23) in the current direction.
The addition/subtraction of data is accomplished by the merging/annihilation of the double half-clusters, and the resulting new double half-clusters will continue to move under current to the read zone. And finally, the degree of polymerization of the double half sub-clusters in the reading area can be read out by utilizing the anisotropic magnetic resistance caused by the planar Hall effect, so that the data addition/subtraction operation is realized.
In order to facilitate understanding of the aspects of the present application, the aspects of the present application are explained below in conjunction with specific embodiments.
Referring to fig. 6 and 7, the same arrow direction represents the same polymerization degree of the two halves, and the opposite arrow direction represents different polymerization degree. Fig. 6 can realize the adder function, the double half sub-clusters with the aggregation degree of +1 and the double half sub-clusters with the aggregation degree of +2 are oppositely arranged under the current drive, and are combined into the double half sub-clusters with the aggregation degree of +3 at the joint of the T-shaped tracks, and the double half sub-clusters are read from the tail end of the tracks along the vertical tracks, so that the calculation of "1+2=3" is realized. Fig. 7 can realize the subtractor function, the double half sub-cluster with the aggregation degree of +1 and the double half sub-cluster with the aggregation degree of-2 move in opposite directions under the drive of current, annihilate into the double half sub-with the aggregation degree of-1 at the joint of the T-shaped track, move to the tail end of the track along the vertical track and are read, so as to realize the calculation of '1-2= -1'.
The digital operation component adopts a polymerized magnetic structure (namely, a double-half sub-cluster) existing in an in-plane magnetized material system as a multi-bit data information carrier to realize information calculation, a first double-half sub-cluster is stored in a first area of an antiferromagnetic layer, a second double-half sub-cluster is stored in a second area, when voltage is simultaneously applied to metal layers corresponding to the first area and the second area, the first double-half sub-cluster and the second double-half sub-cluster move to a third area of the antiferromagnetic layer, and are combined or annihilated in the third area to form a new double-half sub-cluster and are driven to a fourth area, and the polymerization degree of the new double-half sub-cluster is read in the fourth area. The combination of the first double-half sub-cluster and the second double-half sub-cluster is utilized to simulate and realize the addition operation of data, the annihilation of the first double-half sub-cluster and the second double-half sub-cluster can simulate and realize the subtraction operation of data, and the topological number of the finally formed new double-half sub-cluster represents the operation result of the addition operation or the subtraction operation. Through the scheme, the double-half sub-cluster is adopted as a multi-bit data information carrier to realize information calculation, the size of a device is in the micrometer level, and the digital operation assembly is simple in structure, low in power consumption and low in delay, and meanwhile, the density of operation logic units can be effectively improved.
A digital calculator comprises an output device and the digital operation component, wherein the output device is connected with a fourth area of the digital operation component.
Specifically, the specific structure of the digital operation device is as described in the above embodiments and the drawings, when a voltage is applied to the metal layer 10, a current flows through the metal layer 10, and the spin hall effect caused by spin-orbit coupling causes electrons having the same direction spin to accumulate at the interface between the antiferromagnetic layer 20 and the metal and form a spin polarized current in the vertical direction, thereby driving the double half-clusters in the antiferromagnetic layer 20 to start moving.
The merging and annihilation process of the double half-clusters in the current driven antiferromagnetic layer 20 is similar to a simple addition and subtraction operation. And for the merging process of the double half sub-clusters, the double half sub-soliton with the polymerization degree of +1 and the double half sub-cluster with the polymerization degree of +3 move under the drive of current, and finally the soliton and the double half sub-cluster are converged into a new double half sub-cluster with the polymerization degree of +4, wherein the polymerization degree of the newly formed double half sub-cluster is the sum of the original polymerization degrees. For annihilation of the double-half-sub-cluster, the soliton with the polymerization degree of-1 and the double-half-sub-cluster with the polymerization degree of +2 are driven by polarized current to move oppositely, and finally only the soliton with the polymerization degree of +1 is remained, wherein the polymerization degree is the difference between the polymerization degrees of the original soliton and the double-half-sub-cluster.
The double half sub-clusters with the same polymerization degree are combined into a new double half sub-cluster under the drive of current, and the polymerization degree is the sum of the original polymerization degrees; annihilation occurs between the binary clusters with different polymerization degrees, and the final polymerization degree is the difference of the original polymerization degrees. The polymerization degree of the double half sub-clusters can be regulated and controlled through current-driven double half sub-clusters merging or annihilation, and the characteristic enables the double half sub-clusters to become ideal multi-bit data information carriers to realize information calculation.
When the first double-half sub-cluster of the first area and the second double-half sub-cluster of the second area are driven by current and move to the third area to finish merging or annihilation, the formed new double-half sub-cluster continues to move under the driving of the current and finally moves to the fourth area of the antiferromagnetic layer 20, and the outputter can read the polymerization degree of the double-half sub-clusters in the fourth area by utilizing the anisotropic magnetic resistance caused by the planar Hall effect, namely, the obtained operation result is represented.
In the digital calculator, the digital operation component adopts a polymerized magnetic structure (namely, a double-half sub-cluster) existing in an in-plane magnetized material system as a multi-bit data information carrier to realize information calculation, a first double-half sub-cluster is stored in a first area of an antiferromagnetic layer, a second double-half sub-cluster is stored in a second area, when voltage is simultaneously applied to metal layers corresponding to the first area and the second area, the first double-half sub-cluster and the second double-half sub-cluster move to a third area of the antiferromagnetic layer, and are combined or annihilated in the third area to form a new double-half sub-cluster and are driven to a fourth area, and the polymerization degree of the new double-half sub-cluster is read in the fourth area. The combination of the first double-half sub-cluster and the second double-half sub-cluster is utilized to simulate and realize the addition operation of data, the annihilation of the first double-half sub-cluster and the second double-half sub-cluster can simulate and realize the subtraction operation of data, and finally, the degree of polymerization of the formed new double-half sub-cluster represents the operation result of the addition operation or the subtraction operation. Through the scheme, the double-half sub-cluster is adopted as a multi-bit data information carrier to realize information calculation, the size of a device is in the micrometer level, and the digital calculator has the advantages of simple structure, low power consumption and low delay, and meanwhile, the density of an operation logic unit can be effectively improved.
An electronic device comprises the digital operation component.
Specifically, the specific structure of the digital operation device is as described in the above embodiments and the drawings, when a voltage is applied to the metal layer 10, a current flows through the metal layer 10, and the spin hall effect caused by spin-orbit coupling causes electrons having the same direction spin to accumulate at the interface between the antiferromagnetic layer 20 and the metal and form a spin polarized current in the vertical direction, thereby driving the double half-clusters in the antiferromagnetic layer 20 to start moving.
The merging and annihilation process of the double half-clusters in the current driven antiferromagnetic layer 20 is similar to a simple addition and subtraction operation. And for the merging process of the double half sub-clusters, the double half sub-soliton with the polymerization degree of +1 and the double half sub-cluster with the polymerization degree of +3 move under the drive of current, and finally the soliton and the double half sub-cluster are converged into a new double half sub-cluster with the polymerization degree of +4, wherein the polymerization degree of the newly formed double half sub-cluster is the sum of the original polymerization degrees. For annihilation of the double-half-sub-cluster, the soliton with the polymerization degree of-1 and the double-half-sub-cluster with the polymerization degree of +2 are driven by polarized current to move oppositely, and finally only the soliton with the polymerization degree of +1 is remained, wherein the polymerization degree is the difference between the polymerization degrees of the original soliton and the double-half-sub-cluster.
The double half sub-clusters with the same polymerization degree are combined into a new double half sub-cluster under the drive of current, and the polymerization degree is the sum of the original polymerization degrees; annihilation occurs between the binary clusters with different polymerization degrees, and the final polymerization degree is the difference of the original polymerization degrees. The polymerization degree of the double half sub-clusters can be regulated and controlled through current-driven double half sub-clusters merging or annihilation, and the characteristic enables the double half sub-clusters to become ideal multi-bit data information carriers to realize information calculation.
When the first double-half sub-cluster of the first area and the second double-half sub-cluster of the second area are driven by current and move to the third area to finish merging or annihilation, the formed new double-half sub-cluster continues to move under the driving of the current and finally moves to the fourth area of the antiferromagnetic layer 20, and the degree of polymerization of the double-half sub-clusters in the fourth area can be read out by utilizing anisotropic magnetic resistance caused by the planar hall effect, namely, the obtained operation result is shown.
In the electronic device, the digital operation component adopts the polymerized magnetic structure (namely, the double-half sub-cluster) existing in the in-plane magnetized material system as a multi-bit data information carrier to realize information calculation, the first double-half sub-cluster is stored in the first area of the antiferromagnetic layer, the second double-half sub-cluster is stored in the second area, when voltage is applied to the metal layer corresponding to the first area and the second area at the same time, the first double-half sub-cluster and the second double-half sub-cluster move to the third area of the antiferromagnetic layer, and are combined or annihilated in the third area to form a new double-half sub-cluster and are driven to the fourth area, and the polymerization degree of the new double-half sub-cluster is read in the fourth area. The combination of the first double-half sub-cluster and the second double-half sub-cluster is utilized to simulate and realize the addition operation of data, the annihilation of the first double-half sub-cluster and the second double-half sub-cluster can simulate and realize the subtraction operation of data, and finally, the degree of polymerization of the formed new double-half sub-cluster represents the operation result of the addition operation or the subtraction operation. Through the scheme, the double-half sub-cluster is adopted as a multi-bit data information carrier to realize information calculation, the size of the device is in the micrometer level, so that the digital operation assembly is simple in structure, low in power consumption and low in delay, meanwhile, the density of operation logic units can be effectively improved, and the working reliability of electronic equipment is further effectively improved.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (9)

1. A digital computing device, wherein the digital computing device is T-shaped, comprising:
a metal layer;
an antiferromagnetic layer covering the surface of the metal layer and having a first region for carrying a first double half-cluster; a second region for carrying a second binary cluster; when the part of the metal layer corresponding to the first region and the part of the metal layer corresponding to the second region are driven by the input voltage at the same time, the first double-half sub-cluster and the second double-half sub-cluster are combined or annihilated to form a third region; and a fourth region for reading the degree of polymerization of the new bipartite cluster formed after the third region is merged or annihilated.
2. The digital computing device according to claim 1, wherein the metal layer has a thickness of 0.5 nm to 20 nm.
3. The digital computing device of claim 1, wherein the metal layer is at least one of tantalum, tungsten, platinum, gold, silver, rhenium, iridium, niobium, molybdenum, ruthenium, rhodium, palladium, titanium, vanadium, chromium, lead, bismuth, copper, and hafnium.
4. The digital operation device according to claim 1, wherein the antiferromagnetic layer is an antiferromagnetic layer having an in-plane magnetization easy axis or a magnetization easy plane type with a thin film plane.
5. The digital operation component according to any of claims 1-4, wherein the antiferromagnetic layer has a thickness of 0.5 nm to 5 nm.
6. The digital operation component according to any one of claims 1 to 4, wherein the antiferromagnetic layer is a manganese based alloy layer, a transition metal oxide layer or a polycrystalline perovskite thin film layer.
7. The digital operation device according to any of claims 1-4, wherein the antiferromagnetic layer is made of IrMn, ptMn, niMn, niO, coO, cr 2 O 3 、SrMnO 3 、CaMnO 3 、KMnF 3 、KNiF 3 、KCrF 3 At least one of them.
8. A digital calculator comprising an output and the digital computing device of any one of claims 1-7, the output being coupled to a fourth region of the digital computing device.
9. An electronic device comprising the digital computing assembly of any one of claims 1-7.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101349967A (en) * 2008-09-08 2009-01-21 成都卫士通信息产业股份有限公司 CBSA hardware adder of addition and subtraction non-difference paralleling calculation and design method thereof
CN109192853A (en) * 2018-07-02 2019-01-11 南开大学 The continuous controllable device and method for generating magnetic Skyrmion
CN109474268A (en) * 2018-12-19 2019-03-15 北京比特大陆科技有限公司 Circuit structure, circuit board and supercomputer equipment
CN110445490A (en) * 2019-08-12 2019-11-12 香港中文大学(深圳) The logical device of magnetic Skyrmion is driven based on spin wave
WO2020018624A1 (en) * 2018-07-17 2020-01-23 Northwestern University Electric-field-induced switching of antiferromagnetic memory devices
CN111953312A (en) * 2020-07-03 2020-11-17 香港中文大学(深圳) NOT gate based on topological magnetic structure and control method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800565B2 (en) * 2003-01-13 2004-10-05 Veeco Instruments, Inc. Method of forming thin oxidation layer by cluster ion beam
JP2019028569A (en) * 2017-07-26 2019-02-21 株式会社東芝 Memory system, semiconductor storage and signal processing system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101349967A (en) * 2008-09-08 2009-01-21 成都卫士通信息产业股份有限公司 CBSA hardware adder of addition and subtraction non-difference paralleling calculation and design method thereof
CN109192853A (en) * 2018-07-02 2019-01-11 南开大学 The continuous controllable device and method for generating magnetic Skyrmion
WO2020018624A1 (en) * 2018-07-17 2020-01-23 Northwestern University Electric-field-induced switching of antiferromagnetic memory devices
CN109474268A (en) * 2018-12-19 2019-03-15 北京比特大陆科技有限公司 Circuit structure, circuit board and supercomputer equipment
CN110445490A (en) * 2019-08-12 2019-11-12 香港中文大学(深圳) The logical device of magnetic Skyrmion is driven based on spin wave
CN111953312A (en) * 2020-07-03 2020-11-17 香港中文大学(深圳) NOT gate based on topological magnetic structure and control method thereof

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Bimeron clusers in chiral antiferromagnets;Xiaoguang Li .etc;《computational materials》;1-10 *
Current-induced Dynamics of the Antiferromagnetic Skyrmion and Skyrmionium;Laichuan Shen .etc;《PHYSICAL REVIEW APPLIED》;1-9 *
极化码研究综述;刘荣科;孙贺;冯宝平;孔玲;;遥测遥控(第04期);2-17 *

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