CN108627757A - 半导体集成电路以及半导体集成电路的诊断方法 - Google Patents

半导体集成电路以及半导体集成电路的诊断方法 Download PDF

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Publication number
CN108627757A
CN108627757A CN201710710254.6A CN201710710254A CN108627757A CN 108627757 A CN108627757 A CN 108627757A CN 201710710254 A CN201710710254 A CN 201710710254A CN 108627757 A CN108627757 A CN 108627757A
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CN
China
Prior art keywords
value
chain
scan
input
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710710254.6A
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English (en)
Chinese (zh)
Inventor
前川智之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN108627757A publication Critical patent/CN108627757A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31724—Test controller, e.g. BIST state machine
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201710710254.6A 2017-03-21 2017-08-18 半导体集成电路以及半导体集成电路的诊断方法 Pending CN108627757A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017054930A JP6878071B2 (ja) 2017-03-21 2017-03-21 半導体集積回路及び半導体集積回路の診断方法
JP2017-054930 2017-03-21

Publications (1)

Publication Number Publication Date
CN108627757A true CN108627757A (zh) 2018-10-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710710254.6A Pending CN108627757A (zh) 2017-03-21 2017-08-18 半导体集成电路以及半导体集成电路的诊断方法

Country Status (4)

Country Link
US (1) US10401430B2 (enExample)
EP (1) EP3379275A1 (enExample)
JP (1) JP6878071B2 (enExample)
CN (1) CN108627757A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023004731A1 (zh) * 2021-07-30 2023-02-02 华为技术有限公司 用于设计测试电路的方法和电子设备

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102591340B1 (ko) * 2019-01-22 2023-10-20 주식회사 아도반테스토 버퍼 메모리를 사용하여 하나 이상의 테스트 대상 디바이스를 테스트하기 위한 자동 테스트 장비, 하나 이상의 테스트 대상 디바이스의 자동 테스트를 위한 방법 및 컴퓨터 프로그램
US11802807B2 (en) * 2019-09-25 2023-10-31 Dell Products L.P. Leak detection apparatus for an information handling system
JP2023040646A (ja) 2021-09-10 2023-03-23 キオクシア株式会社 半導体装置及び半導体装置の検査方法
WO2023228812A1 (ja) * 2022-05-26 2023-11-30 ヌヴォトンテクノロジージャパン株式会社 検査方法
JP2024138860A (ja) 2023-03-27 2024-10-09 株式会社東芝 半導体集積回路及び半導体集積回路のテスト方法
CN118364781B (zh) * 2024-06-20 2024-08-16 中国人民解放军国防科技大学 集成电路测试模式下的时钟诊断修复方法、装置和设备

Citations (5)

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US20030188241A1 (en) * 2002-03-29 2003-10-02 International Business Machines Corporation CMOS low leakage power-down data retention mechanism
US6691268B1 (en) * 2000-06-30 2004-02-10 Oak Technology, Inc. Method and apparatus for swapping state data with scan cells
US20090326854A1 (en) * 2008-06-26 2009-12-31 Cadence Design Systems, Inc. Testing state retention logic in low power systems
US8296703B1 (en) * 2008-12-19 2012-10-23 Cadence Design Systems, Inc. Fault modeling for state retention logic
US20140289576A1 (en) * 2013-03-25 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method for self test of semiconductor integrated circuit

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JP4228061B2 (ja) * 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 集積回路の試験装置および試験方法
JP2004093351A (ja) 2002-08-30 2004-03-25 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
JP2004325124A (ja) 2003-04-22 2004-11-18 Matsushita Electric Ind Co Ltd 半導体装置
JP2006349548A (ja) 2005-06-17 2006-12-28 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
US7596737B2 (en) * 2006-11-10 2009-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for testing state retention circuits
JP2010282411A (ja) 2009-06-04 2010-12-16 Renesas Electronics Corp 半導体集積回路、半導体集積回路の内部状態退避回復方法
KR102112367B1 (ko) 2013-02-12 2020-05-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US8841952B1 (en) * 2013-05-27 2014-09-23 Freescale Semiconductor, Inc. Data retention flip-flop
CN105575438B (zh) * 2014-10-16 2020-11-06 恩智浦美国有限公司 用于测试存储器的方法及装置
KR102325388B1 (ko) * 2015-06-04 2021-11-11 삼성전자주식회사 데이터 복원을 안정적으로 제어하는 파워 게이팅 제어 회로

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691268B1 (en) * 2000-06-30 2004-02-10 Oak Technology, Inc. Method and apparatus for swapping state data with scan cells
US20030188241A1 (en) * 2002-03-29 2003-10-02 International Business Machines Corporation CMOS low leakage power-down data retention mechanism
US20090326854A1 (en) * 2008-06-26 2009-12-31 Cadence Design Systems, Inc. Testing state retention logic in low power systems
US8296703B1 (en) * 2008-12-19 2012-10-23 Cadence Design Systems, Inc. Fault modeling for state retention logic
US20140289576A1 (en) * 2013-03-25 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method for self test of semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023004731A1 (zh) * 2021-07-30 2023-02-02 华为技术有限公司 用于设计测试电路的方法和电子设备

Also Published As

Publication number Publication date
US10401430B2 (en) 2019-09-03
JP2018155707A (ja) 2018-10-04
US20180275198A1 (en) 2018-09-27
EP3379275A1 (en) 2018-09-26
JP6878071B2 (ja) 2021-05-26

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Application publication date: 20181009