CN108615429B - Integrated circuit and device for gunshot and explosion simulator - Google Patents
Integrated circuit and device for gunshot and explosion simulator Download PDFInfo
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
- G09B9/00—Simulators for teaching or training purposes
- G09B9/003—Simulators for teaching or training purposes for military purposes and tactics
Abstract
The invention provides an integrated circuit applied to a gunshot and explosion sound simulator, which is characterized in that a control module outputs a first selection signal, a first enabling control signal, a first triggering signal and a power-on reset signal to directly or indirectly control a frequency division module, an audio module, a speed module, a beat module and an address carry module, so that a preset sound code stored in a storage module is converted into a preset sound signal, and the output module outputs preset gunshot and/or preset explosion sound, thereby improving the sound quality of the gunshot and explosion sound simulator, and solving the problems that the conventional gunshot and explosion sound simulation circuit is low in gunshot level, low in sound quality distortion and the like and cannot meet the requirements of practical application.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to an integrated circuit and a device for a gunshot and explosion sound simulator.
Background
Currently, the sound effect integrated circuit is a large-scale application specific integrated circuit capable of generating a certain or a plurality of analog sound effects, for example, the sound effect integrated circuit applied to the toy gun can generate gunshot or explosion sound, and in order to feel gunshot and explosion sound to officers in military training, an audio amplifying circuit and a loudspeaker are generally adopted to simulate the gunshot and explosion sound.
However, the existing gunshot and explosion sound simulators have the defects of poor portability, low gunshot sound level, distorted sound quality and the like, and cannot meet the actual application requirements.
Disclosure of Invention
The invention aims to provide an integrated circuit and a device applied to a gunshot and explosion sound simulator, and aims to solve the problems that the conventional gunshot and explosion sound simulation circuit is low in gunshot sound level, low in tone quality distortion and the like and cannot meet practical application requirements.
A first aspect of an embodiment of the present invention provides an integrated circuit for use in a gunshot and detonation simulator, the integrated circuit comprising:
the control module is used for outputting a first selection signal, a first enabling control signal, a first trigger signal and a power-on reset signal;
the frequency dividing module is connected with the control module and used for outputting a first frequency dividing signal, a second frequency dividing signal, a third frequency dividing signal and a first reset signal according to the first enabling control signal and the power-on reset signal;
the storage module is connected with the control module and used for storing a preset sound code and outputting a first preset speed code, a first preset audio code and a first preset beat code according to the first enabling control signal and the first selecting signal;
The audio module is connected with the frequency dividing module and the storage module and is used for outputting a first audio signal according to the first reset signal, the third frequency dividing signal and the first preset audio code;
the speed module is connected with the frequency dividing module and the storage module and is used for outputting a first speed signal according to the first preset speed code and the third frequency dividing signal;
the beat module is connected with the speed module, the storage module and the frequency division module and outputs a first beat signal and a first beat clock signal according to the first frequency division signal, the first preset beat code, the first reset signal and the first speed signal;
the address carry module is connected with the control module, the frequency division module, the storage module and the beat module and is used for outputting a first address carry signal, a first feedback signal and a second feedback signal according to the first preset beat code, the first frequency division signal, the first enabling control signal, the power-on reset signal and the first beat clock signal;
the storage module is also used for receiving the address carry signal and selecting the preset sound code according to the address carry signal;
The control module is further used for controlling the first enabling control signal and the first trigger signal according to the first feedback signal and the second feedback signal;
and the output module is connected with the control module, the frequency division module, the audio module and the beat module and outputs preset gunshot and/or preset explosion sound according to the first enabling control signal, the second frequency division signal, the power-on reset signal, the first beat signal and the first audio signal.
Optionally, the integrated circuit further comprises an oscillation module for providing an oscillation frequency to the frequency dividing module and the audio module;
the first input end of the oscillation module is connected with the enabling control signal output end of the control module, and the oscillation signal output end of the oscillation module is connected with the frequency division module and the first oscillation signal input end of the audio module.
Optionally, the control module includes: the power-on reset circuit comprises a first feedback signal input end, a second frequency division signal input end, a first selection signal output end, a first enabling control signal output end, a first trigger signal output end and a power-on reset signal output end;
The first feedback signal input end and the second feedback signal input end are respectively connected with the first feedback signal output end and the second feedback signal output end of the address carry module;
the second frequency division signal input end is used for receiving a second frequency division signal output by the frequency division module;
the first selection signal output end is used for outputting a first selection signal to the storage module;
the first enabling control signal output end is respectively connected with the first enabling signal input end of the frequency division module, the first enabling signal input end of the storage module, the first enabling signal input end of the address carry module and the first enabling signal input end of the output module;
the first trigger signal output end is connected with the first trigger signal input end of the address carry module and is used for outputting a first trigger signal to the address carry module;
the power-on reset signal output end is respectively connected with the power-on reset signal input end of the frequency division module, the power-on reset signal input end of the address carry module and the power-on reset signal input end of the output module.
Optionally, the control module includes: the device comprises a key unit, a central control unit and a reset unit;
The key unit is used for outputting a key trigger signal, and a key trigger end of the key unit is connected with a key signal input end of the central control unit;
the reset unit is used for outputting the power-on reset signal, the output end of the reset unit is connected with the power-on reset signal input end of the central control unit, and the output end of the reset unit is used as the power-on reset signal output end of the control module;
the first feedback input end of the central control unit is used as the first feedback input end of the control module, the second feedback input end of the central control unit is used as the second feedback input end of the control module, the second frequency division signal input end of the central control unit is used as the second frequency division signal input end of the control module, the first selection signal output end of the central control unit is used as the first selection signal output end of the control module, the first enabling control signal output end of the central control unit is used as the first enabling control signal output end of the control module, and the first triggering signal output end of the central control unit is used as the first triggering signal output end of the control module.
Optionally, the frequency dividing module includes a first enable control signal input end, a first oscillation signal input end, a power-on reset signal input end, a first frequency dividing signal output end, a second frequency dividing signal output end and a first reset signal output end;
the first frequency division signal output end is respectively connected with the first frequency division signal input end of the beat module and the first frequency division signal input end of the address carry module;
the second frequency division signal output end is respectively connected with the second frequency division signal input end of the control module and the second frequency division signal input end of the output module;
the third frequency division signal output end is connected with the third frequency division signal input end of the speed module;
the first reset signal output end of the frequency division module is respectively connected with the first reset signal input end of the audio module and the first reset signal input end of the beat module.
Optionally, the storage module includes a first address carry signal input end, a first selection signal input end, a first enable control signal input end, a first preset speed code output end, a first preset audio code output end, and a first preset beat code output end;
The first address carry signal input end is connected with the first address carry signal output end of the address carry module;
the first selection signal input end is connected with a first selection signal output end of the control module and is used for receiving the first selection signal;
the first enabling control signal input end is connected with the first enabling control signal output end of the control module and is used for receiving a first enabling control signal of the control module;
the first preset speed code output end is connected with a first preset speed code input end of the speed module and is used for sending the first preset speed code to the speed module;
the first preset audio code output end is connected with a first preset audio code input end of the audio module and is used for sending the first preset audio code to the audio module;
the first preset beat code output end is respectively connected with the first preset beat code input end of the beat module and the first preset beat code input end of the address carry module, and is used for sending the first preset beat code to the beat module and the address carry module.
Optionally, the address carry module includes a first enable control signal input end, a first frequency division signal input end, a first trigger signal input end, a first preset beat code input end, a power-on reset signal input end, a first beat clock signal input end, a first address carry signal output end, a first feedback signal output end and a second feedback signal output end;
The first enabling control signal input end is used for receiving a first enabling control signal output by the control module;
the first frequency division signal input end is used for receiving a first frequency division signal output by the frequency division module;
the first trigger signal input end is used for receiving a first trigger signal output by the control module;
the first preset beat code input end is used for receiving a first preset beat code output by the storage module;
the power-on reset signal input end is used for receiving a power-on reset signal output by the control module;
the first beat clock signal input end is connected with the first beat clock signal output end of the beat module and is used for receiving the first beat clock signal of the beat module;
the first address carry signal output end is used for outputting a first address carry signal;
the first feedback signal output end and the second feedback signal output end are respectively connected with the first feedback signal input end of the control module and the second feedback signal input end of the control module and are used for outputting a first feedback signal and a second feedback signal to the control module.
Optionally, the period of the second frequency division signal is greater than the period of the first audio signal.
Optionally, the reset unit includes: the first switch tube, the first capacitor, the first inverter, the second inverter and the third inverter;
the current input end of the first switching tube is connected with a power supply, the control end of the first switching tube is connected with the ground, the current output end of the first switching tube and the first end of the first capacitor are connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the third inverter is used as the output end of the reset unit.
A second aspect of the embodiments of the present invention further provides a device for use in a sound simulator for gunsound and explosion sound, the device comprising a sound emitting device, the device further comprising an integrated circuit as defined in any one of the preceding claims, the output of the integrated circuit being connected to the sound emitting device.
The embodiment of the invention provides an integrated circuit applied to a gunshot and explosion sound simulator, which is used for directly or indirectly controlling a frequency division module, an audio module, a speed module, a beat module and an address carry module by outputting a first selection signal, a first enabling control signal, a first triggering signal and a power-on reset signal through a control module, converting a preset sound code stored in a storage module into a preset sound signal, outputting preset gunshot and/or preset explosion sound through an output module, improving sound quality of the gunshot and explosion sound simulator, and solving the problems that the conventional gunshot and explosion sound simulation circuit is low in gunshot level, low in sound quality distortion and the like and cannot meet actual application requirements.
Drawings
FIG. 1 is a schematic diagram of an integrated circuit for a gunshot and explosion simulator in accordance with a first embodiment of the invention;
FIG. 2 is a schematic diagram of an integrated circuit for a gunshot and explosion simulator in a second embodiment of the invention;
FIG. 3 is a schematic diagram of the control module of the integrated circuit for the sound of a gun and the sound of an explosion simulator in an embodiment of the invention;
FIG. 4 is a schematic circuit diagram of a central control unit of an integrated circuit for a gunshot and explosion simulator in an embodiment of the invention;
fig. 5 is a schematic circuit configuration diagram of a reset unit of an integrated circuit for a gunshot and explosion sound simulator in an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a crossover module for an integrated circuit of a gunshot and explosive sound simulator in an embodiment of the invention;
fig. 7 is a schematic circuit diagram of a flip-flop ZSR according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The basic elements of music include: audio, beat and tempo, where the audio has twelve-tone equal-temperament, i.e. octaves divided into twelve equal-tone parts (semitones)Every time a semitone is raised in the international phonetic symbols of each pitch, the frequency is increasedMultiple times. There are 8 beats in common use: 1/4,1/2,3/4,1,3/2, 3,4 beats, the speed in music is the beats per minute (beat/min), and the setting speed can be about 70-240 according to the music property.
Fig. 1 is a schematic structural diagram of an integrated circuit applied to a gunshot and explosion simulator according to an embodiment of the present invention, and as shown in fig. 1, the integrated circuit in this embodiment includes: a control module 100 for outputting a first selection signal, a first enable control signal, a first trigger signal, and a power-on reset signal; the frequency division module 200 is connected with the control module 100, and is used for receiving the first enabling control signal and the power-on reset signal and outputting a first frequency division signal, a second frequency division signal, a third frequency division signal and the first reset signal according to the first enabling control signal and the power-on reset signal; the memory module 600 is connected with the control module 100, and is used for storing the preset sound code and outputting a first preset speed code, a first preset audio code and a first preset beat code according to the first selection signal and the first enabling control signal; the audio module 300 is connected with the frequency division module 200 and the storage module 600 and is used for outputting a first audio signal according to the first reset signal, the third frequency division signal and the first preset audio code; the speed module 400 is connected with the frequency division module 200 and the storage module 600, and outputs a first speed signal according to a first preset speed code and a third frequency division signal; the beat module 500 is connected with the speed module 400, the storage module 600 and the frequency division module 200, and outputs a first beat signal and a first beat clock signal according to the first frequency division signal, the first preset beat code, the first reset signal and the first speed signal; the address carry module 700 is connected with the control module 100, the frequency division module 200, the storage module 600 and the beat module 500, and is used for outputting a first address carry signal, a first feedback signal and a second feedback signal according to a first preset beat code, a first frequency division signal, a first enabling control signal, the power-on reset signal and the first beat clock signal; and an output module 900 connected to the control module 100, the frequency dividing module 200, the audio module 300 and the beat module 500 and outputting a preset sound signal according to the first enable control signal, the second frequency dividing signal, the power-on reset signal, the first beat signal and the first audio signal.
In this embodiment, the storage module 600 is further configured to receive an address carry signal, select a preset sound code according to the address carry signal, control the first enable control signal and the first trigger signal according to the first feedback signal and the second feedback signal, and the control module 100 sends a first selection signal to the storage module 600, where the first selection signal is used to select a music sound code pre-stored in the storage module 600, and the music sound code is processed by the audio module 300, the speed module 400, the beat module 500, and the address carry module 700 and then outputs a corresponding preset sound signal through the output module 900.
Fig. 2 is a schematic structural diagram of an integrated circuit applied to a gunshot and explosion sound simulator according to a second embodiment of the present invention, and as shown in fig. 2, the integrated circuit applied to the gunshot and explosion sound simulator in this embodiment further includes an oscillation module 800 for providing an oscillation frequency for the frequency division module 200 and the audio module 300. Specifically, a first input end of the oscillation module 800 is connected to an enable control signal output end of the control module 100, and an oscillation signal output end of the oscillation module 800 is connected to first oscillation signal input ends of the frequency division module 200 and the audio module 300.
In this embodiment, when the first enable control signal output by the control module 100 is at a low level, the oscillation module 800 cannot generate the oscillation output square wave, and when the first enable control signal output by the control module 100 is at a high level, the oscillation module 800 can normally oscillate the oscillation output square wave.
As an embodiment of the present invention, the control module 100 includes: the first feedback signal input end ENDB1, the second feedback signal input end T11, the second frequency division signal input end H21, the first selection signal output end D, the first enable control signal output end EN1, the first trigger signal output end LT1, and the power-on reset signal output end POR1. Specifically, control ofThe first feedback signal input end ENDB1 of the module 100, the second feedback signal input end T11 of the control module 100 are respectively connected with the first feedback signal output end ENDB7 of the address carry module 700 and the second feedback signal output end T17 of the address carry module 700. The second frequency division signal input terminal H21 of the control module 100 is configured to receive the second frequency division signal output by the frequency division module 200. The first selection signal output terminal D of the control module 100 is configured to output the first selection signal to the storage module 600, specifically, the number of channels of the first selection signal output terminal D of the control module 100 is determined according to the number of selected music pieces, for example, in this embodiment, 2 music pieces are required to be selected, and then the number of channels is determined by 2 n More than or equal to 2, and n=1 is obtained, so that the control module 100 needs to generate a signal D1 through 1 frequency-division device ZTR, and the first selection signal output end D of the control module 100 is a channel transmission signal D1, and the signal D1 can form a 2-segment signal.
In this embodiment, the first enable control signal output terminal EN1 of the control module 100 is connected to the first enable signal input terminal EN2 of the frequency dividing module 200, the first enable signal input terminal EN6 of the memory module 600, the first enable signal input terminal EN7 of the address carry module 700, and the first enable signal input terminal EN9 of the output module 900, respectively. The first trigger signal output terminal LT1 of the control module 100 is connected to the first trigger signal input terminal LT7 of the address carry module 700, and is configured to output a first trigger signal to the address carry module 700. The power-on reset signal output port 1 of the control module 100 is connected to the power-on reset signal input port POR2 of the frequency division module 200, the power-on reset signal input port POR7 of the address carry module 700, and the power-on reset signal input port POR9 of the output module 900, respectively.
As an embodiment of the present invention, fig. 3 is a schematic circuit diagram of a control module 100 for an integrated circuit of a gunshot and explosion simulator according to an embodiment of the present invention, and as shown in fig. 3, the control module 100 in this embodiment includes: a key unit 103, a central control unit 102, and a reset unit 101; specifically, the key unit 103 is configured to output a key trigger signal, and a key trigger end TG103 of the key unit 103 is connected to a key signal input end TG102 of the central control unit 102; the reset unit 101 is configured to output a power-on reset signal, where the output port POR101 of the reset unit 101 is connected to the power-on reset signal input port POR102 of the central control unit 102, and the output port of the reset unit 101 is used as a power-on reset signal output port of the control module 100, and specifically, the output port POR101 of the reset unit 101 is connected to the power-on reset signal output port POR1 of the control module 100.
In this embodiment, the first feedback input end of the central control unit 102 is used as the first feedback input end of the control module 100, the second feedback input end of the central control unit 102 is used as the second feedback input end of the control module 100, the second frequency division signal input end of the central control unit 102 is used as the second frequency division signal input end of the control module 100, the first selection signal output end of the central control unit 102 is used as the first selection signal output end of the control module 100, the first enable control signal output end of the central control unit 102 is used as the first enable control signal output end of the control module 100, and the first trigger signal output end of the central control unit 102 is used as the first trigger signal output end of the control module 100. Specifically, the first feedback input end 102 of the central control unit 102 is connected to the first feedback input end 1 of the control module 100, the second feedback input end T102 of the central control unit 102 is connected to the second feedback input end T11 of the control module 100, the second frequency division signal input end H2102 of the central control unit 102 is connected to the second frequency division signal input end H21 of the control module 100, the first selection signal output end D102 of the central control unit 102 is connected to the first selection signal output end D of the control module 100, the first enable control signal output end EN102 of the central control unit 102 is connected to the first enable control signal output end EN1 of the control module 100, and the first trigger signal output end LT102 of the central control unit 102 is connected to the first trigger signal output end LT1 of the control module 100.
In this embodiment, the key unit 103 is configured to output a key trigger signal to the central control unit 102, where the second frequency division signal output by the frequency division module 200 is input through the second frequency division signal input end H2102 of the central control unit 102, and is used as a clock signal of the central control unit 102, where the time for the key trigger signal output by the key unit 103 to jump from a low level to a high level is set to T (initial high level 2), and the next rising edge time of the clock signal of the central control unit 102 is set to T (initial high level 1), where the duration for the key unit 103 to be pressed is greater than T, and the duration for the key unit 103 to be pressed is greater than T to prevent the key from being triggered by mistake, so as to output an effective high level signal.
As an embodiment of the present invention, the key unit 103 outputs a key trigger signal, the beat of the preset sound for the sound and sound simulator is 4 beats, the beat of the preset sound is one quarter beat, the number of notes of the preset sound and the preset sound is 32, and the signal frequency of the first speed signal output by the speed module 400 is 2KHz.
As an embodiment of the present invention, fig. 4 is a schematic structural diagram of a central control unit 102 of an integrated circuit for a gunshot and explosion simulator according to an embodiment of the present invention, as shown in fig. 4, a first selection signal output terminal D102 of the central control unit 102 in this embodiment has three channels, and outputs a D1 signal, a D2 signal and a D3 signal, respectively, wherein the central control unit 102 includes: fourth, fifth, sixth, seventh, eighth, ninth, and eleventh inverters INV4, INV5, INV6, INV7, INV8, INV9, INV10, INV11, INV12, INV13, first, second, third, fourth, and third flip-flops Z1, Z2, NOR1, NOR2, and NOR3.
Specifically, the input end of the fourth inverter INV4 is connected to the key signal input end TG102 of the central control unit 102, the output end of the fourth inverter INV4 is commonly connected to the power end of the first flip-flop Z1 with the second input end of the second NOR gate NOR2, the input end of the fifth inverter INV5 is connected to the second frequency division signal input end H2102 of the central control unit 102, the output end of the fifth inverter INV5 and the input end of the sixth inverter INV6 are commonly connected to the second input end CKB of the first flip-flop Z1, the output end of the sixth inverter INV6 is connected to the first input end CK of the first flip-flop Z1, the second output end QB of the first flip-flop Z1 is connected to the second input end CKB of the second flip-flop Z2, the first output end Q of the first flip-flop Z1 and the first input end CK of the second flip-flop Z2 are commonly connected to the input end of the tenth inverter INV10, the second output end QB of the second trigger Z2, the first input end CK of the third trigger Z3 and the input end of the seventh inverter INV7 are commonly connected, the output end of the seventh inverter INV7 is connected with the first channel D1 of the first selection signal output end D102 of the central control unit 102, the first output end Q of the second trigger Z2 is connected with the second output end CKB of the third trigger Z3, the second output end QB of the third trigger Z3, the second input end CKB of the fourth trigger Z4 and the input end of the eighth inverter INV8 are commonly connected, the output end of the eighth inverter INV8 is connected with the second channel D2 of the first selection signal output end D102 of the central control unit 102, the first output end Q of the third trigger Z3 is connected with the first input end CK of the fourth trigger Z4, the first output end of the fourth trigger Z4 is empty, the second output end of the fourth trigger Z4 is connected with the input end of the ninth inverter INV9, the output end of the ninth inverter INV9 is connected with the third channel D3 of the first selection signal output end D102 of the central control unit 102, the power-on reset signal output end R of the first trigger Z1, the power-on reset signal output end R of the second trigger Z2, the power-on reset signal output end R of the third trigger Z3 and the power-on reset signal output end R of the fourth trigger Z4 are commonly connected with the power-on reset signal input end POR102 of the central control unit 102, the output end of the tenth inverter INV10 is commonly connected with the input end of the eleventh inverter 11 at the first input end of the first NOR gate NOR1, the output end of the eleventh inverter INV11 is connected with the second input end of the first NOR gate NOR1, the first input end of the second NOR gate NOR2 is commonly connected with the first trigger signal output end 102 of the central control unit 102, the output end of the second NOR gate NOR2 is commonly connected with the first input end of the third NOR gate NOR3, the output end of the third NOR gate INV 2 is commonly connected with the input end of the third NOR gate 102 db 3, the output end of the third NOR gate 12 is commonly connected with the output end of the third inverter 12 of the third NOR gate 13, the third inverter INV 3 is commonly connected with the output end of the third inverter 102 of the third NOR gate 13, the third inverter is input end of the third inverter 13 is commonly connected with the first input end of the third NOR gate 102 is, the third input end of the third inverter is, the third output end of the third inverter is 2 is commonly connected with the first trigger signal output end of the third NOR input end is.
In this embodiment, the first flip-flop Z1, the second flip-flop Z2, the third flip-flop Z3, and the fourth flip-flop Z4 are all Z flip-flops.
In this embodiment, when the key trigger signal output by the key unit 103 is a high level signal and the key signal input terminal TG102 of the central control unit 102 receives the key trigger signal, the key trigger signal makes the first enable control signal output by the first enable control signal output terminal EN102 of the central control unit 102 be a high level signal, at this time, the second feedback signal received by the second feedback input terminal T102 of the central control unit 102 and the first feedback signal received by the first feedback input terminal ENDB102 of the central control unit 102 are stop signals, at this time, the oscillation module stops oscillating when the first enable control signal is at a low level, and the power-on reset signal received by the power-on reset signal input terminal POR102 of the central control unit 102 is just powered on, so that the circuit does not work.
Fig. 5 is a schematic circuit diagram of a reset unit 101 applied to an integrated circuit of a gunshot and explosion simulator according to an embodiment of the present invention, and as shown in fig. 5, the reset unit 101 includes: a first switching tube M1, a first capacitor C1, a first inverter INV1, a second inverter INV2, and a third inverter INV3; specifically, the current input end of the first switching tube M1 is connected to the control end of the first switching tube M1 of the power supply, the current output end of the first switching tube M1 is commonly connected to the first end of the first capacitor C1 and the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is used as the output end of the reset unit 101, that is, the output end of the third inverter INV3 is connected to the output end POR101 of the reset unit 101.
In this embodiment, the reset unit 101 uses the principle of capacitor charging and discharging to make the output terminal POR101 of the reset unit 101 output the power-on reset signal POR, and the output terminal POR101 of the reset unit 101 is connected with the power-on reset signal output terminal of the control module 100.
Preferably, the switching transistor M1 is a P-type MOS transistor, wherein, when the size of the P-type MOS transistor is larger and the first capacitance C1 is also larger, the delay of the power-on reset signal output by the output terminal POR101 of the reset unit 101 is also longer.
As an embodiment of the present invention, the frequency dividing module 200 includes a first enable control signal input terminal, a first oscillation signal input terminal, a power-on reset signal input terminal, a first frequency dividing signal output terminal, a second frequency dividing signal output terminal, and a first reset signal output terminal; the first frequency division signal output end of the frequency division module 200 is respectively connected with the first frequency division signal input end of the beat module 500 and the first frequency division signal input end of the address carry module 700; the second frequency division signal output end of the frequency division module 200 is respectively connected with the second frequency division signal input end of the control module 100 and the second frequency division signal input end of the output module 900; the third frequency-divided signal output end of the frequency-dividing module 200 is connected with the third frequency-divided signal input end of the speed module 400; the first reset signal output terminal of the frequency dividing module 200 is connected to the first reset signal input terminal of the audio module 300 and the first reset signal input terminal of the beat module 500, respectively.
Fig. 6 is a schematic circuit diagram of a frequency division module 200 of an integrated circuit for a gunshot and explosion simulator according to an embodiment of the present invention, where the frequency division module 200 includes: inverter INV201, inverter INV202, flip-flop Z201, flip-flop Z202, flip-flop Z203, flip-flop Z204, flip-flop Z205, flip-flop Z206, flip-flop Z207, flip-flop Z208, flip-flop Z209, flip-flop Z210, inverter INV203, inverter INV204, inverter INV205, inverter INV206, inverter INV207, NOR gate NOR201; specifically, an input end of the inverter INV201 is connected to the first oscillation signal input end OSC2 of the frequency dividing module 200, an output end of the inverter INV201 and an input end of the inverter INV202 are commonly connected to the second signal input end CKB of the flip-flop Z201, an output end of the inverter INV202 is connected to the first signal input end CK of the flip-flop Z201, an input end of the inverter INV207 is connected to the first enable control signal input end EN2 of the frequency dividing module 200, an output end of the inverter INV207 is connected to the first signal input end of the NOR gate NOR201, a second signal input end of the NOR gate NOR201 is connected to the power-on reset signal input end POR2 of the frequency dividing module 200, an output end of the NOR gate NOR201 is connected to an input end of the inverter INV206, the first signal output end Q of the flip-flop Z201 and the second signal input end CKB of the flip-flop Z202 are commonly connected to the input end of the inverter INV203, the second signal output end QB of the trigger Z201 and the first signal input end CK of the trigger Z202 are connected, the output end of the inverter INV203 is connected with the first frequency division signal output end H12 of the frequency division module 200, the first signal output end Q of the trigger Z202 is connected with the second signal input end of the trigger Z203, the second signal output end QB of the trigger Z202 is connected with the first signal input end of the trigger Z203, the first signal output end Q of the trigger Z203 is connected with the second signal input end of the trigger Z204, the second signal output end QB of the trigger Z203 is connected with the first signal input end of the trigger Z204, the second signal output end QB of the trigger Z204 is connected with the first signal input end of the trigger Z205, the first signal output end Q of the trigger Z205 and the second signal input end CKB of the trigger Z206 are connected with the input end of the inverter INV204, the second signal output end QB of the trigger Z205 and the first signal input end CK of the trigger Z206 are connected, the input end of the inverter INV204 is connected with the second frequency division signal output end H22 of the frequency division module 200, the first signal output end Q of the trigger Z206 is connected with the second signal input end of the trigger Z207, the second signal output end QB of the trigger Z206 is connected with the first signal input end of the trigger Z207, the first signal output end Q of the trigger Z207 is connected with the second signal input end of the trigger Z208, the second signal output end QB of the trigger Z207 is connected with the first signal input end of the trigger Z208, the second signal output end QB of the trigger Z208 is connected with the first signal input end of the trigger Z209, the first signal output end Q of the trigger Z209 is connected with the second signal input end of the trigger Z210, the second signal output end QB of the trigger Z209 is connected with the first signal input end of the trigger Z210, the second signal output end QB of the trigger Z210 is controlled, the first signal output end of the trigger Z210 is connected with the input end of the inverter INV205, the output end of the inverter INV205 is connected with the third frequency division signal output end H32 of the frequency division module 200, the output end of the inverter INV206, the reset signal output end R of the trigger Z201, the reset signal output end R of the trigger Z202, the reset signal output end R of the trigger Z203, the reset signal output end R of the trigger Z204, the reset signal output end R of the trigger Z205, the reset signal output end R of the trigger Z206, the reset signal output end R of the trigger Z207, the reset signal output end R of the trigger Z208, the reset signal output end R of the trigger Z209, the reset signal output terminal R of the flip-flop Z210 is commonly connected to the first reset signal output terminal P12 of the frequency dividing module 200.
In this embodiment, the flip-flops Z201, Z202, Z203, Z204, Z205, Z206, Z207, Z208, Z209, and Z210 in the frequency dividing module 200 are used as two frequency dividing devices to perform frequency division to output a first frequency dividing signal, a second frequency dividing signal, and a third frequency dividing signal, where the first frequency dividing signal is output to the beat module 500 and the address carry module 700, specifically, the first frequency dividing signal acts on the address carry module 700 to participate in the reset of the address carry module 700, the second frequency dividing signal is output to the control module 100 and the output module 900, specifically, the control module 100 receives the second frequency dividing signal to be used as an anti-shake clock signal, the third frequency dividing signal is output to the speed module 400 and the audio module 300, and the power-on reset signal and the first enable control signal received by the frequency dividing module 200 are reset to the frequency dividing module, where when the first enable control signal is a low level signal, the first power-on reset signal P1 output by the frequency dividing module 200 is a high level signal, so that the circuit is always in a reset state.
As an embodiment of the present invention, the memory module 600 includes a first address carry signal input terminal, a first selection signal input terminal, a first enable control signal input terminal, a first preset speed code output terminal, a first preset audio code output terminal, and a first preset beat code output terminal; the first address carry signal input of the memory module 600 is connected to the first address carry signal output of the address carry module 700; the first preset speed code output end of the storage module 600 is connected with the first preset speed code input end of the speed module 400; the first preset audio code output end of the storage module 600 is connected with the first preset audio code input end of the audio module 300; the first preset beat code output terminal of the storage module 600 is connected to the first preset beat code input terminal of the beat module 500 and the first preset beat code input terminal of the address carry module 700, respectively.
As an embodiment of the present invention, the storage module 600 includes: the decoder unit and the sound code storage unit, the storage module 600 switches between 32 notes by receiving the first address carry signal output by the address carry module, in this embodiment, the number of notes of the preset explosion sound and the preset gunshot is 32, specifically, the number of notes can be defined by a designer, when the number of notes of the preset explosion sound and the preset gunshot is 32, the sound code storage unit has 32 positions for writing sound codes in each row, the decoder unit determines the sound codes effectively output through the received first selection signal, for example, in table one, the signals x <0> -x <31> output by the decoder unit control the effective sound codes, specifically, the storage module 600 outputs the effective sound codes 1 and the ineffective sound codes 0 through setting the PMOS tube.
Table one: relation table of sound codes x <0> -x <31> and first preset audio codes and first preset beat codes
Table one: relation table of sound codes x <0> -x <31> and first preset audio codes and first preset beat codes
In Table one, O1-O7 are the first preset audio codes and O8-O9 are the first preset beat codes.
As an embodiment of the present invention, the storage module 600 further includes a tempo code output unit for outputting a first preset tempo code, in this embodiment, since a plurality of pieces of music are stored in the storage module 600, a preset divisor is preset for each piece of music, for example, the first preset tempo code includes tempo code signals such as B1, B2, B3, and B4, and the storage module receives the first selection signal D1, and if D1 is 1 for the second piece of music, the first column sound code is used for controlling, in this embodiment, the tempo of the two pieces of music that can be set is the same, so the first preset tempo code is the same, and then the output signals B1, B2, B3, and B4 act on the tempo module.
As an embodiment of the present invention, the address carry module 700 includes a first enable control signal input terminal, a first frequency division signal input terminal, a first trigger signal input terminal, a first preset beat code input terminal, a power-on reset signal input terminal, a first beat clock signal input terminal, a first address carry signal output terminal, a first feedback signal output terminal, and a second feedback signal output terminal; the first enable control signal input terminal of the address carry module 700 is configured to receive the first enable control signal output by the control module; the first frequency-divided signal input end of the address carry module 700 is used for receiving the first frequency-divided signal output by the frequency-dividing module 200; the first trigger signal input end of the address carry module 700 is configured to receive the first trigger signal output by the control module 100; the first preset beat code input end of the address carry module 700 is configured to receive the first preset beat code output by the storage module 600; the power-on reset signal input end of the address carry module 700 is used for receiving the power-on reset signal output by the control module 100; the first beat clock signal input end of the address carry module 700 is connected with the first beat clock signal output end of the beat module 500, and is used for receiving the first beat clock signal of the beat module 500; the first address carry signal output terminal of the address carry module 700 is configured to output a first address carry signal; the first feedback signal output end of the address carry module 700 and the second feedback signal output end of the address carry module 700 are respectively connected with the first feedback signal input end of the control module 100 and the second feedback signal input end of the control module 100, and are used for outputting the first feedback signal and the second feedback signal to the control module 100.
As an embodiment of the present invention, the address carry module 700 receives the first beat clock signal output by the beat module 500 to provide a carry signal, so as to switch notes sequentially, and since the number of notes can be set by the designer of the music, if the total number of notes of each music set in the circuit is less than or equal to 32, 2 n N=5, so 5 frequency dividers are required to generate the first address carry signals A0-A4 to be supplied to the memory module 600 to determine which set of sound codes (each set of sound codes including a set of first preset audio codes O1-O7) to output.
Specifically, when the number of notes of a certain music piece is 32, the signal generates a first feedback signal T1 through a trigger, and the first feedback signal T1 makes a high level signal generated after the music piece with 32 notes is played, and acts on the control module 100 to stop the oscillation module 800 from oscillating (en=0)). When the number of notes of a certain music piece is smaller than 32, the second feedback signal end b logically combines with the first frequency division signal H1 by using the trigger principle to generate a small high level signal for resetting and make the first enable control signal be a low level signal, for example, when the number of notes of a certain music piece is 32, after the 32 notes are played, the sound code filled in the next position of the storage module 600 makes the output first preset beat codes O8-O11 be 0000.
As an embodiment of the present invention, the oscillation signal input end of the audio module 300 is connected to the output end of the oscillation module 800, the first reset signal input end of the audio module 300 is connected to the first reset signal output end of the frequency division module 200, the third frequency division signal input end of the audio module 300 is connected to the third frequency division signal output end of the frequency division module 200, the first preset audio code input end of the audio module 300 is connected to the output end of the first preset audio code of the storage module 600, and specifically, the audio module 300 outputs the first audio signal according to the first reset signal, the third frequency division signal and the first preset audio code.
In this embodiment, the audio module 300 receives the first preset audio code output by the storage module 600 to determine what audio is generated, the audio module 300 receives the third divided signal, and changes the output first audio signal according to the change of the first preset audio code O1-O7, where the signal frequency of the third divided signal is 8KHz, the first preset audio code O1-O7 may be understood as corresponding to a note, the change of the first audio signal is designed and implemented according to the linear feedback shift register, and a specific design circuit is selected according to the user's needs, for example, the first preset audio code O1-O7 includes 7 audio code channels input, and then a base device is implemented, and in this embodiment, the base device may be a trigger ZSR, where a specific circuit structure of the trigger ZSR is shown in fig. 7.
In this embodiment, the flip-flop ZSR includes a fourth CMOS transistor I6, a fifth CMOS transistor I7, a sixth CMOS transistor I8, a seventh CMOS transistor I10, an eighth CMOS transistor I12, an not gate I9, an not gate I11, an not gate I16, a fourth N-MOS transistor M6, a fifth N-MOS transistor M7, a sixth N-MOS transistor M8, and a fourth P-MOS transistor M9.
Specifically, the source S of the fourth CMOS transistor I6 is used as the input terminal D of the trigger ZSR, the gate GP of the fourth CMOS transistor I6 is used as the PS terminal of the trigger ZSR, the gate GN of the fourth CMOS transistor I6 is used as the PSB terminal of the trigger ZSR, and the drain D of the fourth CMOS transistor I6 is connected to the source S of the sixth CMOS transistor I8. The source electrode S of the fifth CMOS transistor I7 is used as the clock terminal J of the trigger ZSR, the gate electrode GP of the fifth CMOS transistor I7 is used as the PSB terminal of the trigger ZSR, the gate electrode GN of the fifth CMOS transistor I7 is used as the PS terminal of the trigger ZSR, and the drain electrode D of the fifth CMOS transistor I7 is connected with the source electrode S of the sixth CMOS transistor I8. The gate GP of the sixth CMOS transistor I8 is used as the clock terminal CK of the flip-flop ZSR, the gate GN of the sixth CMOS transistor I8 is used as the clock terminal CKB of the flip-flop ZSR, and the drain D of the sixth CMOS transistor I8 is connected to the source S of the seventh CMOS transistor I10 through the not gate I9. The gate GP of the seventh CMOS transistor I10 is used as the clock terminal CKB of the trigger ZSR, the gate GN of the seventh CMOS transistor I10 is used as the clock terminal CK of the trigger ZSR, the drain D of the seventh CMOS transistor I10 is connected to the source S of the eighth CMOS transistor I12, and the drain D of the seventh CMOS transistor I10 is also connected to the input of the nand gate I11. The gate GP of the eighth CMOS transistor I12 is used as the clock terminal CK of the flip-flop ZSR, the gate GN of the eighth CMOS transistor I12 is used as the clock terminal CKB of the flip-flop ZSR, and the drain D of the seventh CMOS transistor I10 is used as the output terminal QB of the flip-flop ZSR. The output end of the NOT gate I11 is used as the output end Q of the trigger ZSR, the output end of the NOT gate I11 is also connected with the input end of the NOT gate I16, and the output end of the NOT gate I16 is connected with the drain electrode D of the seventh CMOS tube I10. The grid electrode of the fourth N-MOS tube M6 is used as a clock end CKB of the trigger ZSR, and the drain electrode of the fourth N-MOS tube M6 is connected with the source electrode of the fifth N-MOS tube M7; the drain electrode of the fifth N-MOS tube M7 is connected with the source electrode of the sixth N-MOS tube M8, the drain electrode of the fifth N-MOS tube M7 is also connected with the input end of the NAND gate I9, the grid electrode of the fifth N-MOS tube M7 is connected with the grid electrode of the sixth N-MOS tube M8, and the grid electrode of the fifth N-MOS tube M7 is also connected with the output end of the NAND gate I9; the drain electrode of the sixth N-MOS tube M8 is connected with the source electrode of the fourth P-MOS tube M9; the gate of the fourth P-MOS transistor M9 is used as the clock terminal CK of the trigger ZSR. The circuit output signal of the trigger ZSR is more stable, the circuit structure is simple, and the cost is saved.
In this embodiment, the audio module 300 is understood as a divide device, i.e. the entire audio module 300 is changed to a preset divide device by controlling the first preset audio codes O1 to O7, for example, when the inputs O1 to O7 are 0101010, the module is a divide by 15 device. First, the maximum divisor (designed according to the requirements of the designer) is determined to be 2 n 1, n is the number of stages (i.e. the circuit requires n ZSR devices), the minimum frequency required by the circuit is the signal obtained by 127 frequency division, so 2 n -1 is equal to or greater than 127, n=7, i.e. 7 ZSR devices are required.
As an embodiment of the present invention, the speed module 400 is also designed and implemented according to a linear feedback shift register, where a first preset speed code input end of the speed module 400 is connected to a first preset speed code output end of the storage module 600, and a third frequency division signal input end of the speed module 400 is connected to a third frequency division signal output end of the frequency division module 200.
In the present embodiment, the maximum divisor of 2 can be obtained from the linear feedback shift register n -1, n is a number of steps; in this circuit, the maximum divisor is 2 4 1=15, so a total of 15 speeds are available, as shown in table two, from which it can be seen that when the divisor 1, the circuit defaults to not need to divide.
In this embodiment, the frequency of the first speed signal TEMPO generated by the circuit is 2KHz, specifically, the frequency of the output first speed signal TEMPO is 2KHz by the third frequency division signal, so that the divisor is 4, that is, the first preset speed codes B1, B2, B3, and B4 are 0111, and then the first speed signal TEMPO is used as the input signal of the TEMPO module 500, which can be specifically designed according to the user's needs.
Divisor code corresponding to each speed of table two
As an embodiment of the present invention, the first frequency-dividing signal input end of the beat module 500 is connected to the first frequency-dividing signal output end of the frequency-dividing module 200, the first preset beat code input end of the beat module 500 is connected to the first preset beat code output end of the storage module 600, the first reset signal input end of the beat module 500 is connected to the first reset signal output end of the frequency-dividing module 200, and the first speed signal input end of the beat module 500 is connected to the first speed signal output end of the speed module 400.
In the present embodiment, the maximum beat required in the beat module 500 is 3 beats, so 2 n -1 is equal to or greater than 12, n=4, so the circuit consists of 4 flip-flops ZSR (maximum divisor of 15), with a total of 15 beats that can occur. The first speed signal generated by the speed module 400 is provided as an input to the beat module 500. When the divisor is 1, that is, the first preset beat codes O8, O9, O10, O11 are 1000), the first beat signal PR generated by the beat module 500 directly acts on the output module 900.
Specifically, one note corresponds to one beat, so the first beat clock signal RLCK generated by the beat circuit acts on the address carry module 700 to make the address carry module 700 perform carry function, i.e. perform note switching.
The reason why "division 4" is 1 beat is that in this embodiment, division 1 is one-fourth beat, division 2 is one-half beat, division three is three-quarter beat, the first 4 is 1 beat, division 6 is three-half beat, division 8 is two beats, and division 12 is three beats, and therefore the shorter the beat, the higher the frequency is, and the smaller the division value is.
Therefore, the required beats can be matched, the divisor to be set for each beat can be obtained, wherein the beat used by the first music piece of the circuit is 3 beats (code 1100), the beat used by the second music piece is 1/4 beat (code 1000), and the beat in the third table can be used for determining and outputting the first preset beat code according to the sound code in a certain storage module 600.
| Divisor number | 08 | 09 | 010 | 011 | Beat | |
| 15 | 0 | 1 | 0 | 0 | ||
| 14 | 0 | 0 | 1 | 0 | ||
| 13 | 1 | 0 | 0 | 0 | ||
| √ | 12 | 1 | 1 | 0 | 0 | 3-beat |
| 11 | 0 | 1 | 1 | 0 | ||
| 10 | 1 | 0 | 1 | 1 | ||
| 9 | 0 | 1 | 0 | 1 | ||
| 8 | 1 | 0 | 1 | 0 | 2-beat | |
| 7 | 1 | 1 | 0 | 1 | ||
| 6 | 1 | 1 | 1 | 0 | 3/2 racket | |
| 5 | 1 | 1 | 1 | 1 | ||
| 4 | 0 | 1 | 1 | 1 | 1 beat | |
| 3 | 0 | 0 | 1 | 1 | 3/4 racket | |
| 2 | 0 | 0 | 0 | 1 | 1/4 beat | |
| √ | 1 | 1 | 0 | 0 | 0 | 1/4 beat |
Divisor code corresponding to each beat of the table
As an embodiment of the invention, the period of the second divided signal is larger than the period of the first audio signal.
As an embodiment of the present invention, a device for a gunshot and explosion simulator is provided, the device comprising a sound generating device, and the device further comprising an integrated circuit according to any one of the above embodiments, wherein an output end of the integrated circuit is connected to the sound generating device.
The integrated circuit applied to the gunshot and explosion sound simulator outputs the first selection signal, the first enabling control signal, the first triggering signal and the power-on reset signal through the control module to directly or indirectly control the frequency division module, the audio module, the speed module, the beat module and the address carry module, so that the preset sound code stored in the storage module is converted into the preset sound signal, and the preset sound signal is output through the output module, thereby improving the sound quality of the gunshot and explosion sound simulator, and solving the problems that the conventional gunshot and explosion sound simulation circuit has low gunshot level, low tone distortion and the like and cannot meet the actual application requirements.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. An integrated circuit for a gunshot and explosive sound simulator, the integrated circuit comprising:
the control module is used for outputting a first selection signal, a first enabling control signal, a first trigger signal and a power-on reset signal;
The frequency dividing module is connected with the control module and used for outputting a first frequency dividing signal, a second frequency dividing signal, a third frequency dividing signal and a first reset signal according to the first enabling control signal and the power-on reset signal;
the storage module is connected with the control module and used for storing a preset sound code and outputting a first preset speed code, a first preset audio code and a first preset beat code according to the first enabling control signal and the first selecting signal;
the audio module is connected with the frequency dividing module and the storage module and is used for outputting a first audio signal according to the first reset signal, the third frequency dividing signal and the first preset audio code;
the speed module is connected with the frequency dividing module and the storage module and is used for outputting a first speed signal according to the first preset speed code and the third frequency dividing signal;
the beat module is connected with the speed module, the storage module and the frequency division module and outputs a first beat signal and a first beat clock signal according to the first frequency division signal, the first preset beat code, the first reset signal and the first speed signal;
The address carry module is connected with the control module, the frequency division module, the storage module and the beat module and is used for outputting a first address carry signal, a first feedback signal and a second feedback signal according to the first preset beat code, the first frequency division signal, the first enabling control signal, the power-on reset signal and the first beat clock signal;
the storage module is also used for receiving the address carry signal and selecting the preset sound code according to the address carry signal;
the control module is further used for controlling the first enabling control signal and the first trigger signal according to the first feedback signal and the second feedback signal;
the output module is connected with the control module, the frequency division module, the audio module and the beat module and outputs preset gunshot and/or preset explosion sound according to the first enabling control signal, the second frequency division signal, the power-on reset signal, the first beat signal and the first audio signal;
the control module is also used for sending a first selection signal to the storage module, wherein the first selection signal is used for selecting music sound codes prestored in the storage module; the music sound code is processed by the audio module, the speed module, the beat module and the address carry module and then outputs a corresponding preset sound signal through the output module;
The first frequency dividing signal is output to the beat module and the address carry module, the first frequency dividing signal acts on the address carry module and participates in resetting of the address carry module, the second frequency dividing signal is output to the control module and the output module, the control module receives the second frequency dividing signal and is used as an anti-shake clock signal, the third frequency dividing signal is output to the speed module and the audio module, and the power-on reset signal and the first enabling control signal received by the frequency dividing module reset the frequency dividing module;
the memory module includes: the storage module is used for switching 32 notes by receiving the first address carry signal output by the address carry module; the decoder unit determines the sound code effectively output by the received first selection signal;
the preset sound code comprises the first preset speed code, the first preset audio code and the first preset beat code.
2. The integrated circuit of claim 1, further comprising an oscillation module for providing an oscillation frequency to the crossover module and the audio module;
The first input end of the oscillation module is connected with the enabling control signal output end of the control module, and the oscillation signal output end of the oscillation module is connected with the frequency division module and the first oscillation signal input end of the audio module.
3. The integrated circuit of claim 2, wherein the control module comprises: the power-on reset circuit comprises a first feedback signal input end, a second frequency division signal input end, a first selection signal output end, a first enabling control signal output end, a first trigger signal output end and a power-on reset signal output end;
the first feedback signal input end and the second feedback signal input end are respectively connected with the first feedback signal output end and the second feedback signal output end of the address carry module;
the second frequency division signal input end is used for receiving a second frequency division signal output by the frequency division module;
the first selection signal output end is used for outputting a first selection signal to the storage module;
the first enabling control signal output end is respectively connected with the first enabling signal input end of the frequency division module, the first enabling signal input end of the storage module, the first enabling signal input end of the address carry module and the first enabling signal input end of the output module;
The first trigger signal output end is connected with the first trigger signal input end of the address carry module and is used for outputting a first trigger signal to the address carry module;
the power-on reset signal output end is respectively connected with the power-on reset signal input end of the frequency division module, the power-on reset signal input end of the address carry module and the power-on reset signal input end of the output module.
4. The integrated circuit of claim 3, wherein the control module comprises: the device comprises a key unit, a central control unit and a reset unit;
the key unit is used for outputting a key trigger signal, and a key trigger end of the key unit is connected with a key signal input end of the central control unit;
the reset unit is used for outputting the power-on reset signal, the output end of the reset unit is connected with the power-on reset signal input end of the central control unit, and the output end of the reset unit is used as the power-on reset signal output end of the control module;
the first feedback input end of the central control unit is used as the first feedback input end of the control module, the second feedback input end of the central control unit is used as the second feedback input end of the control module, the second frequency division signal input end of the central control unit is used as the second frequency division signal input end of the control module, the first selection signal output end of the central control unit is used as the first selection signal output end of the control module, the first enabling control signal output end of the central control unit is used as the first enabling control signal output end of the control module, and the first triggering signal output end of the central control unit is used as the first triggering signal output end of the control module.
5. The integrated circuit of claim 3, wherein the frequency division module includes a first enable control signal input, a first oscillation signal input, a power-on reset signal input, a first frequency division signal output, a second frequency division signal output, and a first reset signal output;
the first frequency division signal output end is respectively connected with the first frequency division signal input end of the beat module and the first frequency division signal input end of the address carry module;
the second frequency division signal output end is respectively connected with the second frequency division signal input end of the control module and the second frequency division signal input end of the output module;
the third frequency division signal output end is connected with the third frequency division signal input end of the speed module;
the first reset signal output end of the frequency division module is respectively connected with the first reset signal input end of the audio module and the first reset signal input end of the beat module.
6. The integrated circuit of claim 3, wherein the memory module includes a first address carry signal input, a first select signal input, a first enable control signal input, a first preset speed code output, a first preset audio code output, and a first preset beat code output;
The first address carry signal input end is connected with the first address carry signal output end of the address carry module;
the first selection signal input end is connected with a first selection signal output end of the control module and is used for receiving the first selection signal;
the first enabling control signal input end is connected with the first enabling control signal output end of the control module and is used for receiving a first enabling control signal of the control module;
the first preset speed code output end is connected with a first preset speed code input end of the speed module and is used for sending the first preset speed code to the speed module;
the first preset audio code output end is connected with a first preset audio code input end of the audio module and is used for sending the first preset audio code to the audio module;
the first preset beat code output end is respectively connected with the first preset beat code input end of the beat module and the first preset beat code input end of the address carry module, and is used for sending the first preset beat code to the beat module and the address carry module.
7. The integrated circuit of claim 3, wherein the address carry module comprises a first enable control signal input, a first divide signal input, a first trigger signal input, a first preset beat code input, a power-on reset signal input, a first beat clock signal input, a first address carry signal output, a first feedback signal output, and a second feedback signal output;
The first enabling control signal input end is used for receiving a first enabling control signal output by the control module;
the first frequency division signal input end is used for receiving a first frequency division signal output by the frequency division module;
the first trigger signal input end is used for receiving a first trigger signal output by the control module;
the first preset beat code input end is used for receiving a first preset beat code output by the storage module;
the power-on reset signal input end is used for receiving a power-on reset signal output by the control module;
the first beat clock signal input end is connected with the first beat clock signal output end of the beat module and is used for receiving the first beat clock signal of the beat module;
the first address carry signal output end is used for outputting a first address carry signal;
the first feedback signal output end and the second feedback signal output end are respectively connected with the first feedback signal input end of the control module and the second feedback signal input end of the control module and are used for outputting a first feedback signal and a second feedback signal to the control module.
8. The integrated circuit of claim 3, wherein a period of the second divided signal is greater than a period of the first audio signal.
9. The integrated circuit of claim 4, wherein the reset unit comprises: the first switch tube, the first capacitor, the first inverter, the second inverter and the third inverter;
the current input end of the first switching tube is connected with a power supply, the control end of the first switching tube is connected with the ground, the current output end of the first switching tube and the first end of the first capacitor are connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the third inverter is used as the output end of the reset unit.
10. A device for a sound simulator for gunsound and explosion sound, the device comprising a sound generating device, characterized in that the device further comprises an integrated circuit according to any of claims 1-9, the output of the integrated circuit being connected to the sound generating device.
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| CN201810667613.9A CN108615429B (en) | 2018-06-26 | 2018-06-26 | Integrated circuit and device for gunshot and explosion simulator |
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| CN201810667613.9A CN108615429B (en) | 2018-06-26 | 2018-06-26 | Integrated circuit and device for gunshot and explosion simulator |
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