CN108563276A - A kind of high speed Voltage Reference Buffer with cross-couplings filter network - Google Patents
A kind of high speed Voltage Reference Buffer with cross-couplings filter network Download PDFInfo
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- CN108563276A CN108563276A CN201810555416.8A CN201810555416A CN108563276A CN 108563276 A CN108563276 A CN 108563276A CN 201810555416 A CN201810555416 A CN 201810555416A CN 108563276 A CN108563276 A CN 108563276A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
A kind of high speed Voltage Reference Buffer with cross-couplings filter network, belongs to Analogous Integrated Electronic Circuits technical field.Including reference voltage generation module and reference voltage output buffer module, reference voltage generation module includes level shifter, the metal-oxide-semiconductor of two backfeed loops and a diode-connected being made of respectively error amplifier and source follower metal-oxide-semiconductor, reference voltage output buffer module includes a CRC filter network, the metal-oxide-semiconductor of two source follower output stages and a diode-connected, the given reference voltage in outside is by generating primary reference voltage and primary negative reference voltage after level shifter, the CRC filter networks filtering being input in reference voltage output buffer module from the output end of two error amplifiers after two feedback control loops respectively again is handled, reference voltage and negative reference voltage are exported finally by two source follower output stages.Present invention saves chip areas, and improve response speed.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, more particularly to a kind of to carry cross-couplings filter network and have
The Voltage Reference Buffer circuit of capability of fast response.
Background technology
The progress of integrated circuit technology makes digital circuit operating rate be continuously improved, it is desirable that analog-digital converter ADC has more
High speed requires also higher and higher, spy however as the raising of ADC speed for the response speed of Voltage Reference Buffer
It is not for the time-interleaved ADC of high speed, not requiring nothing more than Voltage Reference Buffer has quick response speed, and right
More strict requirements are also proposed in interfering with each other for interchannel reference voltage.For these reasons, outstanding filtering is carried to imitate
The high speed Voltage Reference Buffer circuit of the filter network of fruit becomes the research hotspot in this field.Conventional reference voltage buffer
Filter network generally have bigger area consumption, while in order to reach quick responding ability, power consumption is relatively high, therefore
The pass of the filter effect and area and response speed and power consumption that go compromise to consider filter network as possible is needed in the design process
System.
Common high speed reference voltage circuit and its filter network are as shown in Fig. 1 at present, wherein M13, M14, M15,
M16, R3 and R4 together form CRC filter networks, and M11, M12 and R5 constitute its output stage structure, are accessing single channel gradually
When approaching register type analog-digital converter SAR ADC loads, the output end due to generating reference voltage Vreft can be to load electricity
Appearance charges, and generates the output end of negative reference voltage Vrefb and can bleed off the extra charge of load capacitance, and electric charge transfer mistake
It can not be mutated in journey, cause actual circuit that can not be responded moment, therefore generate the output of reference voltage Vreft
End can export a downward overshoot signal delta Vreft, generate negative reference voltage Vrefb output end will appear one it is upward
Signal delta Vrefb is overshooted, shake here can cause M11 and M12 grid ends by the gate-source parasitic capacitance Cgs of M11 and M12 pipes
There is certain shake Δ Vgt and Δ Vgb, the equivalent capacitys of M13~M16 over the ground might as well be set as C1, then can be obtained：
It can analyze to obtain and want to allow the shake smallers of M11 and M12 grid ends, need the capacitance and the reduction that increase C1
The capacitance of Cgs, and the Cgs in real process be output stage source follower gate-source parasitic capacitance, can only by reduce M11 and
The breadth length ratio of M12 goes to reduce it, but the big breadth length ratio contradiction that this and capability of fast response require, therefore can only in real process
Increase the capacitance of C1, since the capacitance of Cgs is bigger, the capacitance of C1 generally requires bigger than the capacitance of Cgs 3 and arrives here
It 5 times or so, for multichannel, needs to consume bigger area.
In transient response, the equivalent load model letter effect analysis for taking single channel ADC is as shown in Fig. 2, wherein kC0
Indicated respectively with mC0 in certain quantizing process DAC top crowns after switching to generate reference voltage Vreft output end it
Between capacitance and to the capacitance size between the output end for generating negative reference voltage Vrefb, I2 is indicated to the charging current of load,
I4 indicate load discharge current, it is assumed that filter effect is relatively good, i.e. Δ Vgt and Δ Vgb very littles, then can consider Vgt and
Vgb is a fixed level, it is evident that since Δ Vreft can cause I1 an increment occur,
ΔI1∝ΔVreft2
And Δ Vrefb can cause I3 a reduction amount occur, and I5 is caused an increment occur,
ΔI3∝ΔVrefb2
ΔI5∝ΔVrefb
Since during real response, the interior output end in parameter reference voltage Vreft of same time is to load
Charging charge amount is equal to the discharge charge amount for the output end load for generating negative reference voltage Vrefb, therefore can obtain generating just
The charging current I2 of the output end of reference voltage Vref t is equal to the discharge stream I4 for the output end for generating negative reference voltage Vrefb, and
Δ I2=Δ I1+ Δs I3
Δ I4=Δ I5+ Δs I3
Due to Δ I2=Δ I4,
Δ I1=Δs I5
And from square directly proportional, the change of I5 for the variable quantity and reference voltage Vreft variable quantities that can analyze the I1 that attains the Way
Change amount is directly proportional to the variable quantity of negative reference voltage Vrefb, and the proportionate relationship of a single order to be allowed to be equal to the proportionate relationship of second order,
It can be obtained by analysis,
ΔVreft<ΔVrefb
It is possible thereby to know that the response speed for the output end for generating negative reference voltage Vrefb is to be slower than generation just with reference to electricity
The response speed of the output end of Vreft is pressed, the foundation of difference is with the foundation of negative reference voltage Vrefb both in real process
Subject to speed, i.e., both reference voltage Vreft and negative reference voltage Vrefb, which establish the inconsistent of speed, can lead to whole sound
It should slow.
Invention content
Big and the problems such as response speed is slow, this hair for circuit area existing for above-mentioned conventional reference voltage buffer structure
It is bright to propose a kind of Voltage Reference Buffer with cross-couplings filter network, under the premise of ensureing filter effect, capacitance
Area can reduce close to 4 times, solve the problems, such as that traditional CRC filter networks direct-to-ground capacitance consumes larger chip area；In addition
It is changed to variable resistance based on fixed resistance will be connect under negative reference voltage Vrefb output ends, realizes raising negative reference voltage
Vrefb and whole response speed, reduce the power consumption of circuit.
The technical scheme is that：
A kind of high speed Voltage Reference Buffer with cross-couplings filter network, including reference voltage generation module 401
With reference voltage output buffer module 402,
The reference voltage generation module 401 includes level shifter, the first error amplifier, the amplification of the second error
Device, the first NMOS tube M1, the second NMOS tube M2 and third NMOS tube M3,
The input terminal of the level shifter connects reference voltage Vbg, for generating primary reference voltage Vrefts
With primary negative reference voltage Vrefbs；
The positive input connection primary reference voltage Vrefts of first error amplifier, negative input connect
The drain electrode of the source electrode and the second NMOS tube M2 of the first NMOS tube M1 is connect, output end connects the grid of the first NMOS tube M1 and output
First bias voltage VGTS；
The positive input connection primary negative reference voltage Vrefbs of second error amplifier, negative input connect
The source electrode of the second NMOS tube M2, the grid of third NMOS tube M3 and drain electrode are connect, output end connects the grid of the second NMOS tube M2
And export the second bias voltage VGBS；
The drain electrode connection supply voltage V of first NMOS tube M1DD, the source electrode ground connection of third NMOS tube M3；
The reference voltage output buffer module 402 includes the 4th NMOS tube M4, the 5th NMOS tube M5, the 6th NMOS tube
M6, the 7th NMOS tube M7, the 8th NMOS tube M8, the 9th NMOS tube M9, the tenth NMOS tube M10, first resistor R1 and second resistance
R2,
The grid of 7th NMOS tube M7 connects the first bias voltage VGTSAnd by connecting the 4th after first resistor R1
Drain electrode and the source electrode of the grid and the tenth NMOS tube M10 of NMOS tube M4 and the 9th NMOS tube M9, drain electrode and source electrode ground connection；
The grid of 8th NMOS tube M8 connects the second bias voltage VGBSAnd by connecting the 5th after second resistance R2
Drain electrode and the source electrode of the grid and the 9th NMOS tube M9 of NMOS tube M5 and the tenth NMOS tube M10, drain electrode and source electrode ground connection；
The drain electrode connection supply voltage V of 4th NMOS tube M4DD, source electrode connect the 5th NMOS tube M5 drain electrode simultaneously export just
Reference voltage Vref t；
The grid of the 6th NMOS tube M6 of source electrode connection of 5th NMOS tube M5 and drain electrode simultaneously export negative reference voltage Vrefb,
The source electrode of 6th NMOS tube M6 is grounded.
Specifically, the first resistor R1 and second resistance R2 is polycrystalline resistor.
Beneficial effects of the present invention are：
1, the present invention, can be effective by using double source follower output stages, i.e. the 4th NMOS tube M4 and the 5th NMOS tube M5
The bandwidth and response speed for improving output reference voltage, by connecing diode under the output end for generating negative reference voltage Vrefb
6th NMOS tube M6 of connection forms a variable resistance being negatively correlated with negative reference voltage Vrefb, improves negative with reference to electricity
The response speed of Vrefb is pressed, while balancing the response speed of double reference voltages, improves whole response speed.
2, a kind of cross-linked CRC filter networks are utilized in the present invention, under the filter capacitor of same size, coupling electricity
Hold equivalent capacity over the ground and will increase 4 times, while improving filter effect, greatly saves chip area.
Description of the drawings
Fig. 1 is the structural schematic diagram of traditional high speed Voltage Reference Buffer circuit with filter network.
Analysis chart is imitated in transient response letter when Fig. 2 is Voltage Reference Buffer connection load.
Fig. 3 is a kind of circuit knot of the high speed Voltage Reference Buffer with cross-couplings filter network proposed by the present invention
Structure schematic diagram.
Fig. 4 is the electrical block diagram of reference voltage output buffer module 402 in the present invention.
Equivalent capacity distribution when Fig. 5 is cross-couplings filter network on 402 structure band of reference voltage output buffer module
Figure.
Specific implementation mode
The invention will be further described with reference to the accompanying drawings and embodiments.
Voltage Reference Buffer proposed by the present invention as shown in figure 3, including prime reference voltage generation module 401 and after
The reference voltage output buffer module 402 of grade, wherein reference voltage generation module 401 include level shifter, the first error
Amplifier, the second error amplifier, the first NMOS tube M1, the second NMOS tube M2 and third NMOS tube M3, the first NMOS tube M1,
Two NMOS tube M2 are connected with the respective substrates of third NMOS tube M3 with source electrode, and the input terminal of level shifter connects reference voltage
Vbg, for generating primary reference voltage Vrefts and primary negative reference voltage Vrefbs；The forward direction of first error amplifier is defeated
Enter the primary reference voltage Vrefts of end connection, negative input connects the source electrode and the second NMOS tube M2 of the first NMOS tube M1
Drain electrode, output end connect the first NMOS tube M1 grid simultaneously export the first bias voltage VGTS；Second error amplifier is just
Primary negative reference voltage Vrefbs is connected to input terminal, negative input connects source electrode, the 3rd NMOS of the second NMOS tube M2
The grid of pipe M3 and drain electrode, output end connect the grid of the second NMOS tube M2 and export the second bias voltage VGBS；First NMOS
The drain electrode connection supply voltage V of pipe M1DD, the source electrode ground connection of third NMOS tube M3.
The output end of first error amplifier is connected to the source follower metal-oxide-semiconductor i.e. grid end of the first NMOS tube M1, then passes through
The source of one NMOS tube M1 feeds back to the negative input of the first error amplifier, and the output end of the second error amplifier is connected to
The source follower metal-oxide-semiconductor i.e. grid end of the second NMOS tube M2, then the second error amplifier is fed back to by the source of the second NMOS tube M2
Negative input, form two feedback control loops, the metal-oxide-semiconductor that third NMOS tube M3 forms a diode-connected replaces tradition to join
Examine the fixed resistance of voltage buffer.The given reference voltage V bg in outside is input in reference voltage generation module 401, is passed through
Primary reference voltage Vrefts and primary negative reference voltage Vrefbs are generated after level shifter, then pass through two respectively instead
It presents the biasing grid voltage of the stabilization of generation, i.e. the first bias voltage VG after loop from the output ends of two error amplifiersTSWith
Two bias voltage VGBSIt is input in reference voltage output buffer module 402.
The structure of reference voltage output buffer module 402 is as shown in Figure 3 and Figure 4, including the 4th NMOS tube M4, the 5th NMOS
Pipe M5, the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS tube M8, the 9th NMOS tube M9, the tenth NMOS tube M10, the first electricity
Hinder R1 and second resistance R2, the 4th NMOS tube M4, the 5th NMOS tube M5, the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS
Pipe M8, the 9th NMOS tube M9 and the respective substrates of the tenth NMOS tube M10 and source electrode interconnection, the grid connection the of the 7th NMOS tube M7
One bias voltage VGTSAnd the grid and the tenth by connecting the 4th NMOS tube M4 and the 9th NMOS tube M9 after first resistor R1
The drain electrode of NMOS tube M10 and source electrode, drain electrode and source electrode ground connection；The grid of 8th NMOS tube M8 connects the second bias voltage VGBS
And the drain electrode by connecting the grid and the 9th NMOS tube M9 of the 5th NMOS tube M5 and the tenth NMOS tube M10 after second resistance R2
And source electrode, drain electrode and source electrode ground connection；The drain electrode connection supply voltage V of 4th NMOS tube M4DD, source electrode the 5th NMOS tube of connection
The drain electrode of M5 simultaneously exports reference voltage Vreft；The source electrode of 5th NMOS tube M5 connects grid and the drain electrode of the 6th NMOS tube M6
And export the source electrode ground connection of negative reference voltage Vrefb, the 6th NMOS tube M6.
Wherein the 7th NMOS tube M7, the 8th NMOS tube M8, the 9th NMOS tube M9, the tenth NMOS tube M10, first resistor R1 and
Second resistance R2 forms CRC filter networks, since source electrode, drain electrode and the substrate of the 7th NMOS tube M7 and the 8th NMOS tube M8 all connect
Ground voltage, it is each to form a mos capacitance over the ground；9th NMOS tube M9 and the tenth NMOS tube M10 form two cross-linked MOS
Capacitance, the 4th NMOS tube M4 are source follower structure, and the 5th NMOS tube M5 is also similar to a source follower structure, the 6th NMOS tube M6
Form the metal-oxide-semiconductor of a diode-connected.The first bias voltage VG that reference voltage generation module 401 is generatedTSPartially with second
Set voltage VGBSBe filtered by CRC filter networks, then by two source follower output stages export reference voltage Vreft and
Negative reference voltage Vrefb.
In some embodiments, according to the difference of application and technique, first resistor R1 and second resistance R2 select polycrystalline
(poly) resistance, temperature coefficient and voltage coefficient are preferable.
Since equivalent capacity is equal over the ground for the grid end of the 4th NMOS tube M4 and the 5th NMOS tube M5, i.e. the 4th NMOS tube M4's
Grid end passes through second by the grid end of equivalent capacity and the 5th NMOS tube M5 after first resistor R1 and the 7th NMOS tube M7 over the ground
Equivalent capacity after resistance R2 and the 8th NMOS tube M8 over the ground is equal, might as well be denoted as C1, and the 4th NMOS tube M4 and the 5th
The gate-source parasitic capacitance approximately equal of NMOS tube M5 pipes, might as well be denoted as C2, and the 9th NMOS tube M9 and the tenth NMOS tube M10 etc.
Imitate capacitance it is also identical, C3 might as well be denoted as, then for the CRC filter networks in the present invention equivalent capacity distribution as shown in figure 5,
Using superposition theorem, negative reference voltage Vrefb zero setting obtains under the influence of reference voltage Vreft, the 4th
The expression formula of grid end the voltage Vgt and Vgb of NMOS tube M4 and the 5th NMOS tube M5 are as follows：
Similarly, it by reference voltage Vreft zero setting, can obtain under the influence of negative reference voltage Vrefb, the 4th NMOS
The expression formula of grid end the voltage Vgt and Vgb of pipe M4 and the 5th NMOS tube M5 are as follows：
Therefore it can obtain, in the case where reference voltage Vreft and negative reference voltage Vrefb is acted on simultaneously, the 4th NMOS tube
The expression formula of grid end the voltage Vgt and Vgb of M4 and the 5th NMOS tube M5 are as follows：
Arrangement obtains
Arrangement obtains
Since in transient response, the shake at the ends reference voltage Vreft and the ends negative reference voltage Vrefb is not much different,
It assume that
Δ Vrefb=- Δ Vreft=Δs V
It can then obtain,
Analysis result：Analysis relative to traditional structure, it can be seen that coupled capacitor appears on denominator, can be equivalent to
The grid end Vgt and Vgb of 4th NMOS tube M4 and the 5th NMOS tube M5 has newly increased a direct-to-ground capacitance, and the capacitance is 4
The capacitance of times C3 utilizes the cross coupling capacitor of C3 sizes, filtering identical with 4 times of C3 size ground capacities may be implemented
Effect, integral capacitor area can reduce the master-slave mode multiple branch circuit close to 3 times or so, used especially for time-interleaved ADC
The structure of reference voltage buffer stage can save a big chunk chip area.
For the lower connecting resistance of negative reference voltage Vrefb, the think of that traditional fixed resistance is replaced using variable resistance is proposed
Think, for the present invention using NMOS tube i.e. the 6th NMSO pipe M6 of a diode-connected, grid and drain electrode are all connected to generation
The output end of negative reference voltage Vrefb, source electrode and substrate are connected to ground voltage, it is recognised that being for equivalent resistance value：
Wherein μ indicates that the mobility of carrier, Cox indicate the unit area grid oxygen capacitance of metal-oxide-semiconductor,Indicate the width of metal-oxide-semiconductor
Long ratio, Vth indicate that the threshold voltage of metal-oxide-semiconductor, λ indicate channel length modulation coefficient.Since the 6th NMOS tube M6 is in saturation
Area, when channel-length modulation is weaker, λ very littles, the equivalent resistance can be approximated to be,
An equivalent resistance being negatively correlated with negative reference voltage Vrefb can be obtained in this way, when carrying out transient response,
As shown in Fig. 2, the increment of the ends negative reference voltage Vrefb response current size I5 becomes,
Wherein R0 indicates that the resistance value under negative reference voltage vrefb original steady state values, R (Δ vrefb) are indicated due to negative ginseng
Examine the variable quantity of resistance caused by the jitter value Δ Vrefb of voltage Vrefb.Above formula can be seen that the velocity of discharge and negative ginseng
The square directly proportional of voltage Vrefb variable quantities is examined, the relationship of second order is increased to by traditional single order relationship, hence it is evident that accelerate negative ginseng
The response speed for examining voltage Vrefb, is in addition analyzed by front, it is known that when carrying out transient response, is had
Δ I1=Δs I5
After variable resistance by the way that connecting resistance under negative reference voltage Vrefb to be changed into this diode-connected, have
ΔI1∝ΔVreft2
ΔI5∝ΔVrefb2
The two has the response speed that the two difference is improved close to identical response speed, comes relative to traditional structure
It says, whole response speed is obviously improved.
In conclusion the present invention proposes a kind of high speed Voltage Reference Buffer with cross-couplings filter network, carry
A kind of new cross-linked filter network is gone out, the capacitance for the equivalent capacity over the ground that can be converted into coupled capacitor increases by 3
Times size, while improving filter effect, is greatly saved the area of chip；In addition proposed by the present invention to be connect using diode
The metal-oxide-semiconductor of method is equivalent to a variable resistance being negatively correlated with reference voltage, improves the response of negative reference voltage Vrefb
Speed also fundamentally solves the problems, such as that there are larger differences in response speed for double reference voltages.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from
Protection domain on the basis of, can be to method and structure above the step of sequence, details and operation make various modifications, change and
Optimization.
Claims (2)
1. a kind of high speed Voltage Reference Buffer with cross-couplings filter network, which is characterized in that produced including reference voltage
Raw module (401) and reference voltage output buffer module (402),
The reference voltage generation module (401) include level shifter, the first error amplifier, the second error amplifier,
First NMOS tube (M1), the second NMOS tube (M2) and third NMOS tube (M3),
The input terminal connection reference voltage (Vbg) of the level shifter, for generating primary reference voltage (Vrefts)
With primary negative reference voltage (Vrefbs)；
The positive input connection primary reference voltage (Vrefts) of first error amplifier, negative input connection
The drain electrode of the source electrode and the second NMOS tube (M2) of first NMOS tube (M1), output end connect the grid of the first NMOS tube (M1) simultaneously
Export the first bias voltage (VGTS)；
The positive input connection primary negative reference voltage (Vrefbs) of second error amplifier, negative input connection
The source electrode of second NMOS tube (M2), the grid of third NMOS tube (M3) and drain electrode, output end connect the second NMOS tube (M2)
Grid simultaneously exports the second bias voltage (VGBS)；
The drain electrode connection supply voltage (V of first NMOS tube (M1)DD), the source electrode ground connection of third NMOS tube (M3)；
The reference voltage output buffer module (402) includes the 4th NMOS tube (M4), the 5th NMOS tube (M5), the 6th NMOS tube
(M6), the 7th NMOS tube (M7), the 8th NMOS tube (M8), the 9th NMOS tube (M9), the tenth NMOS tube (M10), first resistor
(R1) and second resistance (R2),
The grid of 7th NMOS tube (M7) connects the first bias voltage (VGTS) and connect the 4th afterwards by first resistor (R1)
Drain electrode and the source electrode of the grid and the tenth NMOS tube (M10) of NMOS tube (M4) and the 9th NMOS tube (M9), drain electrode and source electrode
Ground connection；
The grid of 8th NMOS tube (M8) connects the second bias voltage (VGBS) and connect the 5th afterwards by second resistance (R2)
Drain electrode and the source electrode of the grid and the 9th NMOS tube (M9) of NMOS tube (M5) and the tenth NMOS tube (M10), drain electrode and source electrode
Ground connection；
The drain electrode connection supply voltage (V of 4th NMOS tube (M4)DD), source electrode connects the drain electrode of the 5th NMOS tube (M5) and output
Reference voltage (Vreft)；
The source electrode of 5th NMOS tube (M5) connects the grid of the 6th NMOS tube (M6) and drains and export negative reference voltage
(Vrefb), the source electrode ground connection of the 6th NMOS tube (M6).
2. the high speed Voltage Reference Buffer according to claim 1 with cross-couplings filter network, which is characterized in that
The first resistor (R1) and second resistance (R2) are polycrystalline resistor.
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| EP1091492A1 (en) * | 1999-10-08 | 2001-04-11 | STMicroelectronics S.r.l. | An output buffer for digital signals |
| JP2011166278A (en) * | 2010-02-05 | 2011-08-25 | Riniaseru Design:Kk | Differential amplifying circuit, two-stage amplifying circuit and a/d conversion circuit using them |
| CN102439845A (en) * | 2010-04-15 | 2012-05-02 | 复旦大学 | Dual-mode voltage-controlled oscillator, frequency synthesizer and wireless receiving apparatus |
| CN103677040A (en) * | 2012-09-25 | 2014-03-26 | 清华大学 | Drive circuit of reference voltage |
| CN105281669A (en) * | 2014-07-03 | 2016-01-27 | 英飞凌科技股份有限公司 | System and method for voltage controlled oscillator |
| EP3079256A1 (en) * | 2015-04-10 | 2016-10-12 | PR Electronics A/S | Zero drift, limitless and adjustable reference voltage generation |
| CN106133632A (en) * | 2014-04-03 | 2016-11-16 | 高通股份有限公司 | Power-efficient, low noise and the actuator insensitive to technique/voltage/temperature (PVT) for voltage controlled oscillator (VCO) |
| CN107688367A (en) * | 2016-08-04 | 2018-02-13 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
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2018
- 2018-06-01 CN CN201810555416.8A patent/CN108563276B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1091492A1 (en) * | 1999-10-08 | 2001-04-11 | STMicroelectronics S.r.l. | An output buffer for digital signals |
| JP2011166278A (en) * | 2010-02-05 | 2011-08-25 | Riniaseru Design:Kk | Differential amplifying circuit, two-stage amplifying circuit and a/d conversion circuit using them |
| CN102439845A (en) * | 2010-04-15 | 2012-05-02 | 复旦大学 | Dual-mode voltage-controlled oscillator, frequency synthesizer and wireless receiving apparatus |
| CN103677040A (en) * | 2012-09-25 | 2014-03-26 | 清华大学 | Drive circuit of reference voltage |
| CN106133632A (en) * | 2014-04-03 | 2016-11-16 | 高通股份有限公司 | Power-efficient, low noise and the actuator insensitive to technique/voltage/temperature (PVT) for voltage controlled oscillator (VCO) |
| CN105281669A (en) * | 2014-07-03 | 2016-01-27 | 英飞凌科技股份有限公司 | System and method for voltage controlled oscillator |
| EP3079256A1 (en) * | 2015-04-10 | 2016-10-12 | PR Electronics A/S | Zero drift, limitless and adjustable reference voltage generation |
| CN107688367A (en) * | 2016-08-04 | 2018-02-13 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
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| CN108563276B (en) | 2020-05-26 |
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