CN103677040A - Drive circuit of reference voltage - Google Patents
Drive circuit of reference voltage Download PDFInfo
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- CN103677040A CN103677040A CN201210362016.8A CN201210362016A CN103677040A CN 103677040 A CN103677040 A CN 103677040A CN 201210362016 A CN201210362016 A CN 201210362016A CN 103677040 A CN103677040 A CN 103677040A
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Abstract
The invention discloses a drive circuit of reference voltage. The drive circuit can achieve a good PSRR, increase the building speed of the reference voltage and reduce power consumption of the circuit. The drive circuit of the reference voltage comprises a closed-loop negative feedback loop and an open loop branch, wherein the open loop branch comprises an NMOS tube (M31) and an NMOS tube (M32), the drain electrode of the NMOS tube (M31) is connected with a power supply VDD, a first bias voltage provided by the closed-loop negative feedback loop is input into the grid electrode of the NMOS tube (M31), the source electrode of the NMOS tube (M31) outputs reference voltage Vrp, the drain electrode of the NMOS tube (M32) is connected with the source electrode of the NMOS tube (M31), a second bias voltage provided by the closed-loop negative feedback loop is input into the grid electrode of the NMOS tube (M32), the source electrode of the NMOS tube (M32) is grounded through an isolation electric device, and the source electrode of the NMOS tube (M32) outputs reference voltage Vrn.
Description
Technical field
The present invention relates to circuit development technique field, particularly a kind of driving circuit of reference voltage.
Background technology
ADC(Analog-to-Digital Converter, analog to digital conversion) technology realizes simulating signal is converted to digital signal.From essence, the function of ADC is that the comparative result based on input simulating signal and input reference voltage is exported numerical coding.The error of reference voltage and noise all will be converted to the error of output encoder, and the performance of reference voltage directly affects performance and the precision of ADC.For the ADC equipment of a 12-bit precision, supply voltage 1.8V, if reference voltage range is supply voltage size, in must be controlled at ± 0.4mV of the error of input reference voltage and noise.
In actual scene, there are many factors can affect the performance of reference voltage.Such as, in the level circuit of flow line structure ADC, switching capacity (switched-capacitor) circuit extracts electric current from reference voltage driving circuit and realizes discharging and recharging electric capacity.On the one hand, switched-capacitor circuit need to have stable reference voltage to guarantee its output accuracy, and on the other hand, the high speed of switch is switched again can introduce larger transient load to reference voltage circuit, causes the shake of reference voltage.In high-speed ADC, the shake of reference voltage must realize stable within the shorter time cycle.Therefore, need to provide for high-speed ADC the implementation of stable reference voltage.
The implementation of existing reference voltage driving circuit is mainly divided into two classes: high impedance realizes technology and Low ESR is realized technology.High impedance is realized technology and is conventionally adopted on larger sheet or the outer electric capacity of sheet, utilizes the variation of large capacitive absorption electric charge to maintain the stable of voltage.Low ESR is realized technology and is depended on high speed voltage buffering (buffer) larger transient current is provided.It is that reference voltage more conventional under current high-speed ADC drives implementation that Low ESR is realized technology.Referring to Fig. 1, shown that existing Low ESR realizes under technology the reference voltage driving circuit for ADC, this circuit drives an open-loop branch 2 to realize by a close loop negative feedback loop 1, reference voltage Vrp and Vrn drive branch road 2 outputs by open loop, and this open loop drives branch road 2 to be driven by close loop negative feedback loop 1.Input voltage Vrpin, Vrnin and Vcmoin are produced by band-gap reference and generating circuit from reference voltage 10, through unity gain feedback loop 4 and loop 5, provide accurate magnitude of voltage, then export and provide larger drive current via open-loop branch 2.Reference voltage Vrp is by PMOS(P-Channel Metal Oxide Semiconductor, P-channel metal-oxide-semiconductor) pipe M11 and M12 produce, reference voltage Vrn is by NMOS(N-Channel Mental Oxide Semiconductor, N NMOS N-channel MOS N) pipe M13 and M14 generation.
At least there is following defect in existing reference voltage drive scheme:
Existing high impedance is realized Technology Need jumbo outer electric capacity is set.Therefore, chip need to increase extra chip bonding pad and package pins, and the stray inductance of binding line and the outer electric capacity of sheet can limit the speed of setting up of reference voltage.
Existing Low ESR is realized technology, drives branch road generally by PMOS pipe and NMOS pipe, to be realized.Because NMOS pipe carrier mobility is greater than the mobility that PMOS manages charge carrier, the design size of PMOS pipe M11 and M12 be greater than NMOS pipe size (such as: in SMIC13 technique, the mobility of electronics is 3 times of hole mobility, therefore the design size of PMOS pipe M11 and M12 is 3 times of NMOS pipe M13 and M14 size).Large-sized PMOS pipe can bring larger stray capacitance.On the one hand, the PMOS pipe decoupling capacitance 6 of M11 and the stray capacitance of M11 form power lead to the coupling path of output terminal Vrp, have reduced PSRR(Power Supply Rejection Ratio, Power Supply Rejection Ratio), affected circuit performance; On the other hand, two PMOS pipe M11 being connected with Vrp and the stray capacitance of M12 all become the capacitive load of output Vrp, cause reference voltage Vrp to set up speed slower, be to guarantee that certain reference voltage sets up speed and will inevitably increase circuit power consumption.
Summary of the invention
The invention provides a kind of driving circuit of reference voltage, to solve existing scheme, adopt the outer capacitive way of sheet need to increase extra chip bonding pad and package pins, introducing stray inductance lower the problem of the speed of setting up, and while adopting large scale PMOS pipe the PSRR of circuit lower, guarantee can cause the excessive problem of circuit power consumption when reference voltage is set up speed.
For achieving the above object, the embodiment of the present invention has adopted following technical scheme:
The driving circuit of a kind of reference voltage that the embodiment of the present invention provides, described driving circuit comprises close loop negative feedback loop and open-loop branch, described open-loop branch comprises NMOS pipe M31 and NMOS pipe M32;
The drain electrode of NMOS pipe M31 is connected to power vd D, the first bias voltage that the grid access close loop negative feedback loop of NMOS pipe M31 provides, the source electrode output reference voltage Vrp of NMOS pipe M31;
The drain electrode of NMOS pipe M32 is connected with the source electrode of NMOS pipe M31, the second bias voltage that the grid access close loop negative feedback loop of NMOS pipe M32 provides, and NMOS manages the source electrode of M32 by isolation electrical part ground connection, the source electrode output reference voltage Vrn of NMOS pipe M32.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS pipe in open-loop branch is realized, while having avoided adopting in open-loop branch NMOS pipe and PMOS to manage simultaneously, the reference voltage that needs large-sized PMOS pipe and cause is set up the problem that speed is slow, circuit power consumption is larger, can Rapid Establishment reference voltage Vrp and Vrn, reduce the power consumption of circuit; And NMOS pipe adopts source class follower to connect in this programme, and grid decoupling capacitance is connected to ground, reduced the coupling of power lead to output terminal, can access good PSRR, thereby improve circuit performance.
And, the reference voltage driving circuit of this programme, circuit structure is simple, does not need the large bulk capacitance outside sheet, neither needs to increase extra chip bonding pad and package pins, has reduced again circuit power consumption, has optimized circuit performance.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the reference voltage drive scheme under existing Low ESR technology;
The circuit diagram of the driving circuit of a kind of reference voltage that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 provides the circuit diagram of the driving circuit of another kind of reference voltage for the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
The driving circuit of the reference voltage of the present embodiment drives an open-loop branch to realize by a close loop negative feedback loop.Close loop negative feedback loop provides initial reference magnitude of voltage accurately, and open-loop branch provides output driving current, produces reference voltage.Referring to Fig. 2, the circuit diagram of the driving circuit of a kind of reference voltage providing for the embodiment of the present invention, this driving circuit comprises close loop negative feedback loop and open-loop branch, described open-loop branch comprises NMOS pipe M31 and NMOS pipe M32;
The drain electrode of NMOS pipe M31 is connected to power vd D, the first bias voltage that the grid access close loop negative feedback loop of NMOS pipe M31 provides, the source electrode output reference voltage Vrp of NMOS pipe M31, the connected mode that NMOS pipe M31 drain electrode is connected to power vd D has buffer action, and NMOS pipe M31 grid is implemented to ground decoupling zero by decoupling capacitance 25, and this structure has improved the PSRR of circuit.
By upper, in the present embodiment, the connected mode of NMOS pipe M31 drain electrode, source electrode and grid and the structure that grid is implemented to ground decoupling zero by decoupling capacitance 25 have good buffer action, have reduced the coupling of power lead to output terminal, have improved the PSRR of circuit.
The drain electrode of NMOS pipe M32 is connected with the source electrode of NMOS pipe M31, the second bias voltage that the grid access close loop negative feedback loop of NMOS pipe M32 provides, and NMOS manages the source electrode of M32 by isolation electrical part ground connection, the source electrode output reference voltage Vrn of NMOS pipe M32.
Above-mentioned isolation electrical part can be realized by a NMOS pipe, also can be realized by resistance, and this isolation electrical part does not advise adopting PMOS pipe to realize.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS pipe in open-loop branch is realized, while having avoided adopting in open-loop branch NMOS pipe and PMOS to manage simultaneously, the reference voltage that needs large-sized PMOS pipe and cause is set up the problem that speed is slow, circuit power consumption is larger, can Rapid Establishment reference voltage Vrp and Vrn, reduce the power consumption of circuit; And this programme has reduced the coupling of power lead to output terminal, can access good PSRR, thereby improve circuit performance.
And, the driving circuit of the reference voltage of this programme, circuit structure is simple, does not need the large bulk capacitance outside sheet, has both reduced circuit power consumption, has optimized circuit performance, has improved again the universal of circuit, is convenient to actual use.
Referring to Fig. 3, for the embodiment of the present invention provides the circuit diagram of the driving circuit of another kind of reference voltage.In the scene of Fig. 3, isolation electrical part is realized by NMOS pipe M33, in open-loop branch, only comprises NMOS pipe.The 3rd bias voltage that the grid access close loop negative feedback loop of NMOS pipe M33 provides, the source ground of described NMOS pipe M33.
Described close loop negative feedback loop comprises branch road 21, and branch road 21 comprises NMOS pipe M34, NMOS pipe M35 and NMOS pipe M36, and branch road 21 is set to electric current on branch road 21 and the proportionate relationship of the electric current in open-loop branch is 1:K, wherein,
The drain electrode of NMOS pipe M34 is connected to power vd D, and the grid of NMOS pipe M34 accesses the first bias voltage and is connected with the grid of NMOS pipe M31, and the source electrode of NMOS pipe M34 is connected with the drain electrode of NMOS pipe M35;
The grid of NMOS pipe M35 accesses the second bias voltage and is connected with the grid of NMOS pipe M32, and the source electrode of NMOS pipe M35 is connected with the drain electrode of NMOS pipe M36;
Grid access the 3rd bias voltage of NMOS pipe M36 is also connected with the grid of NMOS pipe M33, the source ground of NMOS pipe M36.
Close loop negative feedback loop comprises difference transport and placing device 40 and difference transport and placing device 41, and described driving circuit also comprises bias current sources, specific as follows:
The difference amplifier positive input terminal access initial reference voltage Vrpin(Vrpin of difference transport and placing device 40 is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS pipe M34, the output terminal of difference transport and placing device 40 connects one end of charge pump 24, the other end of charge pump 24 is connected to the grid of NMOS pipe M34, and the grid of managing M34 and NMOS pipe M31 to NMOS provides described the first bias voltage;
The difference amplifier positive input terminal access initial reference voltage Vrnin(Vrnin of difference transport and placing device 41 is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS pipe M35, the output terminal of difference transport and placing device 41 is connected to the grid of NMOS pipe M35, and the grid of managing M35 and NMOS pipe M32 to NMOS provides described the second bias voltage;
The output terminal of bias current sources (Ibias) is connected to the drain electrode of NMOS pipe M37, the source electrode of NMOS pipe M37 is connected with the drain electrode of NMOS pipe M38, the source ground of NMOS pipe M38, the grid of the output terminal of bias current sources and NMOS pipe M38 is all connected to the grid of NMOS pipe M36, and the grid of managing M36 and NMOS pipe M33 to NMOS provides described the 3rd bias voltage.
As shown in Figure 3, ADC reference voltage Vrp and Vrn are exported by open-loop branch 20, and this open-loop branch 20 is driven by close loop negative feedback loop 19.Close loop negative feedback loop 19 is usingd the breadth length ratio relation of 1:K and is copied branch road 21 as the second level of close loop negative feedback loop according to open-loop branch 20, copying here refers to that open-loop branch 20 is identical with quantity with the part category in branch road 21, structure is closely similar, and the proportionate relationship of the electric current of the electric current of branch road 21 and open-loop branch 20 is 1:K, for example, when the device in open-loop branch 20 and branch road 21 is all NMOS pipe, the proportionate relationship of the breadth length ratio of NMOS pipe in can branch road 21 and the breadth length ratio of the NMOS pipe of open-loop branch 20 is set to 1:K, thereby can guarantee that branch road 21 and open-loop branch 20 corresponding node voltages equate and size of current pass is 1:K.
Input voltage Vrpin and Vrnin, by being produced by band-gap reference and generating circuit from reference voltage 30, according to the negative feedback characteristic of loop 22 and loop 23, make the source voltage values of NMOS pipe M34 and NMOS pipe M35 equal respectively Vrpin and Vrnin.
For rational DC point being provided to open-loop branch 20 and branch road 21, in loop 22, introduced charge pump 24.Charge pump 24 comprises capacitor C 1 and capacitor C 2, one end of capacitor C 1 is switched on or switched off with DC voltage Vbn2 by K switch 11 and is switched on or switched off by K switch 21 and one end of capacitor C 2, and the other end of capacitor C 1 is switched on or switched off with power vd D by K switch 12 and is switched on or switched off by K switch 22 and the other end of capacitor C 2; One end of capacitor C 2 is also connected to the output terminal of difference transport and placing device 40, and the other end of capacitor C 2 is also connected to the grid of NMOS pipe M34.
Clk1 and clk2 are the two-phase work clocks of charge pump, and Vbn2 is DC voltage.Clk1 and clk2 are not identical, according to the closed and unlatching of clk1 gauge tap K11 and K12, according to the closed and unlatching of clk2 gauge tap K21 and K22.This charge pump makes the first bias voltage of the grid of voltage Vop(access NMOS pipe M34) than voltage Vop1, increased C1 (VDD-Vbn2)/(C1+C2), by adjusting Vbn2, can adjust the numerical value of the first bias voltage, thereby guaranteed that the first bias voltage on the grid of NMOS pipe M34 is enough large, to guarantee that NMOS pipe M31 and M34 normally work.
M32 and M35 gate voltage are provided by the voltage Von of the output terminal of difference transport and placing device 41, M33, M36 and M38, and M32, and M35 and M37 form current mirror, and Ibias is input bias current, and current mirror provides gate voltage (i.e. the 3rd bias voltage) for M33 and M36.
Optionally, also for NMOS pipe is provided with decoupling capacitance 25, decoupling capacitance 26 and decoupling capacitance 27, is respectively gate voltage and realizes pressure stabilization function.Wherein, the grid of NMOS pipe M34 is also connected to one end of electric capacity 25, the other end ground connection of electric capacity 25, thus NMOS pipe M31 grid can be implemented to ground decoupling zero by decoupling capacitance 25, has reduced the coupling of power lead to output terminal, has improved the PSRR of circuit; The grid of NMOS pipe M35 is also connected to one end of electric capacity 26, the other end ground connection of electric capacity 26; The grid of NMOS pipe M36 is also connected to one end of electric capacity 27, the other end ground connection of electric capacity 27.
Optionally, the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS pipe M34 by resistance R 1; The difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS pipe M35 by resistance R 2.By resistance R 1 and resistance R 2, play the effect of burning voltage and electric current.
From the above mentioned, the present embodiment is only realized by nmos source follower as the open-loop branch 20 of output terminal, and circuit is realized simple, and can provide larger drive current for reference voltage Vrp and Vrn, to realize reference voltage faster, sets up.Nmos source follower in this open-loop branch 20 has good buffer action, has avoided the impact of voltage dithering divided ring branch road, has guaranteed the stability of open-loop branch; And reduced the coupling of power lead to output terminal, realized higher PSRR.Because open-loop branch adopts NMOS pipe, realize, the requirement of setting up speed for meeting identical output voltage, drives branch road than PMOS pipe, and this scheme only needs less design size, thereby has reduced current drain, has saved power consumption.
And, in the present embodiment, adopt NMOS pipe M33 as isolation electrical part, and adopt current mirror for the mode that NMOS pipe M33 provides gate voltage, can improve the reference voltage Vrp of output and the precision of Vrn.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS pipe in open-loop branch is realized, while having avoided adopting in open-loop branch NMOS pipe and PMOS to manage simultaneously, the reference voltage that needs large-sized PMOS pipe and cause is set up the problem that speed is slow, circuit power consumption is larger, can Rapid Establishment reference voltage Vrp and Vrn, reduce the power consumption of circuit; And NMOS pipe adopts source class follower to connect in this programme, and grid decoupling capacitance is connected to ground, reduced the coupling of power lead to output terminal, can access good PSRR, thereby improve circuit performance.
And, the reference voltage driving circuit of this programme, circuit structure is simple, does not need the large bulk capacitance outside sheet, neither needs to increase extra chip bonding pad and package pins, has reduced again circuit power consumption, has optimized circuit performance.
Shown in the driving circuit of another reference voltage that the embodiment of the present invention provides and Fig. 3, the difference of driving circuit is mainly, isolation electrical part adopts resistance R 33 to realize, in Fig. 3, the position of NMOS pipe M36 also adopts resistance to realize, bias current sources Ibias in Fig. 3, NMOS pipe M37 and M38 can remove, and the miscellaneous part in Fig. 3 remains unchanged.
Concrete, one end of resistance R 33 is connected to the source electrode of NMOS pipe M32, the other end ground connection of described resistance R 33.
Close loop negative feedback loop comprises branch road 21, branch road 21 comprises NMOS pipe M34, NMOS pipe M35 and resistance R 36, by making branch road 21 be set to electric current on branch road 21 and the proportionate relationship of the electric current in open-loop branch is 1:K to the setting of the breadth length ratio of NMOS pipe and to the setting of resistance, wherein
The drain electrode of NMOS pipe M34 is connected to power vd D, and the grid of NMOS pipe M34 accesses the first bias voltage and is connected with the grid of NMOS pipe M31, and the source electrode of NMOS pipe M34 is connected with the drain electrode of NMOS pipe M35;
The grid of NMOS pipe M35 accesses the second bias voltage and is connected with the grid of NMOS pipe M32, and the source electrode of NMOS pipe M35 is connected with one end of resistance R 36;
The other end ground connection of resistance R 36.
The difference amplifier positive input terminal access initial reference voltage Vrpin(Vrpin of difference transport and placing device 40 is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 40 is connected to the source electrode of NMOS pipe M34, the output terminal of difference transport and placing device 40 connects one end of charge pump 24, the other end of charge pump 24 is connected to the grid of NMOS pipe M34, and the grid of managing M34 and NMOS pipe M31 to NMOS provides described the first bias voltage;
The difference amplifier positive input terminal access initial reference voltage Vrnin(Vrnin of difference transport and placing device 41 is produced by band-gap reference and generating circuit from reference voltage 30), the difference amplifier negative input end of difference transport and placing device 41 is connected to the source electrode of NMOS pipe M35, the output terminal of difference transport and placing device 41 is connected to the grid of NMOS pipe M35, and the grid of managing M35 and NMOS pipe M32 to NMOS provides described the second bias voltage.
From the above mentioned, the source follower that the embodiment of the present invention is formed by NMOS pipe in open-loop branch is realized, while having avoided adopting in open-loop branch NMOS pipe and PMOS to manage simultaneously, the reference voltage that needs large-sized PMOS pipe and cause is set up the problem that speed is slow, circuit power consumption is larger, can Rapid Establishment reference voltage Vrp and Vrn, reduce the power consumption of circuit; And this programme has reduced the coupling of power lead to output terminal, can access good PSRR, thereby improve circuit performance.
And, the driving circuit of the reference voltage of this programme, circuit structure is simple, does not need the large bulk capacitance outside sheet, has both reduced circuit power consumption, has optimized circuit performance, has improved again the universal of circuit, is convenient to actual use.
The foregoing is only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.All any modifications of doing within the spirit and principles in the present invention, be equal to replacement, improvement etc., be all included in protection scope of the present invention.
Claims (10)
1. a driving circuit for reference voltage, is characterized in that, described driving circuit comprises close loop negative feedback loop and open-loop branch, and described open-loop branch comprises N NMOS N-channel MOS N NMOS pipe (M31) and NMOS pipe (M32);
The drain electrode of NMOS pipe (M31) is connected to power vd D, the first bias voltage that the grid access close loop negative feedback loop of NMOS pipe (M31) provides, the source electrode output reference voltage Vrp of NMOS pipe (M31);
The drain electrode of NMOS pipe (M32) is connected with the source electrode of NMOS pipe (M31), the second bias voltage that the grid access close loop negative feedback loop of NMOS pipe (M32) provides, the source electrode of NMOS pipe (M32) is by isolation electrical part ground connection, the source electrode output reference voltage Vrn of NMOS pipe (M32).
2. driving circuit according to claim 1, is characterized in that,
Described isolation electrical part is NMOS pipe (M33), the drain electrode of described NMOS pipe (M33) is connected to the source electrode of NMOS pipe (M32), the 3rd bias voltage that the grid access close loop negative feedback loop of described NMOS pipe (M33) provides, the source ground of described NMOS pipe (M33).
3. driving circuit according to claim 2, it is characterized in that, described close loop negative feedback loop comprises branch road (21), branch road (21) comprises NMOS pipe (M34), NMOS pipe (M35) and NMOS pipe (M36), branch road (21) is set to electric current on branch road (21) and the proportionate relationship of the electric current in open-loop branch is 1:K, wherein
The drain electrode of NMOS pipe (M34) is connected to power vd D, and the grid of NMOS pipe (M34) accesses the first bias voltage and is connected with the grid of NMOS pipe (M31), and the source electrode of NMOS pipe (M34) is connected with the drain electrode of NMOS pipe (M35);
The grid of NMOS pipe (M35) accesses the second bias voltage and is connected with the grid of NMOS pipe (M32), and the source electrode of NMOS pipe (M35) is connected with the drain electrode of NMOS pipe (M36);
Grid access the 3rd bias voltage of NMOS pipe (M36) is also connected with the grid of NMOS pipe (M33), the source ground of NMOS pipe (M36).
4. driving circuit according to claim 3, is characterized in that, described close loop negative feedback loop comprises difference transport and placing device (40) and difference transport and placing device (41), and described driving circuit also comprises bias current sources,
The difference amplifier positive input terminal access initial reference voltage Vrpin of difference transport and placing device (40), the difference amplifier negative input end of difference transport and placing device (40) is connected to the source electrode of NMOS pipe (M34), the output terminal of difference transport and placing device (40) connects one end of charge pump (24), the other end of charge pump (24) is connected to the grid of NMOS pipe (M34), and the grid of managing (M34) and NMOS pipe (M31) to NMOS provides described the first bias voltage;
The difference amplifier positive input terminal access initial reference voltage Vrnin of difference transport and placing device (41), the difference amplifier negative input end of difference transport and placing device (41) is connected to the source electrode of NMOS pipe (M35), the output terminal of difference transport and placing device (41) is connected to the grid of NMOS pipe (M35), and the grid of managing (M35) and NMOS pipe (M32) to NMOS provides described the second bias voltage;
The output terminal of bias current sources is connected to the drain electrode of NMOS pipe (M37), and the source electrode of NMOS pipe (M37) is connected with the drain electrode of NMOS pipe (M38), the source ground of NMOS pipe (M38),
The grid of the output terminal of bias current sources and NMOS pipe (M38) is all connected to the grid of NMOS pipe (M36), and the grid of managing (M36) and NMOS pipe (M33) to NMOS provides described the 3rd bias voltage.
5. driving circuit according to claim 4, is characterized in that,
The difference amplifier negative input end of difference transport and placing device (40) is connected to the source electrode of NMOS pipe (M34) by resistance (R1);
The difference amplifier negative input end of difference transport and placing device (41) is connected to the source electrode of NMOS pipe (M35) by resistance (R2).
6. driving circuit according to claim 4, is characterized in that,
The grid of NMOS pipe (M34) is also connected to one end of electric capacity (25), the other end ground connection of electric capacity (25);
The grid of NMOS pipe (M35) is also connected to one end of electric capacity (26), the other end ground connection of electric capacity (26);
The grid of NMOS pipe (M36) is also connected to one end of electric capacity (27), the other end ground connection of electric capacity (27).
7. driving circuit according to claim 4, is characterized in that, described charge pump (24) comprises electric capacity (C1) and electric capacity (C2),
One end of electric capacity (C1) is switched on or switched off with DC voltage Vbn2 by switch (K11) and passes through switch (K21) and is switched on or switched off with one end of electric capacity (C2), and the other end of electric capacity (C1) is switched on or switched off with power vd D by switch (K12) and passes through switch (K22) and is switched on or switched off with the other end of electric capacity (C2);
One end of electric capacity (C2) is also connected to the output terminal of difference transport and placing device (40), and the other end of electric capacity (C2) is also connected to the grid of NMOS pipe (M34).
8. driving circuit according to claim 1, is characterized in that, described isolation electrical part is resistance (R33), and one end of described resistance (R33) is connected to the source electrode of NMOS pipe (M32), the other end ground connection of described resistance (R33).
9. driving circuit according to claim 8, it is characterized in that, described close loop negative feedback loop comprises branch road (21), branch road (21) comprises that NMOS pipe (M34), NMOS manage (M35) and resistance (R36), branch road (21) is set to electric current on branch road (21) and the proportionate relationship of the electric current in open-loop branch is 1:K, wherein
The drain electrode of NMOS pipe (M34) is connected to power vd D, and the grid of NMOS pipe (M34) accesses the first bias voltage and is connected with the grid of NMOS pipe (M31), and the source electrode of NMOS pipe (M34) is connected with the drain electrode of NMOS pipe (M35);
The grid of NMOS pipe (M35) accesses the second bias voltage and is connected with the grid of NMOS pipe (M32), and the source electrode of NMOS pipe (M35) is connected with one end of resistance (R36);
The other end ground connection of resistance (R36).
10. driving circuit according to claim 9, is characterized in that, described close loop negative feedback loop comprises difference transport and placing device (40) and difference transport and placing device (41),
The difference amplifier positive input terminal access initial reference voltage Vrpin of difference transport and placing device (40), the difference amplifier negative input end of difference transport and placing device (40) is connected to the source electrode of NMOS pipe (M34), the output terminal of difference transport and placing device (40) connects one end of charge pump (24), the other end of charge pump (24) is connected to the grid of NMOS pipe (M34), and the grid of managing (M34) and NMOS pipe (M31) to NMOS provides described the first bias voltage;
The difference amplifier positive input terminal access initial reference voltage Vrnin of difference transport and placing device (41), the difference amplifier negative input end of difference transport and placing device (41) is connected to the source electrode of NMOS pipe (M35), the output terminal of difference transport and placing device (41) is connected to the grid of NMOS pipe (M35), and the grid of managing (M35) and NMOS pipe (M32) to NMOS provides described the second bias voltage.
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| CN105049041A (en) * | 2015-08-28 | 2015-11-11 | 西安启微迭仪半导体科技有限公司 | Low-power on-chip reference voltage driving circuit applied to high-speed analog-digital converter |
| CN105049047A (en) * | 2015-08-28 | 2015-11-11 | 西安启微迭仪半导体科技有限公司 | Reference voltage driving circuit of analogue-to-digital converter |
| CN108563276A (en) * | 2018-06-01 | 2018-09-21 | 电子科技大学 | A kind of high speed Voltage Reference Buffer with cross-couplings filter network |
| CN108874006A (en) * | 2017-05-10 | 2018-11-23 | 深圳清华大学研究院 | reference voltage driving circuit |
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| CN105049041A (en) * | 2015-08-28 | 2015-11-11 | 西安启微迭仪半导体科技有限公司 | Low-power on-chip reference voltage driving circuit applied to high-speed analog-digital converter |
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| CN105049041B (en) * | 2015-08-28 | 2018-12-25 | 西安启微迭仪半导体科技有限公司 | Low-power consumption piece internal reference Voltag driving circuit applied to high-speed AD converter |
| CN105049047B (en) * | 2015-08-28 | 2019-03-08 | 西安启微迭仪半导体科技有限公司 | A kind of driving circuit of analog-digital converter reference voltage |
| CN108874006A (en) * | 2017-05-10 | 2018-11-23 | 深圳清华大学研究院 | reference voltage driving circuit |
| CN108563276A (en) * | 2018-06-01 | 2018-09-21 | 电子科技大学 | A kind of high speed Voltage Reference Buffer with cross-couplings filter network |
| CN111367341A (en) * | 2018-12-26 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Reference voltage generating circuit and NAND chip |
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