CN108520882A - 一种阵列基板及制造该阵列基板的掩膜板 - Google Patents

一种阵列基板及制造该阵列基板的掩膜板 Download PDF

Info

Publication number
CN108520882A
CN108520882A CN201810319342.8A CN201810319342A CN108520882A CN 108520882 A CN108520882 A CN 108520882A CN 201810319342 A CN201810319342 A CN 201810319342A CN 108520882 A CN108520882 A CN 108520882A
Authority
CN
China
Prior art keywords
segment
drain electrode
source electrode
mask plate
compensation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810319342.8A
Other languages
English (en)
Other versions
CN108520882B (zh
Inventor
刘司洋
徐向阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201810319342.8A priority Critical patent/CN108520882B/zh
Publication of CN108520882A publication Critical patent/CN108520882A/zh
Application granted granted Critical
Publication of CN108520882B publication Critical patent/CN108520882B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供一种阵列基板及其制造用的掩膜板,所述掩膜板包括用于形成薄膜晶体管中源极和漏极的源极图块和漏极图块;所述源极图块与所述阵列基板的源极相对应,所述漏极图块与所述阵列基板的漏极相对应;其中,所述源极图块和/或所述漏极图块包括位于其边缘的凸起状补偿图块。

Description

一种阵列基板及制造该阵列基板的掩膜板
技术领域
本发明涉及显示面板领域,尤其涉及一种阵列基板及制造该阵列基板的掩膜板。
背景技术
在TFT-LCD显示领域中,随着对画面分辨率的不断提高,像素尺寸不断减小,对设计和制程提出了更高的要求。在制程能力限制的情况下,普通的像素设计方法一般只能将线宽做到3um以上。在制程能力限制的情况下,若将光罩(Mask)上线宽设计得很窄(<3um),则实际做出来的图形可能不能得到预想的宽度,出现断线或者线宽不均的现象。对于TFT-LCD面板内尤其关键的器件TFT,一般的实际如附图1所示。若当D、S减小到很小时(<3um),TFT实做就会出现断线或不均,从而降低面板的品质。
综上所述,现有技术的TFT-LCD面板,在TFT制备过程中,当Mask线宽设计得很窄时,TFT就会出现断线或不均,从而降低面板的品质。
发明内容
本发明提供一种阵列基板及制造该阵列基板的掩膜板,能够将掩膜板的线宽设计的很窄,满足更小尺寸的TFT设计需求,避免TFT出现断线或不均现象,进而提高显示面板的性能。
为解决上述问题,本发明提供的技术方案如下:
本发明提供一种阵列基板,包括:
基板;
漏极,制备于所述基板上,所述漏极的纵截面的形状为马蹄状,所述纵截面为平行于所述基板的截面;
源极,所述源极对应所述漏极的凹部制备于所述基板上,且与所述漏极绝缘设置;
其中,所述漏极与所述源极的线宽均小于5um,且所述漏极以及所述源极各处线宽均保持均一。
本发明还提供一种制造阵列基板的掩膜板,所述掩膜板包括用于形成薄膜晶体管中源极和漏极的源极图块和漏极图块;
所述源极图块与所述阵列基板的所述源极相对应,所述漏极图块与所述阵列基板的所述漏极相对应;
其中,所述源极图块和/或所述漏极图块包括位于其边缘的凸起状补偿图块。
根据本发明一优选实施例,所述漏极图块包括沿所述漏极图块轮廓线均匀分布的凸起状的第一补偿图块,所述第一补偿图块通过所述漏极图块的边缘部位向外延伸形成。
根据本发明一优选实施例,所述第一补偿图块包括为锯齿状,所述第一补偿图块的齿尖朝向外侧,齿根到齿尖的长度范围为0.2um~2um。
根据本发明一优选实施例,所述漏极图块还包括用于形成实际所需线宽的第一本体图块,所述第一本体图块的宽度小于5um。
根据本发明一优选实施例,所述漏极图块包括至少一个由所述漏极图块端部向外凸起形成的第二补偿图块。
根据本发明一优选实施例,所述第二补偿图块的形状为矩形,且边长的范围在0.2um~2um。
根据本发明一优选实施例,所述源极图块包括沿所述源极图块轮廓线均匀分布的凸起状的第三补偿图块,所述第三补偿图块通过所述源极图块的边缘部位向外延伸形成。
根据本发明一优选实施例,所述源极图块包括至少一个由所述源极图块端部向外凸起形成的第四补偿图块;所述源极图块还包括用于形成实际所需线宽的第二本体图块,所述第二本体图块的宽度小于5um。
根据本发明一优选实施例,所述第三补偿图块包括为锯齿状,所述第三补偿图块的齿尖朝向外侧,齿根到齿尖的长度范围为0.2um~2um;
所述第四补偿图块的形状为矩形,且边长的范围在0.2um~2um。
本发明的有益效果为:相较于现有的TFT-LCD面板,本发明的阵列基板及制造该阵列基板的掩膜板,通过将制备TFT器件的掩膜板平滑的外轮廓设计为锯齿状,即把掩膜板设计成TFT器件所需的线宽外加上锯齿状结构,由此形成的图形较为均匀,不会出现断线,仅在首尾处变窄。因此,本方案还采用在首尾两端增加serif补偿(补偿图块),如此可获得小尺寸TFT的均匀精确成形。本发明提供的掩膜板,线宽可设计的很窄,满足更小尺寸的TFT设计需求,避免TFT出现断线或不均现象,进而提高显示面板的性能。同时,因为TFT能够设计的很小,还可以使相应的显示面板实现窄边化。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有的TFT在掩膜板上设计的结构示意图;
图2为本发明提供的用于制造阵列基板的掩膜板结构示意图;
图3a-3b为采用现有技术中的掩膜板和本发明实施例提供的掩膜板形成的薄膜晶体管的源极局部图形曝光光强的对比图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有技术的TFT-LCD面板,在TFT制备过程中,当Mask线宽设计得很窄时,TFT就会出现断线或不均,从而降低面板的品质的技术问题,本实施例能够解决该缺陷。
如图2所示,为本发明提供的用于制造阵列基板的掩膜板结构示意图,所述掩膜板包括:不透光区域,对应待实施光罩制程的显示器件的预设图案区域,所述不透光区域包括源极图块21和漏极图块22;透光区域,对应所述待实施光罩制程的显示器件的刻蚀区域;所述不透光区域与所述透光区域间隔设置于所述掩膜板上。其中,所述源极图块21与所述阵列基板的所述源极相对应,所述漏极图块22与所述阵列基板的所述漏极相对应;所述漏极图块22的形状为马蹄状,所述源极图块21正对于所述漏极图块22的凹部设计,且所述源极图块21与所述漏极图块22之间存在间隙,所述间隙对应所述阵列基板的薄膜晶体管的沟道区。所述漏极图块22包括沿所述漏极图块22轮廓线均匀分布的凸起状的第一补偿图块221,且所述第一补偿图块221是通过所述漏极图块22的边缘部位向外延伸形成的,图示给出的所述第一补偿图块221分布于所述漏极图块22的局部轮廓线,此处不做限制。其中,所述第一补偿图块221可为锯齿状,所述第一补偿图块221的齿尖朝向外侧,齿根到齿尖的长度范围为0.2um~2um,优选为0.5um~1.5um。所述漏极图块22还包括用于形成实际所需线宽的第一本体图块223,所述第一本体图块223的宽度小于5um,,优选为小于3um。所述漏极图块22还包括第二补偿图块222,所述第二补偿图块222是由所述漏极图块22的两端部向外延伸形成的。所述第二补偿图块222的形状为矩形,且边长的范围在0.2um~2um,优选为所述边长在0.5um~1.5um之间的正方形。所述第二补偿图块222靠近所述第一补偿图块221一侧设置于所述漏极图块22的端部,且与所述第一补偿图块221连接,所述第二补偿图块222还可以设置为多个,并沿所述端部排列。
除上述图示外,所述漏极图块22还可形成一圈环绕所述轮廓线的补偿图块。所述第一补偿图块221的锯齿状图形可由多个连续排列的三角形图形组成。进一步地,组成所述锯齿状图形的各三角形图形的尺寸一致。还可将组成所述锯齿状图形的三角形图形的尺寸设置为沿设定方向依次排列。所述第一补偿图块221的形状还可设计成多个连续排列的半圆形或弧形状的凸起。
本发明提供的所述源极图块21的局部图如图3a中的a所示,所述源极图块21包括沿所述源极图块21轮廓线均匀分布的凸起状的第三补偿图块212,所述第三补偿图块212通过所述源极图块21的边缘部位向外延伸形成。所述源极图块21还包括至少一个由所述源极图块21端部向外凸起形成的第四补偿图块213;所述源极图块21还包括用于形成实际所需线宽的第二本体图块211,所述第二本体图块211的宽度小于5um,优选的,所述宽度小于3um。优选地,所述第三补偿图块212与所述第一补偿图块221保持一致,所述第四补偿图块213与所述第二补偿图块222保持一致。
所述源极图块21与所述漏极图块22之间具有一设定距离,所述设定距离可设置为小于3um;当所述漏极图块22形成一圈环绕轮廓线的所述第一补偿图块221时,分布于所述源极图块21轮廓线的所述第三补偿图块212以及所述第四补偿图块213与所述漏极图块22的所述第一补偿图块221相对的两个顶角之间的距离可设置为小于2um,当要求TFT设计的更小时,两个顶角之间的距离可设置为0.5um~1um之间。
参见图3a-3b,为采用现有技术中的掩膜板和本发明实施例提供的掩膜板形成的薄膜晶体管的源极局部图形曝光光强的对比图。采用本发明实施例提供的上述掩膜板来对源漏金属层进行曝光刻蚀时,由于不透光区域边缘分布有补偿图块,曝光后可形成较为均匀图形。以所述掩膜板的部分源极图块为例,在所述源极图块a的边缘分布有第三补偿图块212,其中,所述源极图块a为实际所需线宽的第二本体图块211外加上锯齿状的所述第三补偿图块212,其中所述第二本体图块211线宽选取2um,所述第三补偿图块212的锯齿边长选取为1um。则曝光时的光强分布如图3b中左侧的a’所示,可预期实际形成的图形较为均匀,仅在首位处变窄,故本发明又在所述源极图块a的首尾两端增加有正方形的第四补偿图块213,如此可获得小尺寸TFT的均匀精确成形。而现有技术的掩膜板的源极图块b为平滑的轮廓,当线宽较小时,实际曝光时的光强分布如图3b中右侧的b’所示,可预测实际形成的图形完全变形,甚至存在断线的可能。
本发明提供的掩膜板,可以减小曝光对不透光区域的影响,而补偿图块的设计,既不会造成实际图形线宽的增大,同时也不会造成刻蚀过量引起断线或者不均现象,在保证预设线宽的情况下,尽量减小曝光对不透光区域的影响,从而避免TFT出现断线或不均现象,进而提高显示面板的性能。
采用上述掩膜板对形成在衬底基板上的金属层进行构图,在所述金属层中形成与所述掩膜板的不透光区域图形一致的源漏极图案。本发明采用上述形式制备的阵列基板,包括:基板;漏极,制备于所述基板上,所述漏极的纵截面的形状为马蹄状,所述纵截面为平行于所述基板的截面;源极,所述源极对应所述漏极的凹部制备于所述基板上,且与所述漏极绝缘设置;其中,所述漏极与所述源极的线宽均小于5um,且所述漏极以及所述源极的各处线宽均保持均一。优选的,所述源极与所述漏极的电极线宽均小于3um。
相较于现有的TFT-LCD面板,本发明的阵列基板及制造该阵列基板的掩膜板,通过将制备TFT器件的掩膜板平滑的外轮廓设计为锯齿状,即把掩膜板设计成TFT器件所需的线宽外加上锯齿状结构,由此形成的图形较为均匀,不会出现断线,仅在首尾处变窄。因此,本方案还采用在首尾两端增加serif补偿(补偿图块),如此可获得小尺寸TFT的均匀精确成形。本发明提供的掩膜板,线宽可设计的很窄,满足更小尺寸的TFT设计需求,避免TFT出现断线或不均现象,进而提高显示面板的性能。同时,因为TFT能够设计的很小,还可以使相应的显示面板实现窄边化。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种阵列基板,其特征在于,包括:
基板;
漏极,制备于所述基板上,所述漏极的纵截面的形状为马蹄状,所述纵截面为平行于所述基板的截面;
源极,所述源极对应所述漏极的凹部制备于所述基板上,且与所述漏极绝缘设置;
其中,所述漏极与所述源极的线宽均小于5um,且所述漏极以及所述源极各处线宽均保持均一。
2.一种制造阵列基板的掩膜板,其特征在于,所述掩膜板包括用于形成薄膜晶体管中源极和漏极的源极图块和漏极图块;
所述源极图块与所述阵列基板的所述源极相对应,所述漏极图块与所述阵列基板的所述漏极相对应;
其中,所述源极图块和/或所述漏极图块包括位于其边缘的凸起状补偿图块。
3.根据权利要求2所述的掩膜板,其特征在于,所述漏极图块包括沿所述漏极图块轮廓线均匀分布的凸起状的第一补偿图块,所述第一补偿图块通过所述漏极图块的边缘部位向外延伸形成。
4.根据权利要求3所述的掩膜板,其特征在于,所述第一补偿图块包括为锯齿状,所述第一补偿图块的齿尖朝向外侧,齿根到齿尖的长度范围为0.2um~2um。
5.根据权利要求4所述的掩膜板,其特征在于,所述漏极图块还包括用于形成实际所需线宽的第一本体图块,所述第一本体图块的宽度小于5um。
6.根据权利要求2所述的掩膜板,其特征在于,所述漏极图块包括至少一个由所述漏极图块端部向外凸起形成的第二补偿图块。
7.根据权利要求6所述的掩膜板,其特征在于,所述第二补偿图块的形状为矩形,且边长的范围在0.2um~2um。
8.根据权利要求2所述的掩膜板,其特征在于,所述源极图块包括沿所述源极图块轮廓线均匀分布的凸起状的第三补偿图块,所述第三补偿图块通过所述源极图块的边缘部位向外延伸形成。
9.根据权利要求8所述的掩膜板,其特征在于,所述源极图块包括至少一个由所述源极图块端部向外凸起形成的第四补偿图块;所述源极图块还包括用于形成实际所需线宽的第二本体图块,所述第二本体图块的宽度小于5um。
10.根据权利要求9所述的掩膜板,其特征在于,所述第三补偿图块包括为锯齿状,所述第三补偿图块的齿尖朝向外侧,齿根到齿尖的长度范围为0.2um~2um;
所述第四补偿图块的形状为矩形,且边长的范围在0.2um~2um。
CN201810319342.8A 2018-04-11 2018-04-11 一种阵列基板及制造该阵列基板的掩膜板 Active CN108520882B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810319342.8A CN108520882B (zh) 2018-04-11 2018-04-11 一种阵列基板及制造该阵列基板的掩膜板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810319342.8A CN108520882B (zh) 2018-04-11 2018-04-11 一种阵列基板及制造该阵列基板的掩膜板

Publications (2)

Publication Number Publication Date
CN108520882A true CN108520882A (zh) 2018-09-11
CN108520882B CN108520882B (zh) 2021-03-23

Family

ID=63432379

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810319342.8A Active CN108520882B (zh) 2018-04-11 2018-04-11 一种阵列基板及制造该阵列基板的掩膜板

Country Status (1)

Country Link
CN (1) CN108520882B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021077294A1 (zh) * 2019-10-22 2021-04-29 京东方科技集团股份有限公司 掩模板及其制作方法、有机发光装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8188481B2 (en) * 2009-10-05 2012-05-29 Hitachi Displays, Ltd. Display panel
CN102749801A (zh) * 2012-06-29 2012-10-24 北京京东方光电科技有限公司 一种掩模板
CN105137710A (zh) * 2015-07-15 2015-12-09 深圳市华星光电技术有限公司 掩膜版及薄膜晶体管的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8188481B2 (en) * 2009-10-05 2012-05-29 Hitachi Displays, Ltd. Display panel
CN102749801A (zh) * 2012-06-29 2012-10-24 北京京东方光电科技有限公司 一种掩模板
CN105137710A (zh) * 2015-07-15 2015-12-09 深圳市华星光电技术有限公司 掩膜版及薄膜晶体管的制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021077294A1 (zh) * 2019-10-22 2021-04-29 京东方科技集团股份有限公司 掩模板及其制作方法、有机发光装置
US11917893B2 (en) 2019-10-22 2024-02-27 Chengdu Boe Optoelectronics Technology Co., Ltd. Mask plate, method for manufacturing mask plate, and organic light-emitting device

Also Published As

Publication number Publication date
CN108520882B (zh) 2021-03-23

Similar Documents

Publication Publication Date Title
US8854588B2 (en) Liquid crystal display
CN100388105C (zh) 液晶显示基板及其修复方法
DE102006028322B4 (de) Flüssigkristallanzeigevorrichtung und Herstellungsverfahren
JP3831868B2 (ja) アクティブマトリックス表示装置とその製造方法
TWI571673B (zh) 曲面顯示面板
DE10150432B4 (de) Arraysubstrat für eine Flüssigkristallanzeige und Verfahren zu dessen Herstellung
US20030085406A1 (en) Process for producing inductor
CN102655095B (zh) 薄膜晶体管及阵列基板的制造方法
CN105788470A (zh) 一种圆形显示屏和圆形显示屏制造方法
CN101078841A (zh) 液晶显示装置及其制造方法
CN103235452B (zh) 一种阵列基板及显示装置
US7871743B2 (en) Gray scale mask
EP3236314B1 (en) Thin film patterning method
WO2020098032A1 (zh) 显示面板的制程方法、显示面板及显示装置
WO2016086642A1 (zh) 黑矩阵结构及制备方法、阵列基板、彩膜基板及显示装置
CN108198820B (zh) 一种阵列基板及其制备方法
KR20160087980A (ko) 액정 표시 장치
CN110275346A (zh) 一种曲面显示面板
CN102725680A (zh) 基板、针对基板的曝光方法、光取向处理方法
CN108520882A (zh) 一种阵列基板及制造该阵列基板的掩膜板
CN109324450B (zh) 一种阵列基板、液晶显示面板
CN106200169B (zh) 液晶显示面板及其制造方法
US20090289257A1 (en) Exposure mask using gray-tone pattern, manufacturing method of tft substrate using the same and liquid crystal display device having the tft substrate
CN110703515A (zh) 显示面板及其制作方法
CN104391349A (zh) 用于制作彩色滤光片的方法、彩色滤光片及液晶面板

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province

Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd.

Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province

Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant