CN108511395A - 一种具有双极应力的绝缘体上硅结构及其制造方法 - Google Patents

一种具有双极应力的绝缘体上硅结构及其制造方法 Download PDF

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CN108511395A
CN108511395A CN201810286263.1A CN201810286263A CN108511395A CN 108511395 A CN108511395 A CN 108511395A CN 201810286263 A CN201810286263 A CN 201810286263A CN 108511395 A CN108511395 A CN 108511395A
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silicon
layer
insulator
germanium
insulated substrate
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CN108511395B (zh
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马雁飞
王昌锋
廖端泉
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Shanghai Huali Microelectronics Corp
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Abstract

本发明提供了一种具有双极应力的绝缘体上硅结构及其制造方法，制造方法包括：提供复合衬底，复合衬底由下至上依次具有硅基体层、掩埋氧化物层和绝缘体上硅层；在绝缘体上硅层上表面外延生长硅锗层；沉积硬掩膜层以覆盖硅锗层对应N型MOS管区域的部分；沉积表面氧化物层以覆盖硅锗层和硬掩膜层；进行高温退火处理，以使绝缘体上硅层对应P型MOS管区域的部分转化为绝缘体上硅锗层，对应N型MOS管区域的部分转化为拉应力绝缘体上硅层；以及去除绝缘体上硅锗层和拉应力绝缘体上硅层表面多余的硅锗层、硬掩膜层和表面氧化物层。本发明所提供的制造方法步骤简单，所制造的器件电特性良好。

Description

一种具有双极应力的绝缘体上硅结构及其制造方法
技术领域
本发明涉及半导体元件，尤其涉及一种含有双极应力的绝缘体上硅结构及其制造方法
背景技术
自从早年德州仪器的Jack Kilby博士发明了集成电路之时起，科学家们和工程师们已经在半导体器件和工艺方面作出了众多发明和改进。近50年来，半导体尺寸已经有了明显的降低，这转化成不断增长的处理速度和不断降低的功耗。迄今为止，半导体的发展大致遵循着摩尔定律，摩尔定律大致是说密集集成电路中晶体管的数量约每两年翻倍。现在，半导体工艺正在朝着20nm以下发展，其中一些公司正在着手14nm工艺。这里仅提供一个参考，一个硅原子约为0.2nm，这意味着通过20nm工艺制造出的两个独立组件之间的距离仅仅约为一百个硅原子。
半导体器件制造因此变得越来越具有挑战性，并且朝着物理上可能的极限推进。半导体技术的近期发展之一已经是绝缘体上硅(SOI，Silicon-On-Insulator)在半导体制造中的利用。但目前的绝缘体上硅结构的半导体器件的电特性仍需调试。因此，亟需一种能够改善绝缘体上硅结构MOS管器件电特性的方法，以及具有较优电特性的绝缘体上硅结构。
发明内容
以下给出一个或多个方面的简要概述以提供对这些方面的基本理解。此概述不是所有构想到的方面的详尽综览，并且既非旨在指认出所有方面的关键性或决定性要素亦非试图界定任何或所有方面的范围。其唯一的目的是要以简化形式给出一个或多个方面的一些概念以为稍后给出的更加详细的描述之序。
如上所述，为提供一种具有较优电特性的绝缘体上硅结构MOS管器件，本发明提供了一种具有双极应力的绝缘体上硅结构的制造方法，包括：提供复合衬底，上述复合衬底由下至上依次具有硅基体层、掩埋氧化物层和绝缘体上硅层；在上述绝缘体上硅层上表面外延生长硅锗层；沉积硬掩膜层以覆盖上述硅锗层对应N型MOS管区域的部分；沉积表面氧化物层以覆盖上述硅锗层和上述硬掩膜层；进行高温退火处理，以使上述绝缘体上硅层对应P型MOS管区域的部分转化为绝缘体上硅锗层，对应上述N型MOS管区域的部分转化为拉应力绝缘体上硅层；以及去除上述绝缘体上硅锗层和上述拉应力绝缘体上硅层表面多余的上述硅锗层、上述硬掩膜层和上述表面氧化物层。
可选的，上述高温退火处理的温度范围为800－1300℃，时间为0.5－3小时。
可选的，上述沉积硬掩膜层的步骤进一步包括，采用接触蚀刻停止层工艺通过低压力化学气相沉积，或，等离子体增强化学气相沉积上述硬掩膜层。
可选的，上述去除步骤进一步包括，采用湿法去除多余的上述硅锗层、上述硬掩膜层和上述表面氧化物层，其中，采用稀氢氟酸去除上述表面氧化物层；采用磷酸去除上述硬掩膜层；以及采用硝酸、氢氟酸、乙酸和水的混合溶液去除上述硅锗层。
可选的，上述混合溶液进一步包括：上述硝酸的浓度为70％；上述氢氟酸的浓度为49％；上述乙酸的浓度为99.9％；以及上述硝酸、氢氟酸、乙酸和水的配比为40：1：2：57。
可选的，上述方法还包括：在上述绝缘体上硅锗层和上述拉应力绝缘体上硅层邻接部分形成STI浅沟槽隔离。
本发明还提供了一种具有双极应力的绝缘体上硅结构，上述绝缘体上硅结构形成在掩埋氧化物层上，上述掩埋氧化物层形成在硅基体层上，上述绝缘体上硅结构、上述掩埋氧化物层和上述硅基体层构成晶体管器件的复合衬底；其中，上述绝缘体上硅结构对应P型MOS管区域为绝缘体上硅锗结构，上述绝缘体上硅锗结构具有压应力，对应N型MOS管区域为拉应力绝缘体上硅结构。
可选的，上述绝缘体上硅结构还包括STI浅沟槽隔离结构，上述STI浅沟槽隔离结构位于上述绝缘体上硅锗结构和上述拉应力绝缘体上硅结构的邻接部分，其中，上述绝缘体上硅锗结构和上述拉应力绝缘体上硅结构邻接上述STI浅沟槽隔离结构的邻接部分结构均匀。
本发明还提供了一种具有双极应力的绝缘体上硅结构，采用如上述的制造方法制造上述绝缘体上硅结构。
本发明还提供了一种晶体管，上述晶体管包含如上述的具有双极应力的绝缘体上硅结构。
本发明所提供的实施例，对应PMOS管区域具有绝缘体上硅锗层，提高了PMOS管的空穴迁移率，对应NMOS管区域具有拉应力绝缘体上硅层，提高了NMOS管的电子迁移率，改善了晶体管的电特性，且本发明所提供的制备方法工艺简单，可操作性强。
附图说明
图1-8示出了根据本发明提供的制造方法一实施例制造的半导体结构示意图。
图9示出了根据本发明提供的制造方法另一实施例制造的半导体结构示意图。
图10示出了现有技术中半导体结构缺陷的示意图。
具体实施方式
本发明涉及半导体工艺与器件。更具体地，本发明的实施例提供一种绝缘体上硅结构，该绝缘体上硅结构具有双极应力，对应NMOS区域的绝缘体上硅层具有拉应力，对应PMOS区域的绝缘体上硅结构为绝缘体上硅锗层，具有压应力。本发明还提供了其他实施例。给出以下描述以使得本领域技术人员能够实施和使用本发明并将其结合到具体应用背景中。各种变型、以及在不同应用中的各种使用对于本领域技术人员将是容易显见的，并且本文定义的一般性原理可适用于较宽范围的实施例。由此，本发明并不限于本文中给出的实施例，而是应被授予与本文中公开的原理和新颖性特征相一致的最广义的范围。
在以下详细描述中，阐述了许多特定细节以提供对本发明的更透彻理解。然而，对于本领域技术人员显而易见的是，本发明的实践可不必局限于这些具体细节。换言之，公知的结构和器件以框图形式示出而没有详细显示，以避免模糊本发明。
请读者注意与本说明书同时提交的且对公众查阅本说明书开放的所有文件及文献，且所有这样的文件及文献的内容以参考方式并入本文。除非另有直接说明，否则本说明书(包含任何所附权利要求、摘要和附图)中所揭示的所有特征皆可由用于达到相同、等效或类似目的的可替代特征来替换。因此，除非另有明确说明，否则所公开的每一个特征仅是一组等效或类似特征的一个示例。
而且，权利要求中未明确表示用于执行特定功能的装置、或用于执行特定功能的步骤的任意组件皆不应被理解为如35USC第112章节第6段中所规定的装置或步骤条款。特别地，在此处的权利要求中使用“….的步骤”或“….的动作”并不表示涉及35USC§112第6段的规定。
注意，在使用到的情况下，标志左、右、前、后、顶、底、正、反、顺时针和逆时针仅仅是出于方便的目的所使用的，而并不暗示任何具体的固定方向。事实上，它们被用于反映对象的各个部分之间的相对位置和/或方向。
如本文使用的术语“在...上方(over)”、“在...下方(under)”、“在...之间(between)”和“在...上(on)”指的是这一层相对于其它层的相对位置。同样地，例如，被沉积或被放置于另一层的上方或下方的一层可以直接与另一层接触或者可以具有一个或多个中间层。此外，被沉积或被放置于层之间的一层可以直接与这些层接触或者可以具有一个或多个中间层。相比之下，在第二层“上”的第一层与该第二层接触。此外，提供了一层相对于其它层的相对位置(假设相对于起始基底进行沉积、修改和去除薄膜操作而不考虑基底的绝对定向)。
如上所述，半导体器件制造变得越来越具有挑战性，并且朝着物理上可能的极限推进。随着器件结构尺寸不断下降，工艺不断微缩，它所要求的薄栅氧层与短沟道会使得器件易产生漏电与低性能。半导体技术的近期发展之一已经是绝缘体上硅(SOI，Silicon-On-Insulator)在半导体制造中的利用。较于传统硅器件，超薄体耗尽型绝缘体上硅(FDSOI，Fully Depleted SOI)结构中的顶层硅膜厚度远小于沟道耗尽区的宽度，减少了源漏耗尽区和沟道耗尽区间的共享电荷，能够效抑制短沟道效应，因此超薄体FDSOI受到业界在纳米结构器件上应用的一致认可。但目前的绝缘体上硅结构的半导体器件的电特性仍需调试。本发明所提供了一种绝缘体上硅半导体器件的制造方法，本发明提供的制造方法步骤简单，且制造的器件电特性良好。具体的，本发明是根据如下描述的步骤实现的。
图1-8示出了图解根据本发明一实施例的用于提供绝缘体上硅结构工艺流程的简化示图。这些示图仅提供示例，不应不当地限制权利要求的范围。本领域技术人员将领会到有许多变体、替换方案、以及变型。取决于实现，可以添加、移除、重复、重新排列、修改、替换、和/或交迭一个或更多个步骤，并且这不影响权利要求的保护范围。
如图1所示，首先提供本发明所使用的复合衬底，复合衬底由下至上依次具有硅基体层110、掩埋氧化物层120和绝缘体上硅层130。硅基体层110的主要作用是为上面的两层提供机械支撑。掩埋氧化物层120通常称为BOX(Buried OXide)层，掩埋氧化物层120将活动的硅层与硅基体层分隔开来，因此，大面积的PN结被介电隔离，进一步的，绝缘体上硅层130的厚度远小于沟道耗尽区的宽度，减少了源漏耗尽区和沟道耗尽区间的共享电荷，能够效抑制短沟道效应。上述复合衬底可以根据现有或将有的SOI晶圆制造技术制成，包括但不限于Smart Cut等工艺。
随后在绝缘体上硅层130上外延生长硅锗层140，图2示出了外延生成了硅锗层140的结构示意图。相比于硅锗材质，硅材质具有更小的晶格常数，由于晶格失配，硅材料中，从下到上晶格被拉升，从而在硅中引入了双轴张应力。同时，硅锗层140为后续工艺提供了锗离子源。
在上述硅锗层140形成后，需要采用图形化的方式利用掩蔽层(通常为有图形的光刻胶)来定义半导体器件的NMOS管和PMOS管区域。上述图形化工艺可包含光致抗蚀剂涂布(例如旋转涂布)、软烤、光掩膜版对准、曝光、曝后烤、光致抗蚀剂显影、冲洗、干燥(例如硬烤)、其他合适的工艺，和/或前述的组合。
如图3所示，针对所定义的NMOS管区域，沉积硬掩膜层150覆盖在硅锗层140上。上述的沉积优选地采用利用接触蚀刻停止层(CESL，contact-etching stop-layer)技术的低压力化学气相沉积(LPCVD)，或，等离子体增强化学气相沉积(PECVD)来形成硬掩膜层150。通常的，硬掩膜层150的材质包括但不限于氮化硅(SiN)。借由上述工艺，能够沉积高应力水平的硬掩膜层150。对应NMOS管区域沉积的硬掩膜层150能够在后续的工艺中保护NMOS管区域的绝缘体上硅层，同时，高应力水平的硬掩膜层150能够在后续工艺中对NMOS管区域的绝缘体上硅层产生拉应力作用。
如图4所示，对整片晶圆便面进行氧化处理形成表面氧化物层160覆盖在硅锗层140和硬掩膜层150上。优选地，采用快速加热工艺，利用氧化剂与硅原子反应生成氧化硅薄膜。本实施例中的表面氧化物层160能够防止硅锗层140中的锗原子向外扩散。
随后进行高温退火处理，图5示出了根据高温退火处理后的结构示意图，其中原本复合衬底中的绝缘体上硅层130对应NMOS管区域的部分转化为拉应力绝缘体上硅层131，对应PMOS管区域的部分被转化为绝缘体上硅锗层132。
更具体地，在上述实施例中，高温退火处理优选采用的温度范围为800－1300℃，时间为0.5－3小时。上述高温退火处理包含高温氧化过程(high temperature oxidationprocess)，亦称为缩合反应(condensation process)。在上述高温过程中，表面氧化物层160能够起到氧化硅锗层140中的硅原子形成二氧化硅SiO2的作用，同时，由于形成了二氧化硅，硅锗层140中锗原子被挤压进绝缘体上硅层，从而对应PMOS区域的绝缘体上硅层转化为绝缘体上硅锗层132。并且，由于锗原子被挤压进入绝缘体上硅层，在此过程中产生了压应力，能够有效改善PMOS管的空穴迁移率。将PMOS管区域的硅锗/硅复合层被缩合转化为单层硅锗层。
如上所述，对应NMOS管区域，由于沉积了硬掩膜层150，在高温过程中，硬掩膜层150使得对应NMOS管区域的硅锗层140中的硅原子没有被氧化，从而，对应NMOS管区域，绝缘体上硅层没有被锗原子挤入。亦是由于沉积了高应力水平的硬掩膜层150，在高温退火处理中，高应力水平的硬掩膜层150对NMOS管区域的绝缘体上硅层产生拉应力，使其转化为拉应力绝缘体上硅层131。
经由上述高温退火处理，使得PMOS管区域形成有绝缘体上硅锗层132，且绝缘体上硅锗层132具有压应力，提高了PMOS管的空穴迁移率。同时具有拉应力的NMOS管区域的拉应力绝缘体上硅层131提高了NMOS管的电子迁移率，有效提高了NMOS管的驱动电流。因而，能够借由简单的步骤提高器件的性能与功函数。
后续的晶体管栅极以及栅极与衬底间的薄栅将形成在绝缘体上硅层上，因而。在形成具有拉应力绝缘体上硅层131和绝缘体上硅锗层132后，还需要除去为生成拉应力绝缘体上硅层131和绝缘体上硅锗层132而形成的多余的硅锗层、硬掩膜层和表面氧化物层。
图6-8示出了除去了上述多余各层的步骤。在去除多余各层时，优选的，采用湿法蚀刻除去上述多余的各层。具体的，针对各层材质的不同，优选不同的去除液以减低对其他各膜层的损害。在本实例中，采用稀氢氟酸去除表面氧化物层160；采用磷酸去除硬掩膜层150；以及采用硝酸、氢氟酸、乙酸和水的混合溶液去除硅锗层140。更具体的，在上述实施例中，所采用的混合溶液中所采用的硝酸浓度为70％，所采用的氢氟酸的浓度为49％，所采用的乙酸的浓度为99.9％以及硝酸、氢氟酸、乙酸和水的配比为40：1：2：57。
在另一实施例中，本发明所提供的方法还包括形成STI浅沟槽隔离以形成PMOS管和NMOS管的有源区。图9示出了在拉应力绝缘体上硅层231和绝缘体上硅锗层232的邻接部分形成STI浅沟槽隔离270的结构示意图。如图9所示，浅沟槽隔离270形成在拉应力绝缘体上硅层231和绝缘体上硅锗层232的邻接部分，且上述拉应力绝缘体上硅层231、绝缘体上硅锗层232和STI浅沟槽隔离270形成在硅基体层210和掩埋氧化物层220上。
上述实施例中的浅沟槽隔离工艺包括但不限于浅沟槽刻蚀、氧化物填充和氧化物平坦化。其中浅沟槽刻蚀包括但不限于隔离氧化层、氮化物沉淀、采用掩膜版进行浅槽隔离以及进行STI浅槽刻蚀。其中STI氧化物填充包括但不限于沟槽衬垫氧化硅、沟槽CVD(化学气相沉积)氧化物填充或PVD(物理气相沉积)氧化物填充。其中硅片表面的平坦化可以通过多种方法实现。可以通过使用SOG(spin-on-glass)填充间隙实现硅片的平坦化，SOG可以由80％的溶剂与20％的二氧化硅构成，淀积之后烘焙SOG，蒸发掉溶剂，将二氧化硅留在间隙当中，也可以进行全部表面的反刻，以减少整个硅片的厚度。亦可以通过CMP工艺(也称为抛光工艺)有效地进行平坦化处理，包括但不限于对沟槽氧化物进行抛光(可以采用化学机械抛光)以及氮化物去除。
由于本发明所提供的方法形成STI浅沟槽隔离270的步骤在形成拉应力绝缘体上硅层231和绝缘体上硅锗层232步骤后，因而，所形成的STI浅沟槽隔离270与绝缘体上硅锗层232的边界不存在小界面。如图9中对应STI浅沟槽隔离270与绝缘体上硅锗层232边缘的放大图所示，本发明所提供的绝缘体上硅锗层232结构均匀且致密。
图10示出了现有技术中先形成STI浅沟槽隔离的技术中绝缘体上硅层330与STI浅槽隔离370边界处存在的缺陷。如图10所示，STI浅沟槽隔离370形成在绝缘体上硅层330中，且上述绝缘体上硅层330和STI浅沟槽隔离370形成在硅基体层310和掩埋氧化物层320上。
在STI浅槽隔离370形成后进行硅锗外延生长工艺，这种方法获得的硅锗薄膜结构不均匀，由于硅与二氧化硅的热膨胀系数不一样，在STI浅槽隔离370形成后进行的热工艺会造成STI浅槽隔离370边缘处的硅要比STI浅槽隔离370内部的二氧化硅的收缩快，因而容易在靠近STI浅槽隔离370区形成小界面380，造成器件实际功函数的变化进而影响到器件的性能。同时，在降温过程中，收缩较快的二氧化硅会对周边有源区的硅产生应力作用，该应力传导至沟道内会造成PMOS内部空穴迁移率下降，从而影响器件的性能。
经由本发明所提供的方法，能够借助简单的工艺步骤同时实现提升FDSOI器件PMOS和NMOS管的性能，由于工业可操作性，且制造的产品性能可靠。
本发明还提供了经由上述本发明所提供的制造方法所制造的具有双极应力的绝缘体上硅结构，绝缘体上硅结构形成在掩埋氧化物层上，掩埋氧化物层形成在硅基体层上，绝缘体上硅结构、掩埋氧化物层和硅基体层构成晶体管器件的复合衬底；其中，绝缘体上硅结构对应P型MOS管区域为绝缘体上硅锗结构，对应N型MOS管区域为拉应力绝缘体上硅结构。其中绝缘体上硅锗结构具有压应力，拉应力绝缘体上硅结构具有拉应力。本发明所提供的绝缘体上硅结构还可以包括STI浅沟槽隔离结构，STI浅沟槽隔离结构位于绝缘体上硅锗结构和拉应力绝缘体上硅结构的邻接部分，其中，绝缘体上硅锗结构和拉应力绝缘体上硅结构邻接STI浅沟槽隔离结构的邻接部分结构均匀。
本发明所提供的绝缘体上硅结构中对应PMOS区域的硅锗薄膜层均匀且保留有退火工程中残留的压应力，提高了PMOS的空穴迁移率。同时，对应NMOS区域的绝缘体上硅结构具有拉应力，进一步提高了NMOS的电子迁移率。有效提高了器件的功函数与性能。
本发明还提供了一种包含上述绝缘体上硅结构的晶体管。如上所述，本发明所提供的N型MOS晶体管的电子迁移率提高，所提供的P型MOS晶体管的空穴迁移率提高，有效改善了器件的功函数与性能。
因此，已经描述了用于制作双极应力的绝缘体上硅结构的制造方法和具有双极应力的绝缘体上硅结构的实施例。尽管已经关于特定的示例性实施例描述了本公开，但将明显的是，可以对这些实施例做出各种修改和改变而不偏离本公开的更广泛的精神和范围。因此，本说明书和附图应被视为是说明性的含义而不是限制性的含义。
应当理解的是，本说明书将不用于解释或限制权利要求的范围或意义。此外，在前面的详细描述中，可以看到的是，各种特征被在单个实施例中组合在一起以用于精简本公开的目的。本公开的此方法不应被解释为反映所要求保护的实施例要求比在每个权利要求中明确列举的特征更多的特征的目的。相反，如所附权利要求所反映的，创造性主题在于少于单个所公开的实施例的所有特征。因此，所附权利要求据此并入详细描述中，其中每个权利要求独立地作为单独的实施例。
在该描述中提及的一个实施例或实施例意在结合该实施例描述的特定的特征、结构或特性被包括在方法的至少一个实施例中。在说明书中各处出现的短语一个实施例不一定全部指的是同一实施例。

Claims (10)

1.一种具有双极应力的绝缘体上硅结构的制造方法，包括：
提供复合衬底，所述复合衬底由下至上依次具有硅基体层、掩埋氧化物层和绝缘体上硅层；
在所述绝缘体上硅层上表面外延生长硅锗层；
沉积硬掩膜层以覆盖所述硅锗层对应N型MOS管区域的部分；
沉积表面氧化物层以覆盖所述硅锗层和所述硬掩膜层；
进行高温退火处理，以使所述绝缘体上硅层对应P型MOS管区域的部分转化为绝缘体上硅锗层，对应所述N型MOS管区域的部分转化为拉应力绝缘体上硅层；以及
去除所述绝缘体上硅锗层和所述拉应力绝缘体上硅层表面多余的所述硅锗层、所述硬掩膜层和所述表面氧化物层。
2.如权利要求1所述的制造方法，其特征在于，所述高温退火处理的温度范围为800－1300℃，时间为0.5－3小时。
3.如权利要求1所述的制造方法，其特征在于，所述沉积硬掩膜层的步骤进一步包括，采用接触蚀刻停止层工艺通过低压力化学气相沉积，或，等离子体增强化学气相沉积所述硬掩膜层。
4.如权利要求1所述的制造方法，其特征在于，所述去除步骤进一步包括，采用湿法去除多余的所述硅锗层、所述硬掩膜层和所述表面氧化物层，其中，
采用稀氢氟酸去除所述表面氧化物层；
采用磷酸去除所述硬掩膜层；以及
采用硝酸、氢氟酸、乙酸和水的混合溶液去除所述硅锗层。
5.如权利要求4所述的制造方法，其特征在于，所述混合溶液进一步包括：
所述硝酸的浓度为70％；
所述氢氟酸的浓度为49％；
所述乙酸的浓度为99.9％；以及
所述硝酸、氢氟酸、乙酸和水的配比为40：1：2：57。
6.如权利要求1所述的制造方法，其特征在于，所述方法还包括：
在所述绝缘体上硅锗层和所述拉应力绝缘体上硅层邻接部分形成STI浅沟槽隔离。
7.一种具有双极应力的绝缘体上硅结构，所述绝缘体上硅结构形成在掩埋氧化物层上，所述掩埋氧化物层形成在硅基体层上，所述绝缘体上硅结构、所述掩埋氧化物层和所述硅基体层构成晶体管器件的复合衬底；其中，
所述绝缘体上硅结构对应P型MOS管区域为绝缘体上硅锗结构，所述绝缘体上硅锗结构具有压应力，对应N型MOS管区域为拉应力绝缘体上硅结构。
8.如权利要求7所述的绝缘体上硅结构，其特征在于，所述绝缘体上硅结构还包括STI浅沟槽隔离结构，所述STI浅沟槽隔离结构位于所述绝缘体上硅锗结构和所述拉应力绝缘体上硅结构的邻接部分，其中，
所述绝缘体上硅锗结构和所述拉应力绝缘体上硅结构邻接所述STI浅沟槽隔离结构的邻接部分结构均匀。
9.一种具有双极应力的绝缘体上硅结构，其特征在于，采用如权利要求1－6中任一项所述的制造方法制造所述绝缘体上硅结构。
10.一种晶体管，其特征在于，所述晶体管包含如权利要求7－9中任一项所述具有双极应力的绝缘体上硅结构。
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