CN108493233A - 可降低导通电阻提高运行可靠性的GaN HEMT器件 - Google Patents

可降低导通电阻提高运行可靠性的GaN HEMT器件 Download PDF

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CN108493233A
CN108493233A CN201810433273.3A CN201810433273A CN108493233A CN 108493233 A CN108493233 A CN 108493233A CN 201810433273 A CN201810433273 A CN 201810433273A CN 108493233 A CN108493233 A CN 108493233A
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passivation layer
electrode
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任永硕
王荣华
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Dalian Core Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode

Abstract

本发明公开一种可降低导通电阻提高运行可靠性的GaN HEMT器件,与现有技术不同的是InxAlyGa1‑x‑yN势垒层由矩阵排列的多个环组成,环的外侧是覆盖于沟道层上的源电极,环的内侧是覆盖于沟道层上的漏电极,在InxAlyGa1‑x‑yN势垒层、源电极及漏电极上有第一介质钝化层,所述栅电极是位于第一介质钝化层上且置于源电极及漏电极之间的环形,栅电极的下部穿过第一介质钝化层至InxAlyGa1‑x‑yN势垒层表面,在所述第一介质钝化层及栅电极的上表面覆有第二介质钝化层,在所述漏电极上有穿过第一介质钝化层及第二介质钝化层的通孔,在通孔内及第二介质钝化层上有扩展电极。

Description

可降低导通电阻提高运行可靠性的GaN HEMT器件
技术领域
本发明涉及一种GaN HEMT器件,尤其是一种可降低导通电阻提高运行可靠性的GaN HEMT器件。
背景技术
作为继第一代半导体硅(Si)和第二代半导体砷化镓(GaAs)之后的第三代半导体材料代表—氮化镓(GaN)具有独特的材料特性:宽禁带、耐高温、高电子浓度、高电子迁移率、高导热性等,GaN基高电子迁移率晶体管(HEMT)已广泛应用于微波通讯和电力电子转换等领域。GaN HEMT器件的导通电阻是影响器件性能的关键指标,如GaN HEMT器件的导通电阻大,在射频器件中体现为输出功率密度降低,在电力电子器件中体现为导通损耗增加从而影响电源转换效率,同时导通电阻大会导致器件发热量大,增加散热成本甚至影响器件可靠性,为此人们均致力于降低器件导通电阻。
GaN HEMT器件由下至上依次为衬底(硅、蓝宝石、碳化硅等)、AlxGa1-xN缓冲层、GaN或In GaN沟道层,在沟道层上有InxAlyGa1-x-yN势垒层(可有GaN或SiN帽层覆盖其上)、源电极及漏电极,在InxAlyGa1-x-yN势垒层上有介质钝化层,在介质钝化层上置有栅电极(栅本身和可能存在的栅电极场板),栅电极的下部穿过介质钝化层置于InxAlyGa1-x-yN势垒层上。由于三族氮化物InxAlyGa1-x-yN材料体系具有很强的极化效应,其极化系数随着Al组分的升高而增大,InxAlyGa1-x-yN/GaN界面沟道中的二维电子气(2DEG)浓度亦随极化强度的升高而增大,当外延结构固定时,2DEG的浓度直接影响了GaN HEMT器件的外延导通电阻。现有GaNHEMT器件源电极及漏电极采用“两梳子对插”式的结构,以最大限度延长栅长,但是受器件尺寸及耐压等条件限制,单位面积栅长已经趋于极限,无法进一步降低外延导通电阻。由于栅长度的增加,厚度通常2~8um的源电极和漏电极长度则超过100mm,显然增加了金属电极导通电阻(至少接近GaN HEMT器件总电阻的20%)。另外,现有GaN HEMT器件的电极结构导致中直线位置与转角位置电场分布不一致,转角处易击穿;而且源电极和漏电极中各处的电流分布也不均匀,长条末端电阻显著增加,降低了器件运行的可靠性。
发明内容
本发明是为了解决现有技术所存在的上述技术问题,提供一种可降低导通电阻提高运行可靠性的GaN HEMT器件。
本发明的技术解决方案是:一种可降低导通电阻提高运行可靠性的GaN HEMT器件,由下至上依次为衬底、缓冲层、沟道层,在沟道层上有InxAlyGa1-x-yN势垒层、源电极、漏电极以及栅电极,所述InxAlyGa1-x-yN势垒层由矩阵排列的多个环组成,环的外侧是覆盖于沟道层上的源电极,环的内侧是覆盖于沟道层上的漏电极,在InxAlyGa1-x-yN势垒层、源电极及漏电极上有第一介质钝化层,所述栅电极是位于第一介质钝化层上且置于源电极及漏电极之间的环形,栅电极的下部穿过第一介质钝化层至InxAlyGa1-x-yN势垒层表面,在所述第一介质钝化层及栅电极的上表面覆有第二介质钝化层,在所述漏电极上有穿过第一介质钝化层及第二介质钝化层的通孔,在通孔内及第二介质钝化层上有扩展电极。
本发明的另一种解决方案是将源电极及漏电极位置互换。
本发明通过整面孔洞状电极分布,增加单位面积内栅的长度,降低外延电阻,同时增加了源电极与漏电极金属面积,改善金属布局,降低金属导通电阻。相比现有技术,本发明的可降低外延电阻约30%,降低金属导通电阻约65%,从而实现器件总的导通电阻降低约37%。另外本发明保证各位置电场均一致,不存在电场分布的薄弱点,避免因电场分布不均而导致的击穿现象,且各个位置电流分布更加均匀,热量分布更合理,提升了器件运行可靠性。
附图说明
图1是本发明实施例1的结构示意图。
图2是图1的A-A视图。
图3是本发明实施例2的结构示意图。
图4是本发明实施例3的结构示意图。
图5是本发明实施例1与现有技术相比导通电阻降低比例示意图。
具体实施方式
实施例1:
本发明的可降低导通电阻提高运行可靠性的GaN HEMT器件如图1、图2所示:与现有技术相同由下至上依次为衬底1、缓冲层2、GaN沟道层3,在沟道层3上有Al0.3Ga0.7N势垒层4、源电极5及漏电极6,与现有技术所不同的是所述Al0.3Ga0.7N势垒层4由矩阵排列的多个环组成,可以如图1所示为圆形环,亦可采用方形环等规则形状,环的外侧是覆盖于沟道层3上的源电极5,环的内侧是覆盖于沟道层3上的漏电极6,在Al0.3Ga0.7N势垒层4、源电极5及漏电极6上有第一介质钝化层21,所述栅电极7是位于第一介质钝化层21上且置于源电极5及漏电极6之间的环形,栅电极7的下部穿过第一介质钝化层21至Al0.3Ga0.7N势垒层4表面,在所述第一介质钝化层21及栅电极7的上表面覆有第二介质钝化层22,在所述漏电极6上有穿过第一介质钝化层21及第二介质钝化层22的通孔,在通孔内及第二介质钝化层22上有扩展电极23。
本发明实施例1的隔离区、衬底1、缓冲层2、沟道层3、Al0.3Ga0.7N势垒层4、源电极5、漏电极6及栅电极7的制备方法与现有技术相同,第一介质钝化层21与第二介质钝化层22的制备方法同现有技术的介质钝化层,即通过PECVD或ALD的方法生长SiN、Al2O3或其他高k介质层,漏电极扩展电极23的制备方法同现有技术漏电极的制备方法。
将本发明实施例1所得器件与现有器件GaN HEMT器件在相同器件面积内本发明实施例1的外延电阻、金属导通电阻及器件总的导通电阻均降低,降低比例如图5所示。由图5可以看出,本发明实施例1降低外延电阻约30%,降低金属导通电阻约65%,从而实现器件总的导通电阻降低约37%。
实施例2:
实施例2的基本结构同实施例1,与实施例1所不同的是漏电极扩展电极23如图3所示,是连接各漏电极6的条状结构。
制备方法同实施例1。
实施例3:
实施例3的基本结构同实施例1,但源电极5及漏电极6位置互换,具体结构如图4所示。即与现有技术所不同的是Al0.3Ga0.7N势垒层4由矩阵排列的多个环组成,环的外侧是覆盖于沟道层3上的漏电极6,环的内侧是覆盖于沟道层3上的源电极5,在Al0.3Ga0.7N势垒层4、源电极5及漏电极6上有第一介质钝化层21,所述栅电极7是位于第一介质钝化层21上且置于源电极5及漏电极6之间的环形,栅电极7的下部穿过第一介质钝化层21至Al0.3Ga0.7N势垒层4表面,在所述第一介质钝化层21及栅电极7的上表面覆有第二介质钝化层22,在所述源电极5上有穿过第一介质钝化层21及第二介质钝化层22的通孔,在通孔内及第二介质钝化层22上有扩展电极23。

Claims (1)

1.一种可降低导通电阻提高运行可靠性的GaN HEMT器件,由下至上依次为衬底(1)、缓冲层(2)、沟道层(3),在沟道层(3)上有InxAlyGa1-x-yN势垒层(4)、源电极(5)、漏电极(6)以及栅电极(7),其特征在于:所述InxAlyGa1-x-yN势垒层(4)由矩阵排列的多个环组成,环的外侧是覆盖于沟道层(3)上的源电极(5),环的内侧是覆盖于沟道层(3)上的漏电极(6),在InxAlyGa1-x-yN势垒层(4)、源电极(5)及漏电极(6)上有第一介质钝化层(21),所述栅电极(7)是位于第一介质钝化层(21)上且置于源电极(5)及漏电极(6)之间的环形,栅电极(7)的下部穿过第一介质钝化层(21)至InxAlyGa1-x-yN势垒层(4)表面,在所述第一介质钝化层(21)及栅电极(7)的上表面覆有第二介质钝化层(22),在所述漏电极(6)上有穿过第一介质钝化层(21)及第二介质钝化层(22)的通孔,在通孔内及第二介质钝化层(22)上有扩展电极(23)。
CN201810433273.3A 2018-05-08 2018-05-08 可降低导通电阻提高运行可靠性的GaN HEMT器件 Pending CN108493233A (zh)

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