CN108469866A - Superhigh precision low-cost high-order compensation band gap reference circuit - Google Patents
Superhigh precision low-cost high-order compensation band gap reference circuit Download PDFInfo
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- CN108469866A CN108469866A CN201810451456.8A CN201810451456A CN108469866A CN 108469866 A CN108469866 A CN 108469866A CN 201810451456 A CN201810451456 A CN 201810451456A CN 108469866 A CN108469866 A CN 108469866A
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- pmos tube
- tube
- transistor
- breadth length
- length ratio
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
Superhigh precision low-cost high-order compensation band gap reference circuit, is related to integrated circuit.The present invention includes：The source electrode of concatenated first PMOS tube and the 6th NMOS tube, concatenated second PMOS tube and the 7th NMOS tube, the 7th NMOS tube connects the input terminal of transistor group, output end and the control terminal ground connection of transistor group；First PMOS tube, the second PMOS tube, the breadth length ratio of third PMOS tube are identical, are a unit breadth length ratio；6th NMOS tube is identical with the breadth length ratio of the 7th NMOS tube；The breadth length ratio of 4th PMOS tube and the 5th PMOS tube is 2.375 times of unit breadth length ratios, the resistance value R of first resistor R11The resistance value R of=35424 Ω, second resistance R22=119260.8 Ω.The present invention can obtain high-precision bandgap voltage reference.
Description
Technical field
The present invention relates to integrated circuits, more particularly to need high-precision A/D, D/A conversion of high precision reference reference voltage
Device class circuit.
Background technology
Arbitrarily simulate signal level in its range can be converted to its corresponding unique number by high-precision a/d converter
Code word exports, and converts correspondence, is usually determined by reference voltage.
Arbitrary numeral input code word in its range can be converted to its corresponding unique simulation by high-precision d/a converter
Signal exports, and converts correspondence, is generally also determined by reference voltage.
From the foregoing, it will be observed that being directed to high-precision A/D, D/A class converter, the temperature characterisitic of reference voltage will will have a direct impact on conversion
The precision and performance of device circuit.
The generation principle of bandgap voltage reference is：By two amounts with opposite temperature coefficients, pass through weight phase appropriate
Add, the temperature coefficient or even zero-temperature coefficient of a very little will be obtained.
The forward conduction voltage of PN junction diode usually has negative temperature coefficient, such as the base-emitter electricity of transistor
Press (VBE), junction voltage VBEIt can be simply expressed as with the relationship of temperature：
VBE(T)=Vgo-B*T-C*f(T)
Wherein VgoFor the band gap voltage of silicon, B, C are temperature independent constants, and T indicates that temperature, f (T) are second order or more
High-order temperature funtion.
When two identical bipolar transistor operations are in different current densities, the junction voltage V of base-emitterBE
Difference △ VBE, in a linear relationship with temperature, expression formula is：
△VBE=VBE1-VBE2=(kT/q) * ln (n)
Wherein k, q are synthermal unrelated constant, and n is the electric current ratio of two transistors, and T indicates temperature.Typical △ VBE
Generation schematic diagram it is as shown in Figure 1：
The single order temperature compensation bandgap reference scheme of mainstream at present, is all made of △ VBETo VBESingle order temperature-compensating is carried out, by
In △ VBEOnly there is single order temperature coefficient, therefore pass through △ VBEBandgap voltage reference V after compensationREFTemperature coefficient usually will
More than 20ppm/ DEG C, which far can not meet A/D, D/A class converter application environment of superelevation conversion accuracy.Typical single order
It is as shown in Figure 2 that temperature compensation bandgap reference voltage generates schematic diagram：
To obtain the bandgap voltage reference of higher precision, the scheme of mainstream is at present, on the basis of single order temperature-compensating
Increase high-order temperature compensation circuit, the high-order temperature compensated of mainstream includes PTAT2The resistance ratio of voltage compensation, different temperature coefficients
The schemes such as compensation, piecewise linearity current compensation.It is as shown in Figure 3 that exemplary higher order temperature compensation bandgap reference voltage generates schematic diagram：
Using above-mentioned high-order temperature compensated scheme, the temperature coefficient that can effectively reduce bandgap voltage reference typically can
The temperature coefficient of band-gap reference to be reduced within 5ppm/ DEG C, but said program is required to add additional circuit to generate
High-order amount f (T), the cost to sacrifice larger chip area and circuit power consumption exchange high-precision temperature performance for.
Invention content
The technical problem to be solved by the invention is to provide a kind of high-order compensation band gap reference circuits, are hardly increasing
Under the premise of any chip area and circuit power consumption, the temperature coefficient of band-gap reference is improved.
The present invention solve the technical problem the technical solution adopted is that, superhigh precision low-cost high-order compensation band gap benchmark
Circuit, including：
Concatenated first PMOS tube and the 6th NMOS tube, the grid of the first PMOS tube and drain electrode connect, the 6th NMOS tube
Source electrode is grounded by first resistor R1 and the first transistor；
Concatenated second PMOS tube and the 7th NMOS tube, the drain and gate connection of the 7th NMOS tube,
The drain electrode of third PMOS tube is grounded by second resistance R2,
The drain electrode of 4th PMOS tube is grounded by third transistor, and the base stage of third transistor connects the drain electrode of third metal-oxide-semiconductor；
The drain electrode of 5th PMOS tube is grounded by the 4th transistor, and the base stage of the 4th transistor connects the drain electrode of the 4th metal-oxide-semiconductor；
First PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube and the 5th PMOS tube grid connect；
It is characterized in that, the source electrode of the 7th NMOS tube connects the input terminal of transistor group, the output end of transistor group and control
End ground connection；The transistor group is made of 8 PNP transistors, wherein the emitter of each transistor is connected to transistor group
Input terminal, the collector of each transistor are connected to the input terminal of transistor group, collector and base earth；
First PMOS tube, the second PMOS tube, the breadth length ratio of third PMOS tube are identical, are a unit breadth length ratio；
6th NMOS tube is identical with the breadth length ratio of the 7th NMOS tube；
The breadth length ratio of 4th PMOS tube and the 5th PMOS tube is 2.375 times of unit breadth length ratios,
The resistance value R of first resistor1=35424 Ω, the resistance value R of second resistance2=119260.8 Ω.
The invention has the advantages that under conditions of almost not increasing any additional circuit, by extracting △ VBEOr VBE
The high-order amount in circuit occurs, progress is high-order temperature compensated, to obtain high-precision bandgap voltage reference.
Description of the drawings
Fig. 1 is typical case △ VBEGeneration schematic diagram.
Fig. 2 is that typical single order temperature compensation bandgap reference voltage generates schematic diagram.
Fig. 3 is that exemplary higher order temperature compensation bandgap reference voltage generates principle.
Fig. 4 is a kind of single order temperature compensation bandgap reference circuit of classics.
Fig. 5 is low overhead high-order temperature compensation bandgap reference circuit figure in the present invention.
Fig. 6 is that circuit diagram only carries out fiducial temperature performance diagram when single order temperature-compensating in the present invention.
Fig. 7 is fiducial temperature performance diagram when circuit diagram carries out high-order temperature compensated in the present invention.
Specific implementation mode
Superhigh precision low-cost high-order compensation band gap reference circuit, including：
The grid of concatenated first PMOS tube M1 and the 6th NMOS tube M6, the first PMOS tube M1 and drain electrode connect, and the 6th
The source electrode of NMOS tube M6 passes through first resistor R1 and the first transistor Q1 ground connection；
The drain and gate of concatenated second PMOS tube M2 and the 7th NMOS tube M7, the 7th NMOS tube M7 connect,
The drain electrode of third PMOS tube M3 is grounded by second resistance R2,
The drain electrode of 4th PMOS tube M4 is grounded by third transistor Q3, and the base stage of third transistor Q3 connects third metal-oxide-semiconductor
The drain electrode of M3；
The drain electrode of 5th PMOS tube M5 connects the 4th metal-oxide-semiconductor by the 4th transistor Q4 ground connection, the base stage of the 4th transistor Q4
The drain electrode of M4；
The grid of first PMOS tube M1, the second PMOS tube M2, third PMOS tube M3, the 4th PMOS tube M4 and the 5th PMOS tube M5
Pole connects；
It is characterized in that, the source electrode of the 7th NMOS tube M7 connects the input terminal of transistor group, the output end of transistor group and control
End ground connection processed；The transistor group is made of 8 PNP transistors, wherein the emitter of each transistor is connected to transistor group
Input terminal, the collector of each transistor is connected to the input terminal of transistor group, collector and base earth；
First PMOS tube M1, the second PMOS tube M2, the breadth length ratio of third PMOS tube M3 are identical, are the wide length of unit
Than；
The breadth length ratio of 6th NMOS tube M6 and the 7th NMOS tube M7 is identical；
The breadth length ratio of 4th PMOS tube M4 and the 5th PMOS tube M5 is 2.375 times of unit breadth length ratios, first resistor R1's
Resistance value R1The resistance value R of=35424 Ω, second resistance R22=119260.8 Ω.
Further, referring to Fig. 1-7.The present invention is in the structure of Fig. 2, and direct sampling goes out high-order amount f (T), then using figure
Schematic diagram shown in 3 generates high-precision bandgap voltage reference.High-order amount f (T) is by the △ V in Fig. 2BEOr VBEIt is direct that circuit occurs
It generates.Circuit diagram shown in Fig. 3 does not almost increase any additional circuit on the basis of Fig. 2.
After the schematic diagram of Fig. 2 is realized using specific circuit structure, single order temperature compensation bandgap reference circuit such as Fig. 4 institutes
Show.
In Fig. 4, the function of clamp circuit is to ensure Vx=Vy, the breadth length ratio of metal-oxide-semiconductor M1, M2, M3 is disposed as 1* (W/L),
The breadth length ratio of M4 and M5 is disposed as m* (W/L), and it is 8 that the number of transistor Q1, Q3, Q4, which are the number of 1, Q2,.By simulation electricity
Roadbed present principles are it is found that IM1=IM2=IM3, IM4=IM5=m*IM1, VBE3=VBE4=VBE。
From the foregoing, it will be observed that IM2=IPTAT=(VBE1-VBE2)/R1=(kT/q) * ln (8)/R1, final bandgap voltage reference VREF
For：
VREF=IM3*R2+VBE3+VBE4=(kT/q) * ln (8) * R2/R1+2*VBE=A*T+2*VBE；
Wherein A=(k/q) * ln (8) * (R2/R1), pass through rational proportion R1And R2Resistance value, V can be completely counterbalanced byBEIn one
Rank temperature coefficient, to obtain classical first compensation phase bandgap voltage reference VREF。
High order compensation circuit in the present invention does not increase on circuit structure shown in Fig. 4 any device, only rationally matches
The parameter of related device is set, high-order compensation band gap reference voltage is obtained, concrete principle is as follows；
It is in certain functional relation that the currentamplificationfactorβ of bipolar transistor, which has with absolute temperature, and feature is such as
Shown in lower：
β=fβ(T)；
If the emitter current for flowing through bipolar transistor is first-order linear electric current (Ie=A*T), then bipolar transistor at this time
Base current Ib=Ie/ β=A*T/fβ(T), by 1/fβ(T) it can be obtained with Taylor expansion：1/fβ(T)=a+b*T+c*T2
+···+n*TnIf only considering the temperature coefficient of first three rank, Ib=A* (a*T+b*T2+c*T3)。
Wherein A, a, b, c are synthermal unrelated constant term, and T is temperature term.Therefore IbPractical is high-order temperature coefficient
The magnitude of current, if in conjunction with Fig. 3 and Fig. 4 it is found that by IbIt is defined as high-order amount f (T), resistance R2By IbGenerated voltage gain definition
For amplification coefficient K2, then high-order compensation schematic diagram shown in Fig. 3 can be realized completely by Fig. 4.
The high order compensation circuit structure chart of the present invention is as shown in figure 4, wherein Ib(Q3)Temperature coefficient it is as follows：
Ib(Q3)=m*A* (a*T+b*T2+c*T3)；
The high-order compensation band gap reference voltage V that final Fig. 4 is obtainedREFAs follows：
VREF=(IM3+Ib(Q3))*R2+VBE3+VBE4=IM3*R2+2*VBE+Ib(Q3)*R2
=(kT/q) * ln (8) * R2/R1+2*VBE+Ib(Q3)*R2；
In Fig. 4, when the breadth length ratio of metal-oxide-semiconductor M1, M2, M3 are fixed as 1* (W/L), the number of transistor Q1, Q3, Q4 are fixed as
1, Q2 number is fixed as 8, only needs reasonable disposition R at this time1、R2Resistance value and m value, V can be completely counterbalanced byBEIn voltage
Single order and second-order temperature coefficient (the even more temperature coefficient of high-order).
Whether V in classical single order temperature compensation structureBEOr △ VBEGeneration circuit only sampled bipolar transistor
Pn-junction voltage, and the base current of any transistor is not used, thus the present invention using the not used base current of sampling come
The high-order compensation for carrying out band-gap reference, it is complete under the premise of reaching and almost not increasing any additional devices and chip area
At the high-order compensation of band-gap reference.
Simulating, verifying
The schematic diagram of Fig. 4 is subjected to simulation analysis, artificial circuit figure is as shown in figure 5, wherein Q1~Q4 is positive-negative-positive crystal
Pipe, M1~M5 are PMOS tube, and M6, M7 are NMOS tube, and R1, R2 are resistance.
In Fig. 5, if the breadth length ratio of PMOS tube M1, M2, M3 are fixed as 1* (W/L), in clamp circuit, NMOS tube M5's and M6
Breadth length ratio is fixed as (W/L)N, the number that the number of transistor Q1, Q3, Q4 is fixed as 1, Q2 is fixed as 8.Resistance is set at this time
R1, R2 and m are variable.
PMOS current mirrors and NMOS current mirrors constitute the clamp circuit of mutual negative feedback structure, it can be ensured that Vx=Vy, therefore I1=
(VBE2-VBE1)/R1, therefore I1~I5It is PTAT current, and I1=I2=I3, I4=I5=m*I1.In the artificial circuit, I1
Current value only by R1It determines.
If R is arbitrarily arranged1Resistance value, most situations, IbSecond-order temperature item V can not be fully compensatedBETwo
Rank temperature term, therefore adjust R2Resistance value, be only capable of the voltage V to reference outputREFSingle order temperature-compensating is carried out.
In Fig. 5, work as R1=308640 Ω, R2When=1129249.9 Ω, m=2.375, VREFEnd can obtain base after first compensation phase
Quasi- voltage, simulation result as shown in fig. 6, it will be appreciated from fig. 6 that only carry out the reference voltage of single order temperature-compensating warm temperature drift entirely at this time
About：
9.57mV/ (180 DEG C of * 2.539V)=20.9ppm/ DEG C
As reasonable setting R1、R2When resistance value and m coefficients, make IbSecond-order temperature item V is just fully compensatedBESecond order temperature
Item is spent, at this point, by adjusting R2Resistance value, make I3In R2On voltage gain be fully compensated VREFSingle order temperature coefficient,
Thus to the voltage V of reference outputREFSingle order and second-order temperature compensation (even more high-order) are carried out.
In Fig. 5, work as R1=35424 Ω, R2When=119260.8 Ω, m=2.375, VREFEnd can obtain benchmark after high-order compensation
Voltage, simulation result is as shown in fig. 7, as shown in Figure 7, carried out single order and the base of second-order temperature compensation (even more high-order)
Warm temperature drift is about quasi- voltage entirely：
(258.45uV/ 180 DEG C of * 2.523V)=0.57ppm/ DEG C
By Fig. 5, Fig. 6, Fig. 7 it is found that through the invention, almost can not increase on the basis of classical first compensation phase circuit
Under the premise of adding any device and power consumption, only by the way that relevant device parameters are rationally arranged, you can realization is high-order temperature compensated, finally
Simulating, verifying 2.5V band-gap references full temperature temperature drift within the scope of -55 DEG C to 180 DEG C is less than 1ppm/ DEG C, to realize low-cost, surpasses
The design of High-precision band-gap reference circuit.
Claims (1)
1. superhigh precision low-cost high-order compensation band gap reference circuit, including：
Concatenated first PMOS tube and the 6th NMOS tube, the grid of the first PMOS tube and drain electrode connect, the source electrode of the 6th NMOS tube
It is grounded by first resistor and the first transistor；
Concatenated second PMOS tube and the 7th NMOS tube, the drain and gate connection of the 7th NMOS tube,
The drain electrode of third PMOS tube is grounded by second resistance,
The drain electrode of 4th PMOS tube is grounded by third transistor, and the base stage of third transistor connects the drain electrode of third metal-oxide-semiconductor；
The drain electrode of 5th PMOS tube is grounded by the 4th transistor, and the base stage of the 4th transistor connects the drain electrode of the 4th metal-oxide-semiconductor；
First PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube and the 5th PMOS tube grid connect；
It is characterized in that, the source electrode of the 7th NMOS tube connects the input terminal of transistor group, the output end of transistor group and control terminate
Ground；The transistor group is made of 8 PNP transistors, wherein the emitter of each transistor is connected to the input of transistor group
End, the collector of each transistor are connected to the input terminal of transistor group, collector and base earth；
First PMOS tube, the second PMOS tube, the breadth length ratio of third PMOS tube are identical, are a unit breadth length ratio；
6th NMOS tube is identical with the breadth length ratio of the 7th NMOS tube；
The breadth length ratio of 4th PMOS tube and the 5th PMOS tube is 2.375 times of unit breadth length ratios, the resistance value R of first resistor R11=
The resistance value R of 35424 Ω, second resistance R22=119260.8 Ω.
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| CN201810451456.8A CN108469866A (en) | 2018-05-11 | 2018-05-11 | Superhigh precision low-cost high-order compensation band gap reference circuit |
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| CN201810451456.8A CN108469866A (en) | 2018-05-11 | 2018-05-11 | Superhigh precision low-cost high-order compensation band gap reference circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201097251Y (en) * | 2007-09-29 | 2008-08-06 | 比亚迪股份有限公司 | Standard voltage generation circuit with gap |
| CN102854913A (en) * | 2011-06-28 | 2013-01-02 | 比亚迪股份有限公司 | Band-gap reference voltage source circuit |
| CN103076830A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Bandgap reference circuit |
| CN104035470A (en) * | 2014-06-19 | 2014-09-10 | 电子科技大学 | Low-temperature-offset-coefficient bandgap reference voltage generation circuit |
| US20170221531A1 (en) * | 2016-01-28 | 2017-08-03 | Lapis Semiconductor Co., Ltd. | Reference current generating circuit and memory device |
-
2018
- 2018-05-11 CN CN201810451456.8A patent/CN108469866A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201097251Y (en) * | 2007-09-29 | 2008-08-06 | 比亚迪股份有限公司 | Standard voltage generation circuit with gap |
| CN102854913A (en) * | 2011-06-28 | 2013-01-02 | 比亚迪股份有限公司 | Band-gap reference voltage source circuit |
| CN103076830A (en) * | 2012-12-20 | 2013-05-01 | 上海宏力半导体制造有限公司 | Bandgap reference circuit |
| CN104035470A (en) * | 2014-06-19 | 2014-09-10 | 电子科技大学 | Low-temperature-offset-coefficient bandgap reference voltage generation circuit |
| US20170221531A1 (en) * | 2016-01-28 | 2017-08-03 | Lapis Semiconductor Co., Ltd. | Reference current generating circuit and memory device |
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Application publication date: 20180831 |