CN108449082A - A kind of CML level turns the circuit structure of CMOS level - Google Patents
A kind of CML level turns the circuit structure of CMOS level Download PDFInfo
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- CN108449082A CN108449082A CN201810529641.4A CN201810529641A CN108449082A CN 108449082 A CN108449082 A CN 108449082A CN 201810529641 A CN201810529641 A CN 201810529641A CN 108449082 A CN108449082 A CN 108449082A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Abstract
The invention discloses a kind of current mode logic (CML) level to turn CMOS level circuit structures, including：CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while carrying out level-one amplification to CML signal swings；Direct current uncoupling amplifying circuit B, the dc point for removing Differential CML signals, while two level amplification is carried out to the Differential CML signals；And duty ratio circuit for rectifying C, for during high speed CML level carries out CMOS level conversions, duty ratio being avoided to lack of proper care.Circuit structure using the present invention, can efficiently solve in High-speed IC's Chip realize CML level to the conversion of CMOS level purpose.
Description
Technical field
The present invention relates to circuit and signal processing technologies more particularly to a kind of current mode logic (CML) level to turn CMOS
The circuit structure of level.
Background technology
In digital circuit chip, the universal transmission process of signal is all CMOS level, and so-called CMOS level refers to just
" 1 " logic-level voltages are close to supply voltage, and " 0 " logic level is close to 0V.And there is very wide noise margin.It is this
CMOS level is digital circuit the inside level standard the most general, as illustrated in figs. 1A and ib.
And with the development of High-speed IC's Chip technology, in the clock tree circuit of high speed and in high-speed interface circuit
In, the circuit form of traditional cmos level standard increasingly cannot be satisfied the characteristic of high speed transmission of signals, therefore one kind occurs
New signal level transmission mode, i.e. current mode logic (CurrentModel Logic, CML) transmission form, this CML electricity
Flat outputting and inputting has matched, due to reducing peripheral components, more suitable in higher band operation.CML
The characteristics of level, is as shown in Fig. 2, be typically to be made of differential signal, it is defeated to be converted into two difference by two differential input signals
Go out signal, the characteristics of this differential signal is that signal occurs in pairs, is occurred by the Difference signal pair of " just " and negation, this signal
It is that signal swing is smaller first, usually minimum to reach tens millivolts, the supply voltage amplitude of fluctuation of far smaller than CMOS,
Therefore CML level can be referred to as the differential small-signal amplitude of oscillation again, and CMOS level can be referred to as single-ended big signal swing.
Invention content
In view of this, the main purpose of the present invention is to provide a kind of current mode logic (CML) level to turn CMOS level
Circuit structure, to solve to realize conversion of the CML level to CMOS level in High-speed IC's Chip.
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
A kind of current mode logic (CML) level turns CMOS level circuit structures, including：
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while believing CML
Number amplitude of oscillation carries out level-one amplification；
Direct current uncoupling amplifying circuit B, the dc point for removing Differential CML signals, while to the difference CML
Signal carries out two level amplification；And
Duty ratio circuit for rectifying C, for during high speed CML level carries out CMOS level conversions, avoiding duty ratio
Imbalance.
Wherein：The CML level equalizations amplifying circuit A, physical circuit include：Resistance R1, resistance R2, transistor M1, crystalline substance
Body pipe M2, current source Ki1 and current source Ki2 and capacitance C1；The resistance R1 and resistance R2 are all connected with operating voltage VDD；It is described
The grid G of transistor M1 and transistor M2 respectively with VAAnd VBIt is connected；The other end of the drain D and resistance R1 of the transistor M1
It is connected, the drain D of the transistor M2 is connected with the other end of resistance R2；The source S of the transistor M1 and transistor M2's
Source S is connected separately with current source Ki1 and current source Ki2.The other end of the current source Ki1 and current source Ki2 is grounded respectively.
It is connected by capacitance C1 between the transistor M1 and the source S of transistor M2.
The direct current uncoupling amplifying circuit B, physical circuit include：The capacitance being sequentially connected in series with the drain D of transistor M1
C3, phase inverter N2；Capacitance C2, the phase inverter N1 being sequentially connected in series with the drain D with transistor M2；And the phase inverter N2 and anti-
The both ends phase device N1 are parallel with resistance R4 and resistance R3 respectively.
The duty ratio circuit for rectifying C, physical circuit include：The phase inverter being connected with the output end of the phase inverter N2
N6；The phase inverter N5 being connected with the output end of the phase inverter N1；And it is connected in parallel on the input of phase inverter N5 and phase inverter N6
Phase inverter N3 before end and phase inverter N4；The phase inverter N3 being arranged in parallel and phase inverter N4 is oppositely arranged.
The output end of the phase inverter N5 and phase inverter N6 of the duty ratio circuit for rectifying C turn CMOS respectively as CML level
The signal output end of the circuit of level.
Current mode logic (CML) level of the present invention turns CMOS level circuit structures, has the advantages that：
The circuit structure of the present invention, by using CML level equalization amplifying circuits A, direct current uncoupling amplifying circuit B and accounts for
Sky solves the duty ratio that traditional high speed CML level can encounter during carrying out CMOS level conversions than circuit for rectifying C
Imbalance.By using duty ratio circuit for rectifying C, effectively duty ratio can be avoided to lack of proper care so that CMOS level has fine
Duty ratio characteristics.Especially, the signal of two-way inverted phases, Ke Yigen can also be exported using duty ratio circuit for rectifying C
It is used according to demand, can both only use single-phase, the cmos signal of differential phase can also be used, to adapt to the need of different circuits
It asks.
Description of the drawings
Fig. 1 a and Fig. 1 b are existing CMOS level circuits structural schematic diagram；
Fig. 2 is existing current mode logic (CML) electrical block diagram；
Fig. 3 is the electrical block diagram that CML level of the embodiment of the present invention turns CMOS level.
Specific implementation mode
Below in conjunction with the accompanying drawings and the embodiment of the present invention the present invention is described in further detail.
Fig. 3 is the electrical block diagram that CML level of the embodiment of the present invention turns CMOS level.
As shown in figure 3, the CML level turns the circuit of CMOS level, include mainly：It is CML level equalization amplifying circuits A, straight
Flow away amplifier circuit B and duty ratio circuit for rectifying C.Wherein：
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while believing CML
Number amplitude of oscillation carries out level-one amplification.
In the present embodiment, the CML level equalizations amplifying circuit A includes mainly：Resistance R1, resistance R2, transistor
M1, transistor M2, current source Ki1 and current source Ki2 and capacitance C1.
Its particular circuit configurations is：The resistance R1 and resistance R2 are all connected with operating voltage VDD.The transistor M1 and crystalline substance
The grid G of body pipe M2 respectively with VAAnd VBIt is connected；The drain D of the transistor M1 is connected with the other end of resistance R1, the crystal
The drain D of pipe M2 is connected with the other end of resistance R2；The source S of the transistor M1 and the source S of transistor M2 are separately connected
There are current source Ki1 and current source Ki2.The other end of the current source Ki1 and current source Ki2 is grounded respectively.The transistor M1
It is connected by capacitance C1 between the source S of transistor M2.
Direct current uncoupling amplifying circuit B, the dc point for removing Differential CML signals, while to the difference CML
Signal carries out two level amplification.
In the present embodiment, the direct current uncoupling amplifying circuit B, particular circuit configurations are：With the leakage of transistor M1
Capacitance C3, the phase inverter N2 that pole D is sequentially connected in series；Capacitance C2, the phase inverter N1 being sequentially connected in series with the drain D with transistor M2；Institute
It states phase inverter N2 and the both ends phase inverter N1 is parallel with resistance R4 and resistance R3 respectively.
Duty ratio circuit for rectifying C, for during high speed CML level carries out CMOS level conversions, avoiding duty ratio
Imbalance.Specifically correcting process is：Traditional high speed CML level is during carrying out CMOS level conversions, it will usually encounter and account for
Sky is than imbalance, and the embodiment of the present invention uses the duty ratio circuit for rectifying C it is possible to prevente effectively from duty ratio is lacked of proper care so that CMOS
Level has good duty ratio characteristics.In addition, duty ratio circuit for rectifying C can also export the signal of two-way inverted phases,
It can use according to demand, can both only use single-phase, the cmos signal of differential phase can also be used.The two-way reverse phase
The signal of phase, such as 0 ° and 180 °, the signal of 90 ° and 270 ° two groups of outs of phase.
In the present embodiment, the duty ratio circuit for rectifying C, particular circuit configurations are：It is defeated with the phase inverter N2
The connected phase inverter N6 of outlet；The phase inverter N5 being connected with the output end of the phase inverter N1；And it is connected in parallel on phase inverter N5
With the phase inverter N3 and phase inverter N4 before the input terminal of phase inverter N6.The phase inverter N3 being arranged in parallel and phase inverter N4 is
It is oppositely arranged.The output end of the phase inverter N5 and phase inverter N6 turns the circuit of CMOS level respectively as the CML level
Signal output end.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (5)
1. a kind of current mode logic CML level turns CMOS level circuit structures, which is characterized in that including：
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while putting CML signals
Width carries out level-one amplification；
Direct current uncoupling amplifying circuit B, the dc point for removing Differential CML signals, while to the Differential CML signals
Carry out two level amplification；And
Duty ratio circuit for rectifying C, for during high speed CML level carries out CMOS level conversions, duty ratio being avoided to lack of proper care.
2. CML level according to claim 1 turns CMOS level circuit structures, which is characterized in that the CML level equalizations
Amplifying circuit A, physical circuit include：Resistance R1, resistance R2, transistor M1, transistor M2, current source Ki1 and current source Ki2 with
And capacitance C1；The resistance R1 and resistance R2 are all connected with operating voltage VDD；The grid G of the transistor M1 and transistor M2 is distinguished
With VAAnd VBIt is connected；The drain D of the transistor M1 is connected with the other end of resistance R1, the drain D and resistance of the transistor M2
The other end of R2 is connected；The source S of the transistor M1 and the source S of transistor M2 are connected separately with current source Ki1 and electric current
Source Ki2.The other end of the current source Ki1 and current source Ki2 is grounded respectively.The source S of the transistor M1 and transistor M2
Between by capacitance C1 be connected.
3. CML level according to claim 2 turns CMOS level circuit structures, which is characterized in that direct current uncoupling is amplified
Circuit B, physical circuit include：Capacitance C3, the phase inverter N2 being sequentially connected in series with the drain D of transistor M1；With with transistor M2's
Capacitance C2, the phase inverter N1 that drain D is sequentially connected in series；And the phase inverter N2 and the both ends phase inverter N1 are parallel with resistance R4 respectively
With resistance R3.
4. CML level according to claim 3 turns CMOS level circuit structures, which is characterized in that duty ratio circuit for rectifying
C, physical circuit include：The phase inverter N6 being connected with the output end of the phase inverter N2；With the output end with the phase inverter N1
Connected phase inverter N5；And it is connected in parallel on phase inverter N3 and phase inverter N4 before the input terminal of phase inverter N5 and phase inverter N6；
The phase inverter N3 being arranged in parallel and phase inverter N4 is oppositely arranged.
5. CML level according to claim 4 turns CMOS level circuit structures, which is characterized in that the duty ratio correction
The output end of the phase inverter N5 and phase inverter N6 of circuit C turn the signal output end of the circuit of CMOS level respectively as CML level.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810529641.4A CN108449082B (en) | 2018-05-29 | 2018-05-29 | Circuit structure for converting CML level into CMOS level |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810529641.4A CN108449082B (en) | 2018-05-29 | 2018-05-29 | Circuit structure for converting CML level into CMOS level |
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| CN108449082B CN108449082B (en) | 2024-04-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112311379A (en) * | 2019-12-17 | 2021-02-02 | 成都华微电子科技有限公司 | CML level to CMOS logic level conversion circuit |
| CN116633342A (en) * | 2023-07-21 | 2023-08-22 | 灿芯半导体(苏州)有限公司 | Conversion circuit from CML (complementary metal oxide semiconductor) to CMOS (complementary metal oxide semiconductor) level with optimized duty ratio |
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| US20070285147A1 (en) * | 2006-06-07 | 2007-12-13 | Nec Electronics Corporation | Level conversion circuit with duty correction |
| US20090058464A1 (en) * | 2007-09-04 | 2009-03-05 | Hynix Semiconductor Inc. | Current mode logic-complementary metal oxide semiconductor converter |
| GB0912942D0 (en) * | 2009-07-24 | 2009-09-02 | Texas Instruments Ltd | Improved cml to cmos converter |
| US20120206281A1 (en) * | 2011-02-11 | 2012-08-16 | University Of Florida Research Foundation, Inc. | Self-healing analog-to-digital converters with background calibration |
| CN104270122A (en) * | 2014-09-16 | 2015-01-07 | 中国科学院微电子研究所 | Duty ratio correcting circuit |
| JP2015033094A (en) * | 2013-08-06 | 2015-02-16 | 富士通セミコンダクター株式会社 | Duty cycle correction circuit |
| CN208691218U (en) * | 2018-05-29 | 2019-04-02 | 高科创芯(北京)科技有限公司 | A kind of CML level turns the circuit structure of CMOS level |
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2018
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070285147A1 (en) * | 2006-06-07 | 2007-12-13 | Nec Electronics Corporation | Level conversion circuit with duty correction |
| US20090058464A1 (en) * | 2007-09-04 | 2009-03-05 | Hynix Semiconductor Inc. | Current mode logic-complementary metal oxide semiconductor converter |
| GB0912942D0 (en) * | 2009-07-24 | 2009-09-02 | Texas Instruments Ltd | Improved cml to cmos converter |
| US20120206281A1 (en) * | 2011-02-11 | 2012-08-16 | University Of Florida Research Foundation, Inc. | Self-healing analog-to-digital converters with background calibration |
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| CN208691218U (en) * | 2018-05-29 | 2019-04-02 | 高科创芯(北京)科技有限公司 | A kind of CML level turns the circuit structure of CMOS level |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112311379A (en) * | 2019-12-17 | 2021-02-02 | 成都华微电子科技有限公司 | CML level to CMOS logic level conversion circuit |
| CN116633342A (en) * | 2023-07-21 | 2023-08-22 | 灿芯半导体(苏州)有限公司 | Conversion circuit from CML (complementary metal oxide semiconductor) to CMOS (complementary metal oxide semiconductor) level with optimized duty ratio |
| CN116633342B (en) * | 2023-07-21 | 2023-09-26 | 灿芯半导体(苏州)有限公司 | Conversion circuit from CML (complementary metal oxide semiconductor) to CMOS (complementary metal oxide semiconductor) level with optimized duty ratio |
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| CN108449082B (en) | 2024-04-16 |
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