CN208691218U - A kind of CML level turns the circuit structure of CMOS level - Google Patents
A kind of CML level turns the circuit structure of CMOS level Download PDFInfo
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- CN208691218U CN208691218U CN201820811046.5U CN201820811046U CN208691218U CN 208691218 U CN208691218 U CN 208691218U CN 201820811046 U CN201820811046 U CN 201820811046U CN 208691218 U CN208691218 U CN 208691218U
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Abstract
The utility model discloses a kind of current mode logic (CML) level to turn CMOS level circuit structure, it include: CML level equalization amplifying circuit A, for moving difference channel signal progress dc point, while level-one amplification is carried out to CML signal swing；Direct current uncoupling amplifying circuit B carries out second level amplification for removing the dc point of Differential CML signals, while to the Differential CML signals；And duty ratio circuit for rectifying C, for avoiding duty ratio from lacking of proper care during high speed CML level carries out CMOS level conversion.Using the circuit structure of the utility model, the purpose that the conversion of CML level to CMOS level is realized in High-speed IC's Chip can be efficiently solved.
Description
Technical field
The utility model relates to circuit and signal processing technologies more particularly to a kind of current mode logic (CML) level to turn
The circuit structure of CMOS level.
Background technique
In digital circuit chip, the universal transmission process of signal is all CMOS level, and so-called CMOS level just refers to
" 1 " logic-level voltages are close to supply voltage, and " 0 " logic level is close to 0V.And there is very wide noise margin.It is this
CMOS level is level standard the most general inside digital circuit, as illustrated in figs. 1A and ib.
And with the development of High-speed IC's Chip technology, in the clock tree circuit of high speed and in high-speed interface circuit
In, the circuit form of traditional cmos level standard is increasingly unable to satisfy the characteristic of high speed transmission of signals, therefore one kind occurs
New signal level transmission mode, i.e. current mode logic (Current Model Logic, CML) transmission form, this CML
Outputting and inputting for level has matched, due to reducing peripheral components, more suitable for working in higher frequency section.
The characteristics of CML level as shown in Fig. 2, be usually be made of differential signal, be converted into two differences by two differential input signals
The characteristics of point output signal, this differential signal is that signal occurs in pairs, this by the appearance of the Difference signal pair of " just " and negation
Signal is that signal swing is smaller first, and usually minimum to can achieve tens millivolts, the supply voltage of far smaller than CMOS is swung
Amplitude, therefore CML level can be referred to as the differential small-signal amplitude of oscillation again, and CMOS level can be referred to as single-ended big signal swing.
Utility model content
In view of this, the main purpose of the utility model is to provide a kind of current mode logic (CML) level to turn CMOS
Level circuit structure, to solve to realize the conversion of CML level to CMOS level in High-speed IC's Chip.
In order to achieve the above objectives, the technical solution of the utility model is achieved in that
A kind of current mode logic (CML) level turns CMOS level circuit structure, comprising:
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while believing CML
Number amplitude of oscillation carries out level-one amplification；
Direct current uncoupling amplifying circuit B, for removing the dc point of Differential CML signals, while to the difference CML
Signal carries out second level amplification；And
Duty ratio circuit for rectifying C, for avoiding duty ratio during high speed CML level carries out CMOS level conversion
Imbalance.
Wherein: the CML level equalization amplifying circuit A, physical circuit include: resistance R1, resistance R2, transistor M1, crystalline substance
Body pipe M2, current source Ki1 and current source Ki2 and capacitor C1；The resistance R1 and resistance R2 are all connected with operating voltage VDD；It is described
The grid G of transistor M1 and transistor M2 respectively with VAAnd VBIt is connected；The drain D of the transistor M1 and the other end of resistance R1
It is connected, the drain D of the transistor M2 is connected with the other end of resistance R2；The source S of the transistor M1 and transistor M2's
Source S is connected separately with current source Ki1 and current source Ki2.The other end of the current source Ki1 and current source Ki2 is grounded respectively.
It is connected between the transistor M1 and the source S of transistor M2 by capacitor C1.
The direct current uncoupling amplifying circuit B, physical circuit include: the capacitor being sequentially connected in series with the drain D of transistor M1
C3, phase inverter N2；Capacitor C2, the phase inverter N1 being sequentially connected in series with the drain D with transistor M2；And the phase inverter N2 and anti-
The both ends phase device N1 are parallel with resistance R4 and resistance R3 respectively.
The duty ratio circuit for rectifying C, physical circuit include: the phase inverter being connected with the output end of the phase inverter N2
N6；The phase inverter N5 being connected with the output end of the phase inverter N1；And it is connected in parallel on the input of phase inverter N5 and phase inverter N6
Phase inverter N3 and phase inverter N4 before end；The phase inverter N3 being arranged in parallel and phase inverter N4 is oppositely arranged.
The output end of the phase inverter N5 and phase inverter N6 of the duty ratio circuit for rectifying C turn CMOS respectively as CML level
The signal output end of the circuit of level.
Current mode logic (CML) level of the utility model turns CMOS level circuit structure, has the following beneficial effects:
The circuit structure of the utility model, by using CML level equalization amplifying circuit A, direct current uncoupling amplifying circuit B
With duty ratio circuit for rectifying C, solve that traditional high speed CML level can encounter during carrying out CMOS level conversion is accounted for
Sky compares imbalance.By using duty ratio circuit for rectifying C, effectively duty ratio can be avoided to lack of proper care, so that CMOS level has
Good duty ratio characteristics.Especially, the signal that two-way inverted phases can also be exported using duty ratio circuit for rectifying C, can
To use according to demand, single-phase can be both only used, the cmos signal of differential phase also can be used, to adapt to different circuits
Demand.
Detailed description of the invention
Fig. 1 a and Fig. 1 b are existing CMOS level circuit structural schematic diagram；
Fig. 2 is existing current mode logic (CML) electrical block diagram；
Fig. 3 is the electrical block diagram that the utility model embodiment CML level turns CMOS level.
Specific embodiment
With reference to the accompanying drawing and the embodiments of the present invention are described in further detail the utility model.
Fig. 3 is the electrical block diagram that the utility model embodiment CML level turns CMOS level.
As shown in figure 3, the CML level turns the circuit of CMOS level, CML level equalization amplifying circuit A, straight is specifically included that
Flow away amplifier circuit B and duty ratio circuit for rectifying C.Wherein:
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while believing CML
Number amplitude of oscillation carries out level-one amplification.
In the present embodiment, the CML level equalization amplifying circuit A, specifically includes that resistance R1, resistance R2, transistor
M1, transistor M2, current source Ki1 and current source Ki2 and capacitor C1.
Its particular circuit configurations are as follows: the resistance R1 and resistance R2 are all connected with operating voltage VDD.The transistor M1 and crystalline substance
The grid G of body pipe M2 respectively with VAAnd VBIt is connected；The drain D of the transistor M1 is connected with the other end of resistance R1, the crystal
The drain D of pipe M2 is connected with the other end of resistance R2；The source S of the transistor M1 and the source S of transistor M2 are separately connected
There are current source Ki1 and current source Ki2.The other end of the current source Ki1 and current source Ki2 is grounded respectively.The transistor M1
It is connected between the source S of transistor M2 by capacitor C1.
Direct current uncoupling amplifying circuit B, for removing the dc point of Differential CML signals, while to the difference CML
Signal carries out second level amplification.
In the present embodiment, the direct current uncoupling amplifying circuit B, particular circuit configurations are as follows: the leakage with transistor M1
Capacitor C3, the phase inverter N2 that pole D is sequentially connected in series；Capacitor C2, the phase inverter N1 being sequentially connected in series with the drain D with transistor M2；Institute
It states phase inverter N2 and the both ends phase inverter N1 is parallel with resistance R4 and resistance R3 respectively.
Duty ratio circuit for rectifying C, for avoiding duty ratio during high speed CML level carries out CMOS level conversion
Imbalance.Specific correcting process is: traditional high speed CML level is during carrying out CMOS level conversion, it will usually encounter and account for
Sky is than imbalance, and the utility model embodiment uses the duty ratio circuit for rectifying C it is possible to prevente effectively from duty ratio is lacked of proper care, so that
CMOS level has good duty ratio characteristics.In addition, duty ratio circuit for rectifying C can also export the letter of two-way inverted phases
Number, it can use according to demand, can both only use single-phase, the cmos signal of differential phase also can be used.The two-way
The signal of inverted phases, such as 0 ° and 180 °, the signal of 90 ° and 270 ° two groups of outs of phase.
In the present embodiment, the duty ratio circuit for rectifying C, particular circuit configurations are as follows: defeated with the phase inverter N2
The connected phase inverter N6 of outlet；The phase inverter N5 being connected with the output end of the phase inverter N1；And it is connected in parallel on phase inverter N5
With the phase inverter N3 and phase inverter N4 before the input terminal of phase inverter N6.The phase inverter N3 being arranged in parallel and phase inverter N4 is
It is oppositely arranged.The output end of the phase inverter N5 and phase inverter N6 turns the circuit of CMOS level respectively as the CML level
Signal output end.
The above, the only preferred embodiment of the utility model, are not intended to limit the protection of the utility model
Range.
Claims (5)
1. a kind of current mode logic CML level turns CMOS level circuit structure characterized by comprising
CML level equalization amplifying circuit A for moving difference channel signal progress dc point, while putting CML signal
Width carries out level-one amplification；
Direct current uncoupling amplifying circuit B, for removing the dc point of Differential CML signals, while to the Differential CML signals
Carry out second level amplification；And
Duty ratio circuit for rectifying C, for avoiding duty ratio from lacking of proper care during high speed CML level carries out CMOS level conversion.
2. CML level according to claim 1 turns CMOS level circuit structure, which is characterized in that the CML level equalization
Amplifying circuit A, physical circuit include: resistance R1, resistance R2, transistor M1, transistor M2, current source Ki1 and current source Ki2 with
And capacitor C1；The resistance R1 and resistance R2 are all connected with operating voltage VDD；The grid G of the transistor M1 and transistor M2 is distinguished
With VAAnd VBIt is connected；The drain D of the transistor M1 is connected with the other end of resistance R1, the drain D and resistance of the transistor M2
The other end of R2 is connected；The source S of the transistor M1 and the source S of transistor M2 are connected separately with current source Ki1 and electric current
Source Ki2；The other end of the current source Ki1 and current source Ki2 is grounded respectively；The source S of the transistor M1 and transistor M2
Between by capacitor C1 be connected.
3. CML level according to claim 2 turns CMOS level circuit structure, which is characterized in that direct current uncoupling amplification
Circuit B, physical circuit include: the capacitor C3 being sequentially connected in series with the drain D of transistor M1, phase inverter N2；With with transistor M2's
Capacitor C2, the phase inverter N1 that drain D is sequentially connected in series；And the phase inverter N2 and the both ends phase inverter N1 are parallel with resistance R4 respectively
With resistance R3.
4. CML level according to claim 3 turns CMOS level circuit structure, which is characterized in that duty ratio circuit for rectifying
C, physical circuit include: the phase inverter N6 being connected with the output end of the phase inverter N2；With the output end with the phase inverter N1
Connected phase inverter N5；And it is connected in parallel on phase inverter N3 and phase inverter N4 before the input terminal of phase inverter N5 and phase inverter N6；
The phase inverter N3 being arranged in parallel and phase inverter N4 is oppositely arranged.
5. CML level according to claim 4 turns CMOS level circuit structure, which is characterized in that the duty ratio correction
The output end of the phase inverter N5 and phase inverter N6 of circuit C turn the signal output end of the circuit of CMOS level respectively as CML level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820811046.5U CN208691218U (en) | 2018-05-29 | 2018-05-29 | A kind of CML level turns the circuit structure of CMOS level |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820811046.5U CN208691218U (en) | 2018-05-29 | 2018-05-29 | A kind of CML level turns the circuit structure of CMOS level |
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| Publication Number | Publication Date |
|---|---|
| CN208691218U true CN208691218U (en) | 2019-04-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820811046.5U Withdrawn - After Issue CN208691218U (en) | 2018-05-29 | 2018-05-29 | A kind of CML level turns the circuit structure of CMOS level |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108449082A (en) * | 2018-05-29 | 2018-08-24 | 高科创芯(北京)科技有限公司 | A kind of CML level turns the circuit structure of CMOS level |
-
2018
- 2018-05-29 CN CN201820811046.5U patent/CN208691218U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108449082A (en) * | 2018-05-29 | 2018-08-24 | 高科创芯(北京)科技有限公司 | A kind of CML level turns the circuit structure of CMOS level |
| CN108449082B (en) * | 2018-05-29 | 2024-04-16 | 上海芯问科技有限公司 | Circuit structure for converting CML level into CMOS level |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20190402 Effective date of abandoning: 20240416 |