CN108446098B - Method for calculating proportional value between two input voltages - Google Patents
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Abstract
The invention discloses a method for solving a proportional value between two input voltages, which comprises the steps that a proportional value calculation unit of a parallel A/D converter is used for calculating the proportional value between a numerator voltage and a denominator voltage and outputting a digital proportional value; the calculation of the proportional value between the numerator voltage and the denominator voltage is realized by a proportional value calculation unit comprising a parallel A/D converter and the parallel D/A converter, and a digital proportional value and an analog voltage proportional value are output. The method is used for occasions with low requirement on calculation speed of the proportional value and more gradual change of two input voltages.
Description
The invention relates to a circuit for solving a proportional value between two input voltages, which is applied by divisional application, has the original application number of 201610000412.4 and the application date of 2016, 1, month and 4 and is named as a circuit.
Technical Field
The invention relates to an analog operation method, in particular to a method for solving a proportional value between two input voltages.
Background
The conventional analog divider can realize division operation between analog voltages, the output of the operation result is also an analog signal, and a digital signal and an analog signal which reflect the operation result cannot be simultaneously output.
Disclosure of Invention
The invention aims to provide a solution for division operation between analog voltages, namely a method for calculating a proportional value between two input voltages and outputting a digital signal and an analog signal operation result.
In order to achieve the above object, the present invention provides a method for calculating a proportional value between two input voltages, which comprises calculating a proportional value between a numerator voltage and a denominator voltage by a proportional value calculating unit comprising a parallel a/D converter, and outputting a digital proportional value; the parallel A/D converter operates in an automatic continuous conversion mode.
The parallel A/D converter has an analog voltage input, a reference voltage input, and a parallel data output; the analog voltage input end of the parallel A/D converter is a numerator voltage input end, the reference voltage input end is a denominator voltage input end, and the parallel data output end is a digital proportion value output end.
The proportional value calculating unit consists of parallel A/D converters; the parallel A/D converter can be set in an automatic continuous conversion mode; or, the proportional value calculating unit is composed of parallel A/D converters; the parallel A/D converter restarts the next A/D conversion by a conversion end signal output by the parallel A/D converter; or, the proportional value calculating unit consists of a parallel A/D converter and an oscillator; the periodic pulse output by the oscillator is connected to the starting conversion input end of the parallel A/D converter, and the periodic pulse output by the oscillator enables the parallel A/D converter to work in an automatic continuous conversion mode.
The method for calculating the proportional value between the two input voltages can also be that a proportional value calculation unit comprising a parallel A/D converter and the parallel D/A converter realize the calculation of the proportional value between the numerator voltage and the denominator voltage and output a digital proportional value and an analog voltage proportional value.
The parallel D/A converter has a parallel data input, a reference voltage input, and a converted voltage output; the parallel data input end of the parallel D/A converter is a digital proportional value input end; the digital proportion value input end is connected to the digital proportion value output end; the conversion voltage output end is an analog voltage proportional value output end.
The digital proportion value output by the digital proportion value output end and the digital proportion value input by the digital proportion value input end are both binary numbers; when the binary digit number of the digital proportion value output end is equal to the binary digit number of the digital proportion value input end, directly connecting the binary digit of the digital proportion value input end with the binary digit of the digital proportion value output end in sequence; when the number of binary digits of the digital proportion value output end is more than that of the binary digits of the digital proportion value input end, the binary digits of the digital proportion value input end are sequentially connected from the high order of the digital proportion value output end, and the low order binary digits which are more than the digital proportion value output end are not connected to the digital proportion value input end; when the number of binary digits of the digital proportion value output end is less than that of the binary digits of the digital proportion value input end, the binary digits of the digital proportion value output end are connected in sequence from the high order of the digital proportion value input end, and the excessive low order binary digits of the digital proportion value input end are connected to the low level.
Setting the input numerator voltage as U1 and the input denominator voltage as U2; the digital proportion value output by the digital proportion value output end is Z, and the maximum value is Zmax; the voltage input by the reference voltage input end is 1V; the analog voltage proportion value output by the analog voltage proportion value output end is U0; then there is
The numerator voltage U1 and the denominator voltage U2 are positive voltages, and U1 is less than or equal to U2.
The parallel A/D converter reference voltage input end allows the input reference voltage range to be wider than the voltage range of the denominator voltage U2.
The parallel D/a converter is in a direct D/a conversion state.
The method for calculating the proportional value between the two input voltages can also be realized by a circuit comprising a proportional value calculation unit of a parallel A/D converter, the parallel D/A converter and a four-quadrant adjusting and sequencing unit, and the proportional value between the two bipolar voltages is calculated and a digital proportional value and an analog voltage proportional value are output. The four-quadrant adjusting and sorting unit consists of a voltage magnitude sorting circuit and an absolute value and sign circuit, and is provided with a first input voltage input end, a second input voltage input end, a numerator voltage output end, a denominator voltage output end, a magnitude comparison result output end and a proportion value sign output end. And the numerator voltage output end and the denominator voltage output end are connected to the numerator voltage input end and the denominator voltage input end.
The voltage magnitude sorting circuit is provided with a first input absolute value voltage input end, a second input absolute value voltage input end, a numerator voltage output end, a denominator voltage output end and a magnitude comparison result output end.
When the amplitude of the first input absolute value voltage is greater than the second input absolute value voltage, the denominator voltage output by the voltage magnitude sorting circuit is equal to the first input absolute value voltage, and the numerator voltage is equal to the second input absolute value voltage; when the amplitude of the first input absolute value voltage is smaller than the second input absolute value voltage, the denominator voltage output by the voltage magnitude sorting circuit is equal to the second input absolute value voltage, and the numerator voltage is equal to the first input absolute value voltage.
The absolute value and sign circuit is provided with a first input absolute value voltage output end, a second input absolute value voltage output end, a first input voltage input end, a second input voltage input end and a proportional value sign output end. The first input voltage and the second input voltage are bipolar voltages.
The absolute value and sign circuit includes a first absolute value circuit, a second absolute value circuit, and a sign operation circuit. The first absolute value circuit converts the first input voltage into a first input absolute value voltage and outputs the first input absolute value voltage to the voltage magnitude sorting circuit; the second absolute value circuit converts the second input voltage into a second input absolute value voltage and outputs the second input absolute value voltage to the voltage magnitude sorting circuit. The sign operation circuit outputs a proportional sign between the two input voltages in the form of a switching value according to the polarities of the first input voltage and the second input voltage.
The size comparison result output end outputs a size comparison result in the form of switching value; and the proportional value symbol output end outputs a proportional value symbol in the form of a switching value. The switching value is in the form of high and low levels.
The voltage magnitude sequencing circuit consists of a double-channel double-path analog switch and a comparator; the comparator compares the amplitude of the first input absolute value voltage and the amplitude of the second input absolute value voltage; the size comparison result output by the size comparison result output end is controlled by the output of the comparator; the channel selection of the two-channel two-way analog switch is controlled by the output of the comparator.
The invention has the advantages that the ratio value between two input voltages can be automatically obtained and output in the form of digital signals, or simultaneously output in the form of digital signals and analog signals.
Drawings
Fig. 1 is a block diagram of a circuit for obtaining a ratio between two input voltages.
Fig. 2 is embodiment 1 of the proportional value calculating unit 100.
Fig. 3 is embodiment 2 of the proportional value calculating unit 100.
Fig. 4 is embodiment 3 of the proportional value calculating unit 100.
Fig. 5 shows embodiment 1 of the simulation result output unit 200.
Fig. 6 shows embodiment 2 of the simulation result output unit 200.
FIG. 7 is a block diagram of an implementation of the four-quadrant adjusting and sorting unit 300.
Fig. 8 shows an embodiment of a voltage level ordering circuit 301.
Fig. 9 shows an embodiment of an absolute value and sign circuit 302.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.
A circuit for calculating a ratio between two input voltages is shown in fig. 1, and comprises a ratio calculating unit 100, a simulation result outputting unit 200, and a four-quadrant adjusting and sorting unit 300.
The core of the proportional value calculating unit 100 is a parallel a/D converter, which has a numerator voltage input VIN, a denominator voltage input REF, and a digital proportional value output DB OUT.
The parallel A/D converter has an analog voltage input, a reference voltage input, and a parallel data output, and operates in an automatic continuous conversion mode. The analog voltage input terminal is a numerator voltage input terminal VIN of the proportional value calculating unit 100, the reference voltage input terminal is a denominator voltage input terminal REF of the proportional value calculating unit 100, and the parallel data output terminal is a digital proportional value output terminal DB OUT of the proportional value calculating unit 100.
The analog voltage input negative terminal VIN-, the output enable terminal RD, the chip select terminal CS, the digital ground DGND and the analog ground AGND of the ADC0841 are connected to a common ground, and the power supply terminal VCC of the ADC0841 is connected to the positive power supply + VDD. When the output enable terminal RD of the ADC0841 is inputted with a low level, the data output terminals DB7 DB0 keep outputting valid. When each conversion of the ADC0841 is finished, the result is automatically output from the data output terminals DB7 DB 0.
Let the voltage connected to the numerator voltage input VIN be U1, the voltage connected to the denominator voltage input REF be U2, and the digital signal output by the digital scale value output DB OUT be Z. In embodiment 1 of the proportional value calculating unit 100, Z is Z7 to Z0 outputted from the data output terminals DB7 to DB0, and the maximum value Zmax is 255. Then there is
I.e. the ratio between the two input voltages U1, U2 is
The output enable terminal RD, the chip select terminal CS, the sleep mode select terminal PS/FS, the digital ground DGND, and the analog ground AGND of the AD7492 are connected to a common ground, and the analog power supply terminal AVDD and the digital power supply terminal DVDD of the AD7492 are connected to the positive power supply + VDD. When the output enable terminal RD of the AD7492 receives a low input, the data output terminals DB 11-DB 0 keep outputting valid. When the AD7492 conversion is finished, the result is automatically output from the data output terminals DB11 DB 0.
In embodiment 3 of the proportional value calculating unit 100, Z is Z11 to Z0 outputted from the data output terminals DB11 to DB0, and the maximum value Zmax is 4095. Then there is
I.e. the ratio between the two input voltages U1, U2 is
The parallel a/D converter reference voltage input in the proportional value calculating unit 100 allows a wider range of input reference voltages than the input voltage U2 connected to the denominator voltage input REF of the proportional value calculating unit 100.
In addition to the automatic continuous conversion mode adopted by the parallel a/D converter in the above-described 3 embodiments, when the selected parallel a/D converter can operate in the automatic continuous conversion mode by setting, it is preferable to operate the parallel a/D converter in the automatic continuous conversion mode by setting.
The core of the analog result output unit 200 is a parallel D/a converter, which has a digital proportional value input DB IN, a scale factor voltage input VIN3, and an analog voltage proportional value output VOUT. The digital scale value input terminal DB IN is connected to the digital scale value output terminal DB OUT of the scale value calculating unit 100.
The parallel D/a converter has a parallel data input, a reference voltage input, and a converted voltage output. The parallel data input terminal is a digital proportional value input terminal DB IN of the analog result output unit 200, the reference voltage input terminal is a scale factor voltage input terminal VIN3 of the analog result output unit 200, and the conversion voltage output terminal is an analog voltage proportional value output terminal VOUT of the analog result output unit 200.
A buffer switch control end BUF, an output proportion control end GAIN, an input register control end WR, a DAC register control end LDAC, a chip selection end CS and a ground end GND of the AD5330 are connected to a common ground, and a zero clearing end CLR, a low power consumption control end PD and a power supply end VDD of the AD5330 are connected to a positive power supply + VDD. When the input register control end WR of the AD5330 and the DAC register control end LDAC input are in a direct D/A conversion state, and when the conversion delay is not considered, the conversion voltage output end VOUT reflects the data conversion results of the parallel data input ends DB 7-DB 0 in real time.
Assuming that the voltage connected to the scale factor voltage input terminal VIN3 is UK, the voltage output from the analog voltage scale value output terminal VOUT is U0, and the data input from the parallel data input terminals DB7 to DB0 are Z, i.e., 8 bits of Z7 to Z0, and the maximum value Zmax1 is 255, then there are some cases where the voltage is UK, the voltage output from the analog voltage scale value output terminal VOUT is U0, and the data input from the parallel data input terminals DB7 to DB0 is Z, i.e., Z7 to Z0 with 8 bits, and the maximum value Zmax1 is 255
When Zmax1 equals Zmax, there are
When UK is equal to 1V, there are
Obviously, if the simulation result output unit 200 employs embodiment 1 thereof, Zmax1 is equal to Zmax when the proportional value calculating unit 100 employs embodiment 1 or embodiment 2. If embodiment 1 of the analog result output unit 200 is used and embodiment 3 of the scale value calculation unit 100 is used, and Zmax1 is made equal to Zmax, the upper 8 bits of the 12-bit data output from the digital scale value output terminal DB OUT of embodiment 3 of the scale value calculation unit 100 should be selected as the digital scale value input terminal DB IN signal of embodiment 1 of the analog result output unit 200.
A buffer switch control end BUF, an output proportion control end GAIN, an input register control end WR, a DAC register control end LDAC, a chip selection end CS and a ground end GND of the AD5340 are connected to a common ground, and a zero clearing end CLR, a low power consumption control end PD and a power supply end VDD of the AD5340 are connected to a positive power supply + VDD. When the input register control end WR of the AD5340 and the DAC register control end LDAC input are in a direct D/A conversion state, and when the conversion delay is not considered, the conversion voltage output end VOUT reflects the data conversion results of the parallel data input ends DB 11-DB 0 in real time.
Assuming that the voltage connected to the scale factor voltage input terminal VIN3 is UK, the voltage output from the analog voltage scale value output terminal VOUT is U0, and the data input from the parallel data input terminals DB11 to DB0 are Z, i.e., 12 bits of Z11 to Z0, and the maximum value Zmax1 is 4095, then there are
When Zmax1 equals Zmax, there are
When UK is equal to 1V, there are
Obviously, if the simulation result output unit 200 employs embodiment 2 thereof, Zmax1 is equal to Zmax when the proportional value calculating unit 100 employs embodiment 3. If Zmax1 is to be made equal to Zmax when the simulation result output unit 200 employs its embodiment 2 and the proportional value calculating unit 100 employs its embodiment 1 or embodiment 2, the 8-bit digital proportional value data of the proportional value calculating unit 100 should be connected to the upper 8 bits of the 12-bit digital proportional value input terminal of the simulation result output unit 200 and the lower 4 bits of the 12-bit digital proportional value input terminal of the simulation result output unit 200 should be connected to the common ground.
IN the 3 embodiments of the scale value calculating unit 100 and the 2 embodiments of the analog result outputting unit 200, the data of the digital scale value output terminal DB OUT and the digital scale value input terminal DB IN are binary data. The voltage U1 of the numerator voltage input VIN and the voltage U2 of the denominator voltage input REF are both positive voltages, and U1 is less than or equal to U2.
The four-quadrant adjusting and sorting unit 300 is composed of a voltage magnitude sorting circuit 301 and an absolute value and sign circuit 302.
The voltage magnitude sorting circuit 301 is used for comparing magnitudes of two positive input voltages of a to-be-obtained proportional value, namely, a first input absolute value voltage UA and a second input absolute value voltage UB, connecting a voltage with a larger magnitude as a voltage U2 at a denominator voltage input terminal REF, and a voltage with a smaller magnitude as a voltage U1 at a numerator voltage input terminal VIN to the proportional value calculating unit 100, and outputting a comparison result in the form of a switching value.
The voltage level sorting circuit 301 is shown in fig. 8 and comprises a two-channel two-way analog switch 311 and a comparator 312. The dual channel two-way analog switch 311 selects the dual 4-out-of-one multi-way analog switch CD 4052.
The comparator 312 compares the magnitudes of the first input absolute value voltage UA and the second input absolute value voltage UB, and the magnitude switch signal SW1 has a function of being output in the form of a switching value as a comparison result and a function of being connected to the channel selection terminal a of the CD 4052. The channel select terminal B, enable input terminal INH, digital ground VSS, analog ground VEE of CD4052 are connected to common ground, and VDD of CD4052 is connected to positive supply + VDD.
UA > UB, the magnitude switch signal SW1 outputs a low level; the output X of CD4052 is selectively communicated with X0, and the output Y is selectively communicated with Y0, i.e., U1 ═ X0 ═ UB, U2 ═ Y0 ═ UA; satisfy U1< U2.
When UA < UB, the magnitude switch signal SW1 outputs high level; the output X of CD4052 is selectively communicated with X1, and the output Y is selectively communicated with Y1, i.e., U1 ═ X1 ═ UA, U2 ═ Y1 ═ UB; satisfy U1< U2.
The large and small switch signals SW1 are output as a comparison result in the form of a switching value, and in addition to the high and low levels described above, various types of conventional circuits such as an NPN transistor whose collector is open, a PNP transistor whose collector is open, and a relay may be added after the large and small switch signals SW1 to obtain the switching values output in the form of normally open and normally closed switches.
The absolute value and sign circuit 302 is used for converting the first input voltage UX into a first input absolute value voltage UA, converting the second input voltage UY into a second input absolute value voltage UB, and outputting the second input absolute value voltage UB to the voltage magnitude sorting circuit 301; the sign signal SW2 of the ratio value between the two input voltages is output in the form of a switching value according to the polarities of the first input voltage UX and the second input voltage UY.
An absolute value and sign circuit 302 embodiment is shown in fig. 9.
The operational amplifier 321, the operational amplifier 322, the diode 323, the diode 324, the resistor 325, the resistor 326, the resistor 327, the resistor 328, and the resistor 329 form a first absolute value circuit, the input of which is a first input voltage UX, and the output of which is a first input absolute value voltage UA; i.e. UA is the absolute value of UX.
The operational amplifier 331, the operational amplifier 332, the diode 333, the diode 334, the resistor 335, the resistor 336, the resistor 337, the resistor 338 and the resistor 339 form a second absolute value circuit, the input of which is a second input voltage UY, and the output of which is a second input absolute value voltage UB; i.e. UB is the absolute value of UY.
The first absolute value circuit and the second absolute value circuit can use any other absolute value circuit or a precise full-wave rectifying circuit.
The comparator 341, the comparator 342, the diode 343, the diode 344, and the exclusive or gate 345 constitute a sign operation circuit.
The comparator 341 and the diode 343 convert the positive and negative polarities of the first input voltage UX into low-level and high-level signals for output and are connected to an input terminal of the xor gate 345; the comparator 342 and the diode 344 convert the positive and negative polarities of the second input voltage UY into low-level and high-level signals, and are connected to the other input terminal of the xor gate 345; the exclusive-or gate outputs a proportional value sign signal SW2 in the form of high and low levels; if the first input voltage UX and the second input voltage UY have the same polarity, the proportional value sign signal SW2 is at a low level; if the first input voltage UX is not the same as the second input voltage UY in polarity, the proportional value symbol signal SW2 is high. The exclusive or gate 345 is replaced with an exclusive or gate, or the first input voltage UX is changed from the negative input terminal connected to the comparator 341 shown in fig. 9 to the positive input terminal of the comparator 341, or the second input voltage UY is changed from the negative input terminal connected to the comparator 342 shown in fig. 9 to the positive input terminal of the comparator 342, so that the proportional-value sign signal SW2 is high when the polarities of the first input voltage UX and the second input voltage UY are the same; when the first input voltage UX and the second input voltage UY have different polarities, the proportional value symbol signal SW2 is at a low level.
The proportional value sign signal SW2 is output in the form of a switching value, and besides the high and low levels, various conventional circuits such as an NPN transistor with an open collector, an PNP transistor with an open collector, and a relay may be added after the proportional value sign signal SW2 to obtain the switching values output in the form of normally open and normally closed switches.
Taken together, when | UX | > | UY |, there are
When | UX | < | UY |, there are
When the | UX | ═ UY | is present, UA ═ UB and U1 ═ U2 are present regardless of whether SW1 is high or low, so
The device is used for occasions with low requirements on the voltage proportion value calculation speed and gentle voltage change.
The above description is only an example of the present invention and is not intended to limit the present invention, and various modifications and changes may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (8)
1. A method for calculating a ratio between two input voltages, comprising:
the calculation of the proportional value between the numerator voltage and the denominator voltage is realized by a circuit comprising a proportional value calculation unit of a parallel A/D converter and a four-quadrant adjusting and sequencing unit, and a digital proportional value is output; the parallel A/D converter works in an automatic continuous conversion mode;
the parallel A/D converter has an analog voltage input, a reference voltage input, and a parallel data output; the analog voltage input end of the parallel A/D converter is a numerator voltage input end, the reference voltage input end is a denominator voltage input end, and the parallel data output end is a digital proportion value output end;
the four-quadrant adjusting and sorting unit consists of a voltage magnitude sorting circuit and an absolute value and sign circuit, and is provided with a first input voltage input end, a second input voltage input end, a numerator voltage output end, a denominator voltage output end, a magnitude comparison result output end and a proportional value sign output end; the numerator voltage output end and the denominator voltage output end are connected to the numerator voltage input end and the denominator voltage input end;
the voltage magnitude sorting circuit is provided with a first input absolute value voltage input end, a second input absolute value voltage input end, a numerator voltage output end, a denominator voltage output end and a magnitude comparison result output end;
when the amplitude of the first input absolute value voltage is larger than the second input absolute value voltage, the denominator voltage output by the voltage magnitude sorting circuit is equal to the first input absolute value voltage, and the numerator voltage is equal to the second input absolute value voltage; when the amplitude of the first input absolute value voltage is smaller than the second input absolute value voltage, the denominator voltage output by the voltage magnitude sorting circuit is equal to the second input absolute value voltage, and the numerator voltage is equal to the first input absolute value voltage;
the absolute value and sign circuit is provided with a first input absolute value voltage output end, a second input absolute value voltage output end, a first input voltage input end, a second input voltage input end and a proportional value sign output end; the first input voltage and the second input voltage are bipolar voltages;
the absolute value and sign circuit comprises a first absolute value circuit, a second absolute value circuit and a sign operation circuit; the first absolute value circuit converts the first input voltage into a first input absolute value voltage and outputs the first input absolute value voltage to the voltage magnitude sorting circuit; the second absolute value circuit converts the second input voltage into a second input absolute value voltage and outputs the second input absolute value voltage to the voltage magnitude sorting circuit; the sign operation circuit outputs a proportional value sign between the two input voltages in a switching value mode according to the polarities of the first input voltage and the second input voltage;
the size comparison result output end outputs a size comparison result in the form of switching value; the proportional value symbol output end outputs a proportional value symbol in the form of a switching value; the switching value is in the form of high and low levels;
the voltage magnitude sequencing circuit consists of a double-channel double-path analog switch and a comparator; the comparator compares the amplitude of the first input absolute value voltage and the amplitude of the second input absolute value voltage; the size comparison result output by the size comparison result output end is controlled by the output of the comparator; the channel selection of the two-channel two-way analog switch is controlled by the output of the comparator.
2. A method of scaling two input voltages as claimed in claim 1, wherein: the parallel A/D converter restarts the next A/D conversion by a conversion end signal output by itself.
3. A method of scaling two input voltages as claimed in claim 1, wherein: the proportional value calculating unit consists of a parallel A/D converter and an oscillator; the periodic pulse output by the oscillator is connected to the starting conversion input end of the parallel A/D converter, and the periodic pulse output by the oscillator enables the parallel A/D converter to work in an automatic continuous conversion mode.
4. A method of scaling two input voltages according to any one of claims 1 to 3, characterized by: calculating a proportional value between the numerator voltage and the denominator voltage by a proportional value calculating unit and a parallel D/A converter, and outputting a digital proportional value and an analog voltage proportional value;
the parallel D/A converter has a parallel data input, a reference voltage input, and a converted voltage output; the parallel data input end of the parallel D/A converter is a digital proportional value input end; the digital proportion value input end is connected to the digital proportion value output end; the conversion voltage output end is an analog voltage proportional value output end.
5. A method of scaling two input voltages as claimed in claim 4, wherein:
the digital proportion value output by the digital proportion value output end and the digital proportion value input by the digital proportion value input end are both binary numbers; when the binary digit number of the digital proportion value output end is equal to the binary digit number of the digital proportion value input end, directly connecting the binary digit of the digital proportion value input end with the binary digit of the digital proportion value output end in sequence; when the number of binary digits of the digital proportion value output end is more than that of the binary digits of the digital proportion value input end, the binary digits of the digital proportion value input end are sequentially connected from the high order of the digital proportion value output end, and the low order binary digits which are more than the digital proportion value output end are not connected to the digital proportion value input end; when the number of binary digits of the digital proportion value output end is less than that of the binary digits of the digital proportion value input end, the binary digits of the digital proportion value output end are connected in sequence from the high order of the digital proportion value input end, and the excessive low order binary digits of the digital proportion value input end are connected to the low level.
6. A method of scaling two input voltages as claimed in claim 5, wherein: setting the input numerator voltage as U1 and the input denominator voltage as U2; the digital proportion value output by the digital proportion value output end is Z, and the maximum value is Zmax; the voltage input by the reference voltage input end is 1V; the analog voltage proportion value output by the analog voltage proportion value output end is U0; then there is
。
7. A method of scaling two input voltages as claimed in claim 6, wherein: the numerator voltage and the denominator voltage are both positive voltages, and the numerator voltage is less than or equal to the denominator voltage.
8. A method of scaling two input voltages as claimed in claim 1, wherein: the parallel A/D converter reference voltage input end allows the voltage range of the input reference voltage to be wider than that of the denominator voltage.
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| Publication number | Publication date |
|---|---|
| CN105677295A (en) | 2016-06-15 |
| CN105677295B (en) | 2018-06-26 |
| CN108446098A (en) | 2018-08-24 |
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