CN102237874A - Analog-to-digital converter and relevant calibration comparer thereof - Google Patents
Analog-to-digital converter and relevant calibration comparer thereof Download PDFInfo
- Publication number
- CN102237874A CN102237874A CN2010101666454A CN201010166645A CN102237874A CN 102237874 A CN102237874 A CN 102237874A CN 2010101666454 A CN2010101666454 A CN 2010101666454A CN 201010166645 A CN201010166645 A CN 201010166645A CN 102237874 A CN102237874 A CN 102237874A
- Authority
- CN
- China
- Prior art keywords
- relatively
- bolt
- output
- switch
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a successive approximation type analog-to-digital converter, in particular to a successive approximation type analog-to-digital converter which can be used for greatly lowering the power consumption and reducing the utilization area of a chip. The successive approximation type analog-to-digital converter comprises a sample-and-hold unit, an approximation control unit, a search memory and a calibration comparer, wherein the calibration comparer comprises a positive input end, a negative input end, a time sequence signal input end, a digital data port, a bolt-lock unit, a starting switch, a first controllable variable resistor, a second controllable variable resistor, a reset switch module, a controllable-capacitance device and an output end.
Description
Technical field
The present invention relates to a kind of successive approximation that is used for and simulate, particularly simulate to digital quantizer and relevant calibration comparator thereof with the successive approximation that reduces the chip usable floor area relevant for a kind of power consumption that can significantly reduce to digital quantizer and relevant calibration comparator thereof.
Background technology
Analog-to-digital converter (Analog to Digital Converter) can be a numerical data with the analog signal conversion in the real world, transfers to digital signal processing device again and handles.Along with science and technology is popularized day by day, many products all possess multimedia function, for example, the compression of image and voice signal or identification just must comprise the analog signal of image and sound, are converted to numerical data via analog-to-digital converter, export to digital signal processor then, carry out operation of data, be stored in numerical data memory mechanism again, or via Internet communication.In addition, the use of all types of sensing components, for example, digital clinical thermometer utilizes temperature sensor exactly, produces the temperature signal of simulation, via analog-to-digital converter, temperature signal is changed into digital pattern, in addition computing, correction and demonstration.In addition, in fields such as medical science, communication and controls, the use of analog-to-digital converter is also more and more frequent, almost can be described as omnipresent.Wherein, successive approximation is simulated to digital quantizer (Successive Approximation Analog to Digital Converter, abbreviate SAR ADC as) be a kind of common custom design of analog-to-digital converter, be common in that sampling frequency belongs to medium data volume or than the application of low speed.
Please refer to Fig. 1, Fig. 1 simulates to the schematic diagram of digital quantizer 10 for a successive approximation in the known technology.Analog-to-digital converter 10 comprises a sample-and-hold circuit 100, a comparator 102, approaches a calculation control unit 104 and a digital to analog converter 106.The mode of operation of analog-to-digital converter 10 is as follows, and at first, sample-and-hold circuit 100 is with input signal VIN sampling and maintain a sampling voltage VSIN.Comparator 102 is relatively imported the size of a sampling voltage VSIN and an aanalogvoltage VCOM, and with its comparative result output to approach the calculation control unit 104.Approach the comparative result that calculation control unit 104 is exported according to comparator 102, produce a numerical data DK, digital to analog converter 106 then is converted to aanalogvoltage VCOM with numerical data DK, and outputs to comparator 102.
In analog-to-digital converter 10, approach the comparative result of calculation control unit 104 according to comparator 102, once to produce the mode of a significance bit, produce the numerical data DK with a plurality of significance bits one by one, the aanalogvoltage VCOM that digital to analog converter 106 is produced levels off to sampling voltage VSIN.Circulation according to this is till producing all significance bits.Generally speaking, number of significant bits is relevant with the precision of analog-to-digital converter 10, number of significant bits the more, usually precision is just higher, and above-mentioned numeral to the cycle-index of analog-converted and comparison procedure also just the more.
Yet, traditional successive approximation simulate to digital quantizer must possess one independently numeral thereby derive some technical difficulty to analog-converted (DAC) unit, after Will Details is set forth in.Please refer to Fig. 2, Fig. 2 one is example with seven (7-bit) electric capacity charging-successive approximation is simulated to the schematic diagram of digital quantizer (Charge-Redistribution SAR ADC) 20.Analog-to-digital converter 20 comprises a sample-and-hold circuit 200 (among this figure do not have indicate), a comparator 202, and approaches calculation control unit 204, a numeral to analog-converted unit 206 and a reference voltage output unit 208.The framework of analog-to-digital converter 20 and function mode are 10 1 kinds of special and common patterns of analog-to-digital converter, and special character is that analog-to-digital converter 20 utilizes a kind of technology of charge redistribution, reach the function of numeral to analog-converted.In addition, numeral is formed by the capacitor C 1～C7 with different capacitances and contactor S0～S7 to analog-converted unit 206.Because when the end points of capacitor C 1～C7 is positioned at same voltage, the quantity of capacitance decision store charge, therefore numeral need have proportionate relationship accurately between the capacitance of the included different electric capacity in analog-converted unit 206, and then can make the stored amount of charge of capacitor C 1～C7, and the Mo that numeral is exported to analog-converted unit 206 intends the living enough accuracys of Dian Ya Productivity.Therefore, the amount of charge of capacitor C 1～C7 must be very good with respect to the linearity of voltage, simulate to digital conversion results accurately obtaining, and metal-insulator-metal type (Meta1-Insulator-Metal, MIM) electric capacity just meets above-mentioned condition.In known semiconductor technology, with the electric capacity of metal-insulator-metal type institute construction, its amount of charge is good far beyond metal-oxide semiconductor electric capacity (MOS Capacitor) with respect to the linearity of voltage.Yet, about 1～2 (the fF/ μ m of the unit-area capacitance value of metal-insulator-metal capacitor
2), much smaller than unit-area capacitance value (about 7fF/ μ m of metal-oxide semiconductor electric capacity
2).In other words, with respect to same capacitance, metal-insulator-metal capacitor need possess the chip area of big several times.But therefore the linearity of metal-oxide semiconductor electric capacity is not used in the design of analog-to-digital converter 20 not as metal-insulator-metal capacitor.
In addition, no matter be the particular architectures of the framework or the analog-to-digital converter 20 of analog-to-digital converter 10, numeral wherein all need use reference voltage output unit 208 that reference voltage VREF is provided to analog-converted unit 206.Show that according to experimental result the electric power that reference voltage output unit 208 is spent accounts for half of whole analog-digital converter 20 spent electric power greatly.Yet, indispensable part when numeral to analog-converted unit 206 is analog-to-digital converter 20 runnings, therefore spent a large amount of electric power can not be exempted.Simultaneously, because the power consumption of reference voltage output unit 208 is bigger, analog-to-digital converter 20 also need expend big electric energy to keep its normal operation.
Summary of the invention
Therefore, the present invention proposes a kind of successive approximation and simulates to digital quantizer and relevant calibration comparator thereof.
The present invention discloses an a kind of analog-to-digital converter of saving electrical source consumption, comprises a sampling keeping unit, is connected in an external differential input signal, according to a sampling frequency signal, takes a sample, keeps and export a differential sampled signal; One approaches control unit, is connected in this calibration comparator, according to the comparative result of this comparator, exports a memory address, and in simulating when digital translation is finished, exports a transformation result; One searches internal memory, is connected in this calibration comparator and this approaches control unit, according to this memory address, exports a numerical data these a plurality of numerical data input ports to this calibration comparator; An and calibration comparator, be connected in this sampling keeping unit, this approaches control unit and this searches internal memory, relatively this a differential sampled signal and a built-in equivalent drift voltage are exported a comparative result, comprise a positive input terminal, be used for receiving a forward signal of a differential sampled signal; One negative input end is used for receiving a negative-going signal of this differential sampled signal; One clock signal input is used for receiving a clock signal; One digital data port is used for receiving a numerical data; One bolt-lock unit, comprise one first relatively the end, one second relatively the end, one first output and one second output are used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output and this second output; One starting switch comprises one first end, and one second end is connected in this clock signal input, and one the 3rd end is connected in a ground end, is used for size according to this clock signal, controls this first end to the signal of the 3rd end and links; One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for this forward signal according to this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch; One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for this negative-going signal according to this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch; One reset switch module is connected in this clock signal input and this bolt-lock unit, is used for size according to this clock signal, controls the state of this bolt-lock unit; One controlled capacitance device is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And an output, be connected in this first output of this bolt-lock unit, be used for exporting a comparative result.
The present invention discloses a kind of successive approximation that is used in addition and simulates calibration comparator to digital quantizer, comprises a positive input terminal, is used for receiving a forward signal of a differential sampled signal; One negative input end is used for receiving a negative-going signal of this differential sampled signal; One clock signal input is used for receiving a clock signal; One digital data port is used for receiving a numerical data; One bolt-lock unit, comprise one first relatively the end, one second relatively the end, one first output and one second output are used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output and this second output; One starting switch comprises one first end, and one second end is connected in this clock signal input, and one the 3rd end is connected in a ground end, is used for size according to this clock signal, controls this first end to the signal of the 3rd end and links; One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for this forward signal according to this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch; One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for this negative-going signal according to this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch; One reset switch module is connected in this clock signal input and this bolt-lock unit, is used for size according to this clock signal, controls the state of this bolt-lock unit; One controlled capacitance device is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And an output, be connected in this first output of this bolt-lock unit, be used for exporting a comparative result.
Description of drawings
Fig. 1 simulates schematic diagram to digital quantizer for a successive approximation in the known technology.
Fig. 2 simulates schematic diagram to digital quantizer for an electric capacity charging-successive approximation in the known technology.
Fig. 3 A is that a successive approximation according to the present invention is simulated the Knot structure schematic diagram to digital quantizer.
Fig. 3 B simulates the schematic diagram of calibration module to the digital quantizer for a successive approximation according to the present invention.
Fig. 3 C is one according to calibration comparator De Knot structure schematic diagram of the present invention.
Fig. 4 is the embodiment schematic diagram of the calibration comparator of a single position.
Fig. 5 A is the embodiment schematic diagram of one or two calibration comparator.
Fig. 5 B is the embodiment schematic diagram of the calibration comparator of a multidigit.
Wherein, description of reference numerals is as follows:
10,20 analog-to-digital converters, 102,202 comparators
100 sample-and-hold circuits 104,204 approach the calculation control unit
106,206 digital to analog converters
208 reference voltage output unit
30 calibration comparators
300 reset switch modules, 302 starting switches
304 bolt-lock unit, 306 first controlled variable resistors
308 second controlled variable resistor 310 controlled capacitance devices
312 digital data port, 314 clock signal inputs
60 analog-digital converters
600 sampling keeping units 602 approach control unit
604 search internal memory
70 calibration modules
700 standard voltage sources, 702 voltage-selected switches
704 controller calibrations, 706 counters
708 internal memories
IN_P positive input terminal IN_N negative input end
Scale value VB voltage subscript value on the VA voltage
CT1 first relatively holds CT2 second relatively to hold
The OP1 first output OP2 second output
VCC power supply GND ground end
R_1～R_K resistance
C1～C7 electric capacity
S0～S7 contactor
The INV1 first inverter INV2 second inverter
VD_1～VD_N, SVD normal voltage
The EOV equivalent drift voltage
CU_1～CU_N controlled capacitance sub-cell
MP1～MP6, MP_N1 PMOS crystal
Pipe
MN1～MN9, MN_N1 nmos pass transistor
The marginal switch of the positive limit of SP_1～SP_N switch S N_1～SN_N
INV_1～INV_N inverter CC_1～CC_N electric capacity
VIN input signal VSIN sampling voltage
VCOM aanalogvoltage CLK clock signal
DK, D numerical data
D_1～D_N bit data
The anti-phase letter of YD_1～YD_N D_1～D_N
Number
Embodiment
Analog-to-digital converter in the known technology must adopt the electric capacity with the construction of metal-insulator-metal type institute, causes chip area to heighten.Trace it to its cause, caused by the restriction on the analog-to-digital converter framework in the known technology in fact.Wherein, most important reason is that known technology must adopt the voltage electric capacity good with respect to the electric charge linearity, otherwise simulation to digital transformation result just has sizable error.In addition, the existence of reference voltage VREF also makes the analog-to-digital converter power consumption in the known technology bigger.
Described in summary of the invention of the present invention, purpose of the present invention promptly is to provide a successive approximation to simulate brand-new framework to digital quantizer, use a calibration mode and method, successive approximation is simulated to digital quantizer can adopt the relatively poor electric capacity of the linearity, and do not influence the accuracy of transformation result.And brand-new framework of the present invention be because of need not using as the reference voltage VREF in the known technology, thereby the big problem of power consumption is resolved in the lump.Be convenient clear statement method of operation of the present invention and execution mode thereof,, be described in down implementation method of the present invention, principle and formation important document:
Please refer to Fig. 3 A, Fig. 3 A is that a successive approximation of the present invention is simulated to the configuration diagram of digital quantizer 60.Analog-digital converter 60 comprises that a sampling keeping unit 600, approaches control unit 602, and searches internal memory 604 and calibration comparator 30.Wherein, sampling keeping unit 600 receives an outside input differential wave VIN according to a sampling frequency signal (do not have among this figure and indicate), is taken a sample, and becomes differential sampled signal VSIN, and is sent to calibration comparator 30.Approach control unit 602 and be connected in calibration comparator 30 and search internal memory 604, be used for controlling the running of analog-to-digital converter 60.Approach the comparative result COMP of control unit 602, export a memory address ADDR to searching internal memory 604, and when simulation to the action of numeral was all finished, the transformation result to digital translation was simulated in output according to comparator.In addition, search internal memory 604 and be connected in calibration comparator 30 and approach control unit 602,, export a numerical data D to calibration comparator 30 according to approaching the memory address ADDR that control unit 602 is given.
For providing analog-to-digital converter 60 suitable calibration function, must an additional calibration module.Please refer to Fig. 3 B, Fig. 3 B is the schematic diagram that is used for a calibration module 70 of successive approximation simulation digital quantizer 60.Calibration module 70 operates in calibration mode.Wherein, calibration module 70 comprises a standard voltage source 700, a voltage-selected switch 702, a controller calibration 704, a counter 706 and an internal memory 708.When analog-digital converter 60 entered calibration mode operation, standard voltage source 700 was used for providing the normal voltage VD_1～VD_N of some between a scale value VA on the voltage and a voltage subscript value VB.Preferably, these normal voltages are evenly distributed on the voltage between the scale value VA and voltage subscript value VB, its execution mode is series resistance R_1～R_K, wherein an end is connected in scale value VA on the voltage, the other end is connected in voltage subscript value VB, can be connected required normal voltage VD_1～VD_N between resistance and the resistance.Voltage-selected switch 702 is connected in standard voltage source 700, is used for from above-mentioned normal voltage VD_1～VD_N, selects a normal voltage SVD wherein to export calibration comparator to.Counter 706 is connected in calibration comparator 30, is used to provide numerical data DD.This numerical data DD is used for adjusting an equivalent drift voltage EOV (about equivalent drift voltage EOV, please know clearly and read following explanation).Preferably, when voltage-selected switch 702 is connected in a new normal voltage VD_1～VD_N, counter 706 begins up to count or begin down to count from maximum from minimum value, is used for comparative result according to calibration comparator 60, and whether decision counter 706 should continue counting.When comparative result display standard magnitude of voltage and equivalent drift voltage EOV equate (in fact, only can judge reach the most approaching equate or inferior to the state that equates), counter 706 promptly stops counting, and is connected to next normal voltage.
In addition, in Fig. 3 B, internal memory 708 is connected in counter 706 and voltage-selected switch 702, be used for when calibration comparator 30 shows that equivalent drift voltage EOV equate with standard voltage value, in internal memory 708, write down the count value of counter 706 at this moment and the standard voltage value index value or the numbering of standard voltage value (or corresponding to).Preferably, internal memory 708 is searched internal memory 704 for what share with analog-to-digital converter 60.For example, N normal voltage VD_1～VD_N arranged, when calibration was finished, internal memory 708 should have N data.In addition, controller calibration 704 is connected in voltage-selected switch 702, counter 706 and internal memory 708, is used for comparative result according to calibration comparator 30, the action of control voltage-selected switch 702, counter 706 and internal memory 708.When voltage-selected switch 702 was connected to a new normal voltage VD_1～VD_N, controller calibration 704 command counters 706 restarted counting.When calibration comparator 30 shows that equivalent drift voltage EOV and standard voltage value reach the most approaching or inferior approaching state, the count value of the standard voltage value of 708 record this moments of controller calibration 704 order internal memories one index value or the numbering of standard voltage value (or corresponding to) and counter 706 is all calibrated end up to all normal voltage VD_1～VD_N.
After calibration module 70 is finished calibration actions in the successive approximation simulation digital quantizer, the present invention will be converted to the normal manipulation mode of the analog-to-digital converter 60 among Fig. 3 A automatically.Wherein, about surely belonging to this area tool general knowledge person, required modulation control (Switching Control) circuit of the conversion of data path between calibration mode and the normal manipulation mode (Data Path) knows, and be achieved, so do not give unnecessary details or express in figure according to above-listed description.
Thin bilge construction about calibration comparator 30 please refer to Fig. 3 C, and Fig. 3 C is depicted as the schematic diagram of one of embodiment of the invention calibration comparator 30.Calibration comparator 30 comprises a positive input terminal IN_P, a negative input end IN_N, a clock signal input 314, a digital data port 312, a reset switch module 300, a starting switch 302, a bolt-lock unit 304, one first controlled variable resistor 306, one second a controlled variable resistor 308 and a controlled capacitance device 310.Positive input terminal IN_P and negative input end IN_N are used for receiving the positive and negative to signal of differential sampled signal respectively.Preferably, outside input differential wave VIN is after sampling, become differential sampled signal VSIN, the positive phase signals of differential sampled signal VSIN is connected in the positive input terminal IN_P of calibration comparator 30, and the negative signal of differential sampled signal VSIN then is connected in the negative input end IN_N of calibration comparator 30; In addition, the voltage-selected switch 702 that is used for calibration mode also can export normal voltage SVD to the positive input terminal IN_P of calibration comparator, and with the negative input end IN_N ground connection of calibration comparator, the voltage standard that calibration comparator is used with as calibration the time.Secondly, clock signal input 314 is used for receiving a clock signal CLK, as the sequential benchmark of control calibration comparator 30.Digital data port 312 is used for receiving a numerical data D, and it comprises N positions such as D_1～D_N.Bolt-lock unit 304 comprises that one first relatively holds CT1, one second relatively to hold CT2, one first output OP1 and one second output OP2, be used for the difference that comparison first relatively holds CT1 and second relatively to hold CT2 circuit numerical value, to determine the state value of the first output OP1 and the second output OP2.Starting switch 302 is used for according to the voltage of clock signal CLK, controls the first controlled variable resistor 306 and the second controlled variable resistor 308 to the signal between the ground end and links, to start comparison.The first controlled variable resistor 306 and the second controlled variable resistor 308 are connected to the positive input terminal IN_P and the negative input end IN_N of differential sampled signal, be used for forward signal and negative-going signal according to differential sampled signal, adjust first respectively and relatively hold CT1 and second relatively to hold CT2 to the resistance value between the starting switch 302.Reset switch module 300 is used for according to the size of clock signal CLK, the state of control bolt-lock unit 304.Preferably, when clock signal CLK arrives a default voltage (is a low-voltage at this), reset switch module 300 relatively holds CT1, second relatively to hold the voltage of end points such as CT2, the first output OP1 and the second output OP2 with first, is refitted in the magnitude of voltage near power supply VCC.Controlled capacitance device 310 is connected in first and relatively holds CT1, second relatively to hold CT2 and ground end GND, is used for according to numerical data D control first capacitance of relatively holding CT1 and second relatively to hold CT2 extremely to hold.In addition, it should be noted that the designer can select to export a comparative result by the first output OP1 or the second output OP2.Please refer to Fig. 3 C, Fig. 3 C utilizes the first output OP1 to export comparative result COMP.And preferably, the first controlled variable resistor 306 and the second controlled variable resistor 308 are N type MOS (metal-oxide-semiconductor) transistor (NMOS).
In simple terms, reset switch module 300 conducting when clock signal CLK electronegative potential makes first relatively to hold CT1, second relatively to hold CT2, the first output OP1 and the second output OP2 all to draw high high potential, with the action of the bolt-lock unit 304 of resetting.Starting switch 302 is controlled by clock signal CLK also, and different with reset switch module 300 is that starting switch 302 conducting when clock signal CLK high potential is in order to start the comparison of calibration comparator 30.In addition, bolt-lock unit 304 relatively first relatively holds CT1 and second relatively to hold the difference of CT2 circuit coefficients value, preferably can be the difference of resistance value, the difference of capacitance or the gap of the product of resistance value and capacitance.When calibration comparator 30 starts, first input end CT1 is refitted in identical voltage (approximating power supply VCC) with the second input CT2, but, because the difference of the circuit coefficients of the first input end CT1 and the second input CT2, the voltage that impels first input end CT1 and the second input CT2 with different speed to the low-voltage convergence.Wherein, the end that the product of resistance value and capacitance is bigger, its speed to the low-voltage convergence is slower.Otherwise, the end that the product of resistance value and capacitance is smaller, then velocity of approach is very fast.Because first relatively holds CT1 and second relatively to hold the velocity of approach difference at two ends such as CT2, can make bolt-lock unit 304 toward different stable state convergences.For example, first relatively holds CT1 very fast to the speed of low-voltage convergence, then reaches when stablizing in bolt-lock unit 304 states, and the first output OP1 is a high voltage, and second relatively to hold CT2 be low-voltage.Otherwise, if second relatively hold CT2 very fast to the speed of low-voltage convergence, then reaching when stablizing in bolt-lock unit 304 states, the first output OP1 is a low-voltage, and second relatively holds CT2 to be high voltage.Preferably, because the output of calibration comparator 30 is connected in the first output OP1.At last, the comparative result of calibration comparator 30 is exactly the steady-state voltage value of the first output OP1.
Therefore, control the first controlled variable resistor 306 and the second controlled variable resistor 308 by differential sampled signal, the present invention can control the resistance value of the first input end CT1 and the second input CT2 respectively.Simultaneously, the numerical data D by digital data port 312 is received controls controlled capacitance device 310, and then controls the capacitance of the first input end CT1 and the second input CT2 respectively.At last, by comparing first input end CT1 and the resistance value of the second input CT2 and the product size of capacitance, the output voltage of decision calibration comparator 30.In addition, when the resistance value of the first input end CT1 and the second input CT2 is individually fixed in certain value, also can be by only adjusting the comparative result of its other capacitance with decision calibration comparator 30; Perhaps, when the capacitance of the first input end CT1 and the second input CT2 is individually fixed in certain value, also can be by adjusting the comparative result of its other resistance value separately with decision calibration comparator 30.
Such as the present invention can make the resistance value of the first input end CT1 and the second input CT2 be individually fixed in certain value by fixing differential sampled signal.Simultaneously, by the numerical data D that digital data port 312 is received, control controlled capacitance device 310 progressively changes first and relatively holds CT1 relatively to hold the capacitance of CT2 with respect to second, and reads the comparative result of calibration comparator 30 successively.Then when the comparative result of calibration comparator 30 shows that the circuit coefficients of the first input end CT1 and the second input CT2 is the most approaching or inferior approaching state, write down the corresponding relation between differential sampled signal and the numerical data D.Preferably, any one the numerical data D in this corresponding relation can be used to corresponding to a normal voltage.Thus, the present invention can utilize this phenomenon, by calibration comparator 30 is carried out calibration actions.About the calibrating mode and the device of calibration comparator 30, will be in hereinafter describing in detail.
It should be noted that the numerical data that is received by digital data port 312, control controlled capacitance device 310 can be considered in first and relatively holds CT1 and second relatively to hold between the CT2, produces a correspondent voltage value.The present invention claims this to be " equivalent drift voltage " (EquivalentOffset Voltage) EOV because of the pairing voltage difference of imbalance.Equivalent drift voltage EOV is former to betide a kind of phenomenon of Voltage unbalance of two inputs of general operation amplifier before this, and this energy imbalance is generally led because of due to circuit design or error that chip manufacturing produced.The present invention utilizes the energy imbalance that artificially painstakingly causes two inlet circuit coefficients, produces a voltage differences in the input of calibration comparator 30, and is used the comparison signal size.Therefore, calibration comparator 30 also can be considered the device in order to more differential sampled signal and equivalent drift voltage EOV.Preferably, when differential sampled signal during greater than equivalent drift voltage EOV, the comparative result of calibration comparator 30 is a high voltage (logical value is 1); Otherwise when differential sampled signal during less than equivalent drift voltage EOV, the comparative result of calibration comparator 30 is a low-voltage (logical value is 0).
In brief, calibration comparator 30 determines the stable state of bolt-lock unit 304 by positive input terminal IN_P and the voltage of negative input end IN_N and the numerical data that digital data port 312 is received, and as the comparative result of calibration comparator 30.Calibration comparator 30 both can be used for converting a stroke numeral data D to an equivalent drift voltage EOV, was used for doing with an external voltage comparison of voltage swing.In addition, also can be by changing numerical data D, at a normal voltage, the work of calibrating obtains the pairing equivalent drift voltage EOV of numerical data D.
Be noted that the calibration comparator 30 shown in Fig. 3 C is the present invention's embodiment schematic diagram, this area tool knows that usually the knowledgeable is when doing suitable modification, and be not limited thereto according to different demands.For instance, please refer to Fig. 4, Fig. 4 is the circuit diagram of calibration comparator 30.In Fig. 4, the first controlled variable resistor 306 and the second controlled variable resistor 308 are formed by transistor MN3 and transistor MN4 respectively.The gate of transistor MN3 and transistor MN4 is connected to positive input terminal IN_P and negative input end IN_N, is used for receiving differential sampled signal.Starting switch 302 is formed by transistor MN5, and conducting when it is high voltage at clock signal CLK is to start the comparison of calibration comparator 30.Reset switch module 300 is formed by transistor MP3, MP4, MP5 and MP6, respectively in order to realize a reset switch, with conducting when clock signal CLK is low-voltage, thereby relatively hold CT1, second relatively to hold CT2, the first output OP1 and the second output OP2 to be refitted in high voltage with first.Bolt-lock unit 304 is formed by transistor MN1, MP1, MN2 and MP2.Wherein, transistor MN1 and MP1 form one first inverter INV1, and transistor MN2 and MP2 form one second inverter INV2.The input of the output of the first inverter INV1 and the second inverter INV2 is connected, and the input of the output of the second inverter INV2 and the first inverter INV1 is connected, and forms the latch assembly 304 that can keep in the one digit number certificate.Because first input end CT1 is connected in the source electrode of transistor MN1 in the bolt-lock unit 304, if the source voltage of transistor MN1 is higher, then the driving force by transistor MP1 and the formed first inverter INV1 of transistor MN1 diminishes.If the same time, the source voltage of transistor MN2 that is connected in the second input CT2 is lower, and then the driving force by transistor MP2 and the formed second inverter INV2 of transistor MN2 becomes big.Thus, have the stable state that will determine bolt-lock unit 304 than the inverter of strong driving force.With the said circumstances is example, and the driving force of transistor MP2 and the formed second inverter INV2 of transistor MN2 is bigger, will make the first output OP1 be output as low-voltage.Otherwise if the source voltage of transistor MN1 is lower, the driving force of the first inverter INV1 that is formed by transistor MP1 and transistor MN1 is bigger, then will make the first output OP1 be output as high voltage.
It should be noted that, according to circuit theory, electrical conductivity between field-effect transistor drain and the source electrode (conductivity) can increase with the enhancing of drain to the passage electric field strength between the source electrode, so, can change the drain of transistor and the electrical conductivity between the source electrode via the gate of oxide-semiconductor control transistors voltage difference to source electrode.Therefore, under all identical situation of the length and width of transistor MN3 and MN4, the electrical conductivity between transistor drain and the source electrode will be proportional to transistorized aisle resistance, thereby can be poor to source voltage by transistorized gate, adjust transistorized aisle resistance.Therefore controlled variable resistor 306 and 308 can be realized with transistor MN3 and MN4 respectively.
In addition, for making things convenient for clear interpretation controlled capacitance device 310, please continue with reference to figure 4.Controlled capacitance device 310 among Fig. 4 is controlled by the numerical data D_1 of single position, wherein comprises positive limit switch S P_1, marginal switch S N_1, inverter INV_1 and capacitor C C_1.Positive limit switch S P_1 and marginal switch S N_1 are formed by transistor MN6 and MN7 respectively, are used for controlling first and relatively hold CT1 and second relatively to hold the binding of CT2 to capacitor C C_1.Inverter INV_1 is formed by transistor MP_N1 and MN1_N1, in order to produce the inversion signal YD_1 of bit data D_1.Capacitor C C_1 is formed by a metal-oxide semiconductor formula electric capacity, as first capacitance of relatively holding CT1 or second relatively to hold CT2 to observe is provided.
In Fig. 4, controlled capacitance device 310 only comprises an electric capacity, and in fact, controlled capacitance device 310 also can be according to different demands, and the more than one electric capacity of surpassing is arranged.Please refer to Fig. 5 A, Fig. 5 A shows another embodiment schematic diagram of calibration comparator 30.For knowing that demonstration connects the method that is subjected to more than the circuit of the controlled capacitance device 310 of a controlled capacitance sub-cell, in Fig. 5 A, controlled capacitance device 310 comprises controlled capacitance sub-cell CU_1 and CU_2, and controls this two controlled capacitance sub-cells (CU_1 and CU_2) by two numerical data D (comprising a D_1 and D_2).Controlled capacitance sub-cell CU_1 comprises that the formed positive limit of transistor MN6 switch, the formed marginal switch of transistor MN7, an inverter (not being shown among the figure) and are by the formed capacitance component CC_1 of metal-oxide semiconductor formula electric capacity.The gate of transistor MN6 is connected in the position D_1 of numerical data D, and the gate of transistor MN7 is connected in the inversion signal YD_1 of a D_1.Controlled capacitance sub-cell CU_2 comprises that the formed positive limit of transistor MN8 switch, the formed marginal switch of a transistor MN9, an inverter (not being shown among the figure) and are by the formed capacitance component CC_2 of metal-oxide semiconductor formula electric capacity.The gate of transistor MN8 is connected in the position D_2 of numerical data D, and the gate of transistor MN9 is connected in the inversion signal YD_2 of a D_2.Wherein, the capacitance of capacitance component CC_2 is a times of capacitance component CC_1; Therefore, can relatively hold CT1 and second relatively to hold in first and produce the capacitance that quadravalence (i.e. two quadratic power rank) varies in size between the CT2 by control bit D_1 and position D_2.In addition, other How It Works all is entirely identical to aforementioned, so will not give unnecessary details.
Please refer to Fig. 5 B, Fig. 5 B is another embodiment schematic diagram of calibration comparator 30.In Fig. 5 B, controlled capacitance device 310 comprises controlled capacitance sub-cell CU_1～CU_N.Wherein, each controlled capacitance sub-cell of controlled capacitance sub-cell CU_1～CU_N all comprises a positive limit switch, a marginal switch, an inverter and an electric capacity.Therefore, N controlled capacitance sub-cell CU_1～CU_N comprises N positive limit switch S P_1～SP_N, N marginal switch S N_1～SN_N, N inverter INV_1～INV_N and N capacitor C C_1～CC_N altogether.Wherein, the capacitance of capacitor C C_1～CC_N is the binary system proportionate relationship.In addition, in Fig. 5 B, a digital data port 312 is used for receiving digital data D (containing D_1～D_N equipotential).Preferably, the figure place of numerical data D is corresponding to the number of controlled capacitance device 310, and it represents the numeral of a binary system, and in order to represent the size of specific physical quantity or numeral, for example the position of voltage is accurate or the like.Because the capacitance among controlled capacitance sub-cell CU_1～CU_N is one to be the sequence of binary system proportionate relationship, make each controlled capacitance sub-cell CU_1～CU_N corresponding one to one with each D_1～D_N among the numerical data D, and connect one to one, for example, D_1 be connected in CU_1, D_2 be connected in CU_2 ..., and D_N be connected in CU_N or the like.Thus, the size of numerical data D representative can man-to-man various combination corresponding to capacitance in all controlled capacitance sub-cells.Therefore, can pass through control bit D_1～D_N, in first capacitance of relatively holding CT1 and second relatively to hold the Nth power rank of CT2 generation two to vary in size.Therefore, can further pass through input digital data D, the control first electric capacity number of relatively holding CT1 and second relatively to hold CT2 to observe is to produce the equivalent drift voltage EOV that two Nth power rank vary in size, as comparing than usefulness with differential sampled signal.In addition, in Fig. 5 B, except obvious sign controlled capacitance sub-cell CU_1～CU_N, remaining circuit and How It Works all are entirely identical to aforementioned, so will not give unnecessary details.
Therefore, when needs increased numeral to the precision of analog-converted, calibration comparator 30 Only need increase the figure place of numerical data D and the number of controlled capacitance sub-cell CU_1～CU_N, can increase the precision of numeral to analog-converted.Wherein, owing to the capacitor C C_1～CC_N in the controlled capacitance sub-cell all can be formed by metal-oxide semiconductor formula electric capacity (MOS Capacitor), to save chip area.According to the experimental measurement result, the unit-area capacitance value of metal-oxide semiconductor formula electric capacity is about 7fF/ μ m
2Therefore, metal-oxide semiconductor formula electric capacity shared chip area can (the unit-area capacitance value be about 1～2fF/ μ m far beyond general employed metal-insulator-metal type formula electric capacity
2) reduce many.
More than by among the present invention implementation method, principle and the constitutive requirements of calibration comparator of use.According to above-mentioned calibration comparator, the present invention is set up the brand-new framework of an analog-to-digital converter.Calibration comparator 30 can be according to multistage comparison and judgment mode, differential sampled signal VSIN after each sampling is carried out the inferior comparison of plural number, comparison each time all can produce a new significance bit, makes the progressively differential sampled signal VSIN of convergence of the pairing equivalent drift voltage EOV of numerical data D.The pairing numerical data D of memory address ADDR is corresponding to the equivalent drift voltage EOV of calibration comparator 30.In brief, the control unit 602 that approaches of analog-to-digital converter 60 is judged the pairing memory address ADDR of equivalent drift voltage EOV of next stage according to the comparative result COMP of calibration comparator 30, and exports to and search internal memory 604.Calibration comparator 30 is according to searching the numerical data D that internal memory 604 is exported, with control controlled capacitance sub-cell CU_1～CU_N (relevant numerical data D and controlled capacitance sub-cell CU_1～CU_N, please refer to Fig. 5 B), produce the equivalent drift voltage EOV of next stage, with the differential sampled signal VSIN of convergence.Approach control unit 602 and whenever do the action of once judging, analog-to-digital converter 60 just produces a new significance bit, and circulation according to this is till producing all significance bits.It should be noted that to meeting the requirement of accuracy the figure place of searching the numerical data D that internal memory 604 exported should be exported the figure place of memory address ADDR at least greater than calibration comparator.
Hence one can see that, because the calibration comparator that used of the disclosed analog-to-digital converter 60 of the present invention 30 is integrated numeral to the analog-converted function, thereby can exempt in the known technology numeral to analog-converted unit 106, and then the consumption of saving electric power.In addition, analog-to-digital converter 60 can be in when start, and the situation that needs to recalibrate carries out the calibration actions of calibration comparator 30 when taking place, to set up or to upgrade the corresponding relation of searching numerical data D and equivalent drift voltage EOV in the internal memory 604.
In sum, one of the present invention and known technology major technique difference is that the present invention uses one to integrate the comparator of numeral to the analog-converted function, and numeral is removed to the analog-converted unit.
Simultaneously, exempted digital reference voltage circuit in the known technology, thereby saved many electric power to the required use in analog-converted unit.Via distinctive calibration procedure, the present invention's analog-to-digital converter can store the numerical data of comparator and the functional relation of equivalent drift voltage, makes the present invention need not the capacitive means that uses the linearity good, can simulate to digital translation accurately.Via the metal-oxide semiconductor formula electric capacity that uses high unit-area capacitance value, chip area that electric capacity is shared thereby significantly minimizing.
Generally speaking, by the unique architecture and the comparator of integration numeral to the analog-converted function that design an analog-to-digital converter, to replace known numeral to the analog-converted unit, the present invention can effectively reach significantly saves energy and the effect that reduces chip area.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (29)
1. analog-to-digital converter of saving electrical source consumption is characterized in that comprising:
One sampling keeping unit is connected in an external differential input signal, according to a sampling frequency signal, takes a sample, keeps and export a differential sampled signal;
One approaches control unit, is connected in this calibration comparator, according to the comparative result of this comparator, exports a memory address, and in simulating when digital translation is finished, exports a transformation result;
One searches internal memory, is connected in this calibration comparator and this approaches control unit, according to this memory address, exports a numerical data these a plurality of numerical data input ports to this calibration comparator; And
One calibration comparator is connected in this sampling keeping unit, this approaches control unit and this searches internal memory, and relatively this a differential sampled signal and a built-in equivalent drift voltage are exported a comparative result, comprising:
One positive input terminal is used for receiving a forward signal of a differential sampled signal;
One negative input end is used for receiving a negative-going signal of this differential sampled signal;
One clock signal input is used for receiving a clock signal;
One digital data port is used for receiving a numerical data;
One bolt-lock unit, comprise one first relatively the end, one second relatively the end, one first output and one second output are used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output and this second output;
One starting switch comprises one first end, and one second end is connected in this clock signal input, and
One the 3rd end is connected in a ground end, is used for size according to this clock signal, controls this first end to the signal of the 3rd end and links;
One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for this forward signal according to this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch;
One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for this negative-going signal according to this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch;
One reset switch module is connected in this clock signal input and this bolt-lock unit, is used for size according to this clock signal, controls the state of this bolt-lock unit;
One controlled capacitance device is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And
One output is connected in this first output of this bolt-lock unit, is used for exporting a comparative result.
2. analog-to-digital converter as claimed in claim 1 is characterized in that comprising a calibration module in addition, is used for calibrating this analog-to-digital converter.
3. analog-to-digital converter as claimed in claim 2 is characterized in that this calibration module comprises:
One standard voltage source is used for providing a plurality of standard voltage value between a scale value on the voltage and a voltage subscript value;
One voltage-selected switch is connected in this standard voltage source and this positive input terminal, with selecting a standard voltage value to export this positive input terminal in these a plurality of standard voltage value of cause;
One counter is connected in this controller calibration, this internal memory and this calibration comparator, is used for producing a count results;
One internal memory is connected in this counter, is used for when this calibration comparator shows that this comparative result equates, writes down this count results of this counter in a memory address corresponding to this standard voltage value; And
One controller calibration is connected in this calibration comparator, is used for controlling this count results that this internal memory writes down this counter when this calibration comparator shows that this comparative result equates.
4. analog-to-digital converter as claimed in claim 1, it is characterized in that this first controlled variable resistor, this second controlled variable resistor and this starting switch are all N type MOS (metal-oxide-semiconductor) transistor, one drain of this first controlled variable resistor and this second controlled variable-resistance this N type MOS (metal-oxide-semiconductor) transistor be connected in this bolt-lock unit this first relatively the end, one gate is connected in this positive input terminal, and one source pole is connected in this first end of this starting switch.
5. analog-to-digital converter as claimed in claim 1 is characterized in that this reset switch module comprises:
One first reset switch comprises that one first end is connected in a power supply, and one second end is connected in this clock signal input, and one the 3rd end be connected in this bolt-lock unit this first relatively the end, be used for according to clock signal, this first end of conducting is to the binding of the 3rd end;
One second reset switch comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, reaches this first output that one the 3rd end is connected in this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the binding of the 3rd end;
One the 3rd replacement switch comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, reaches this second output that one the 3rd end is connected in this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the binding of the 3rd end; And
One quadruple is put switch, comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, and one the 3rd end be connected in this bolt-lock unit this second relatively the end, be used for according to clock signal, this first end of conducting is to the binding of the 3rd end.
6. analog-to-digital converter as claimed in claim 5, it is characterized in that this first reset switch, this second reset switch, the 3rd replacement switch and this quadruple put switch and be all P type MOS (metal-oxide-semiconductor) transistor, and this of each reset switch first end is an one source pole, this second end is a gate, and the 3rd end is a drain.
7. analog-to-digital converter as claimed in claim 1 is characterized in that this bolt-lock unit comprises:
One first inverter is connected in a power supply, this first relatively end, this first output and this second output, is used for according to this power supply and this first signal of end relatively, and the anti-phase result of signal who exports this first output is to this second output; And
One second inverter is connected in this power supply, this second relatively end, this first output and this second output, is used for the signal relatively held according to this power supply and second, and the anti-phase result of signal who exports this second output is to this first output.
8. analog-to-digital converter as claimed in claim 7 is characterized in that this first inverter and this second inverter all respectively comprise:
One P type MOS (metal-oxide-semiconductor) transistor, the one gate is connected in this first output, and one source pole is connected in this power supply, and a drain is connected in this second output; And
One N type MOS (metal-oxide-semiconductor) transistor, the one gate is connected in this first output, and one source pole is connected in this first end relatively, and a drain is connected in this second output.
9. analog-to-digital converter as claimed in claim 1 is characterized in that this controlled capacitance device comprises:
One electric capacity comprises one first end, and one second end is connected in this ground end;
One positive limit switch, comprise that one first end is connected in this first end relatively of this bolt-lock unit, one second end is connected in this numerical data, and one the 3rd end is connected in this electric capacity, be used for signal magnitude according to this numerical data, this first end of conducting to the signal of the 3rd end links;
One inverter is used for producing the anti-phase result of this numerical data; And
One marginal switch, comprise that one first end is connected in this second end relatively of this bolt-lock unit, one second end is connected in this inverter, and one the 3rd end is connected in this electric capacity, be used for inversion signal size according to this numerical data, this first end of conducting to the signal of the 3rd end links.
10. analog-to-digital converter as claimed in claim 9, it is characterized in that this positive limit switch and this marginal switch are all N type MOS (metal-oxide-semiconductor) transistor, this first end of this positive limit switch or this marginal switch is a drain, and this second end is a gate, and the 3rd end is an one source pole.
11. analog-to-digital converter as claimed in claim 1 is characterized in that this circuit coefficients value is a resistance value, or a capacitance, or the product of a capacitance and a resistance value.
12. analog-to-digital converter as claimed in claim 1 is characterized in that this controlled capacitance device comprises:
A plurality of electric capacity, each electric capacity comprise one first end, and one second end is connected in this ground end;
A plurality of positive limits switch, each positive limit switch comprise one first end be connected in this bolt-lock unit this first relatively the end, one second end is connected in this numerical data, and one the 3rd end is connected in an electric capacity of these a plurality of electric capacity, be used for signal magnitude according to this numerical data, this first end of conducting to the signal of the 3rd end links;
A plurality of inverters, each inverter are used for producing the anti-phase result of this numerical data; And
A plurality of marginal switches, each marginal switch comprise one first end be connected in this bolt-lock unit this second relatively the end, one second end is connected in this inverter, and one the 3rd end is connected in an electric capacity of these a plurality of electric capacity, be used for inversion signal size according to this numerical data, this first end of conducting to the signal of the 3rd end links.
13. analog-to-digital converter as claimed in claim 12 is characterized in that the capacitance of these a plurality of electric capacity is the binary system proportionate relationship.
14. analog-to-digital converter as claimed in claim 12, it is characterized in that this a plurality of positive limits switch and these a plurality of marginal switches are all N type MOS (metal-oxide-semiconductor) transistor, this first end of each positive limit switch or marginal switch is a drain, and this second end is a gate, and the 3rd end is an one source pole.
15. a calibration comparator that is used for an analog-to-digital converter is characterized in that comprising:
One positive input terminal is used for receiving a forward signal of a differential sampled signal;
One negative input end is used for receiving a negative-going signal of this differential sampled signal;
One clock signal input is used for receiving a clock signal;
One digital data port is used for receiving a numerical data;
One bolt-lock unit, comprise one first relatively the end, one second relatively the end, one first output and one second output are used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output and this second output;
One starting switch comprises one first end, and one second end is connected in this clock signal input, and one the 3rd end is connected in a ground end, is used for size according to this clock signal, controls this first end to the signal of the 3rd end and links;
One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for this forward signal according to this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch;
One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for this negative-going signal according to this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch;
One reset switch module is connected in this clock signal input and this bolt-lock unit, is used for size according to this clock signal, controls the state of this bolt-lock unit;
One controlled capacitance device is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And
One output is connected in this first output of this bolt-lock unit, is used for exporting a comparative result.
16. calibration comparator as claimed in claim 15, it is characterized in that this first controlled variable resistor and this second controlled variable resistor are N type MOS (metal-oxide-semiconductor) transistor, one drain of this N type MOS (metal-oxide-semiconductor) transistor be connected in this bolt-lock unit this first relatively the end, one gate is connected in this positive input terminal, and one source pole is connected in this first end of this starting switch.
17. calibration comparator as claimed in claim 15 is characterized in that this starting switch is a N type MOS (metal-oxide-semiconductor) transistor, this of this starting switch first end is a drain, and this second end is a gate, and the 3rd end is an one source pole.
18. calibration comparator as claimed in claim 15 is characterized in that this reset switch module comprises:
One first reset switch comprises that one first end is connected in a power supply, and one second end is connected in this clock signal input, and one the 3rd end be connected in this bolt-lock unit this first relatively the end, be used for according to clock signal, this first end of conducting is to the binding of the 3rd end;
One second reset switch comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, reaches this first output that one the 3rd end is connected in this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the binding of the 3rd end;
One the 3rd replacement switch comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, reaches this second output that one the 3rd end is connected in this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the binding of the 3rd end; And
One quadruple is put switch, comprises that one first end is connected in this power supply, and one second end is connected in this clock signal input, and one the 3rd end be connected in this bolt-lock unit this second relatively the end, be used for according to clock signal, this first end of conducting is to the binding of the 3rd end.
19. calibration comparator as claimed in claim 18, it is characterized in that this first reset switch, this second reset switch, the 3rd replacement switch and this quadruple put switch and be all P type MOS (metal-oxide-semiconductor) transistor, and this of each reset switch first end is an one source pole, this second end is a gate, and the 3rd end is a drain.
20. calibration comparator as claimed in claim 15 is characterized in that this bolt-lock unit comprises:
One first inverter is connected in a power supply, this first relatively end, this first output and this second output, is used for according to this power supply and this first signal of end relatively, and the anti-phase result of signal who exports this first output is to this second output; And
One second inverter is connected in this power supply, this second relatively end, this first output and this second output, is used for the signal relatively held according to this power supply and second, and the anti-phase result of signal who exports this second output is to this first output.
21. calibration comparator as claimed in claim 20 is characterized in that this first inverter and this second inverter all respectively comprise:
One P type MOS (metal-oxide-semiconductor) transistor, the one gate is connected in this first output, and one source pole is connected in this power supply, and a drain is connected in this second output; And
One N type MOS (metal-oxide-semiconductor) transistor, the one gate is connected in this first output, and one source pole is connected in this first end relatively, and a drain is connected in this second output.
22. calibration comparator as claimed in claim 15 is characterized in that this controlled capacitance device comprises:
One electric capacity comprises one first end, and one second end is connected in this ground end;
One positive limit switch, comprise that one first end is connected in this first end relatively of this bolt-lock unit, one second end is connected in this numerical data, and one the 3rd end is connected in this electric capacity, be used for signal magnitude according to this numerical data, this first end of conducting to the signal of the 3rd end links;
One inverter is used for producing the anti-phase result of this numerical data; And
One marginal switch, comprise that one first end is connected in this second end relatively of this bolt-lock unit, one second end is connected in this inverter, and one the 3rd end is connected in this electric capacity, be used for inversion signal size according to this numerical data, this first end of conducting to the signal of the 3rd end links.
23. calibration comparator as claimed in claim 22, it is characterized in that this positive limit switch and this marginal switch are all N type MOS (metal-oxide-semiconductor) transistor, this first end of this positive limit switch or this marginal switch is a drain, and this second end is a gate, and the 3rd end is an one source pole.
24. calibration comparator as claimed in claim 15 is characterized in that this circuit coefficients value is a resistance value, or a capacitance, or the product of a capacitance and a resistance value.
25. calibration comparator as claimed in claim 15 is characterized in that this electric capacity is a metal-oxide semiconductor formula electric capacity.
26. calibration comparator as claimed in claim 15 is characterized in that this controlled capacitance device comprises:
A plurality of electric capacity, each electric capacity comprise one first end, and one second end is connected in this ground end;
A plurality of positive limits switch, each positive limit switch comprise one first end be connected in this bolt-lock unit this first relatively the end, one second end is connected in this numerical data, and one the 3rd end is connected in an electric capacity of these a plurality of electric capacity, be used for signal magnitude according to this numerical data, this first end of conducting to the signal of the 3rd end links;
A plurality of inverters, each inverter are used for producing the anti-phase result of this numerical data; And
A plurality of marginal switches, each marginal switch comprise one first end be connected in this bolt-lock unit this second relatively the end, one second end is connected in this inverter, and one the 3rd end is connected in an electric capacity of these a plurality of electric capacity, be used for inversion signal size according to this numerical data, this first end of conducting to the signal of the 3rd end links.
27. calibration comparator as claimed in claim 26 is characterized in that the capacitance of these a plurality of electric capacity is the binary system proportionate relationship.
28. calibration comparator as claimed in claim 26 is characterized in that these a plurality of electric capacity are all metal-oxide semiconductor formula electric capacity.
29. calibration comparator as claimed in claim 26, it is characterized in that this a plurality of positive limits switch and these a plurality of marginal switches are all N type MOS (metal-oxide-semiconductor) transistor, this first end of each positive limit switch or marginal switch is a drain, and this second end is a gate, and the 3rd end is an one source pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010166645.4A CN102237874B (en) | 2010-04-27 | 2010-04-27 | Analog-to-digital converter and relevant calibration comparer thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010166645.4A CN102237874B (en) | 2010-04-27 | 2010-04-27 | Analog-to-digital converter and relevant calibration comparer thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102237874A true CN102237874A (en) | 2011-11-09 |
| CN102237874B CN102237874B (en) | 2014-05-14 |
Family
ID=44888172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010166645.4A Active CN102237874B (en) | 2010-04-27 | 2010-04-27 | Analog-to-digital converter and relevant calibration comparer thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102237874B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253901A (en) * | 2015-06-11 | 2016-12-21 | 矽创电子股份有限公司 | Analog-digital commutator and relevant calibration steps and calibration module |
| CN108446098A (en) * | 2016-01-04 | 2018-08-24 | 湖南工业大学 | The method for seeking ratio value between two input voltages |
| CN110166050A (en) * | 2018-02-13 | 2019-08-23 | 新唐科技股份有限公司 | Digital background formula correcting circuit |
| CN113552793A (en) * | 2021-07-26 | 2021-10-26 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
| CN114245985A (en) * | 2021-09-17 | 2022-03-25 | 迪克创新科技有限公司 | Comparator, related image sensor and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400302B1 (en) * | 2001-02-26 | 2002-06-04 | Analog Devices, Inc. | Quasi-differential successive-approximation structures and methods for converting analog signals into corresponding digital signals |
| US6608582B2 (en) * | 2001-06-29 | 2003-08-19 | Intel Corporation | A/D conversion using a variable offset comparator |
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
-
2010
- 2010-04-27 CN CN201010166645.4A patent/CN102237874B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400302B1 (en) * | 2001-02-26 | 2002-06-04 | Analog Devices, Inc. | Quasi-differential successive-approximation structures and methods for converting analog signals into corresponding digital signals |
| US6608582B2 (en) * | 2001-06-29 | 2003-08-19 | Intel Corporation | A/D conversion using a variable offset comparator |
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253901A (en) * | 2015-06-11 | 2016-12-21 | 矽创电子股份有限公司 | Analog-digital commutator and relevant calibration steps and calibration module |
| CN106253901B (en) * | 2015-06-11 | 2020-02-21 | 矽创电子股份有限公司 | Analog-digital conversion device and related calibration method and calibration module |
| CN108446098A (en) * | 2016-01-04 | 2018-08-24 | 湖南工业大学 | The method for seeking ratio value between two input voltages |
| CN108446098B (en) * | 2016-01-04 | 2022-03-18 | 湖南工业大学 | Method for calculating proportional value between two input voltages |
| CN110166050A (en) * | 2018-02-13 | 2019-08-23 | 新唐科技股份有限公司 | Digital background formula correcting circuit |
| CN110166050B (en) * | 2018-02-13 | 2023-01-13 | 新唐科技股份有限公司 | Digital background type correction circuit |
| CN113552793A (en) * | 2021-07-26 | 2021-10-26 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
| CN113552793B (en) * | 2021-07-26 | 2022-04-05 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
| CN114245985A (en) * | 2021-09-17 | 2022-03-25 | 迪克创新科技有限公司 | Comparator, related image sensor and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102237874B (en) | 2014-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20110102217A1 (en) | Analog-to-digital Converter and Related Calibrating Comparator | |
| CN102237874B (en) | Analog-to-digital converter and relevant calibration comparer thereof | |
| CN102594353B (en) | Digital-to-analog converter and successive approximation storage converter | |
| Osipov et al. | Two advanced energy-back SAR ADC architectures with 99.21 and 99.37% reduction in switching energy | |
| CN108322199B (en) | Dynamic comparison method | |
| CN113295930B (en) | Micro-watt level micro-capacitance measuring method and circuit | |
| CN112152606B (en) | Interface circuit and electronic device | |
| Rabuske et al. | Charge-Sharing SAR ADCs for low-voltage low-power applications | |
| Bienstman et al. | An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling | |
| Chen et al. | A highly energy-efficient, area-efficient switching scheme for SAR ADC in biomedical applications | |
| De Venuto et al. | Low power 12-bit SAR ADC for autonomous wireless sensors network interface | |
| Chou et al. | A low-glitch binary-weighted DAC with delay compensation scheme | |
| CN106571827B (en) | Differential SAR ADC (synthetic Aperture Radar ADC) and switched capacitor structure, A/D (analog to digital) conversion method and layout implementation method thereof | |
| Shetty et al. | A 14-bit high speed 125ms/s low power SAR ADC using dual split capacitor DAC architecture in 90nm CMOS technology | |
| CN101710827B (en) | Dynamic offset generating circuit for streamline analog-to-digital converter | |
| Wang et al. | Nested-Oversampling Successive Approximation (OSA) Technique for Readout Circuit of MEMS Capacitive Accelerometer | |
| CN106685420A (en) | Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array | |
| Gupta et al. | Implementation of low supply rail-to-rail differential voltage comparator on flexible hardware for a flash ADC | |
| Chaput et al. | An area-efficient 8-bit single-ended ADC with extended input voltage range | |
| Carandang et al. | Development of a low power 8-bit successive approximation register ADC in 90nm process technology for biomedical application | |
| Fan et al. | Capacitor recombination algorithm combined with LMS algorithm in 16-bit SAR ADC with redundancy | |
| Choi et al. | An SRAM-based hybrid computation-in-memory macro using current-reused differential CCO | |
| CN102545907A (en) | Digital-analogue converter | |
| Xiao et al. | A 0.8 µW 8-bit 1.5∼ 20-pF-input-range capacitance-to-digital converter for lab-on-chip digital microfluidics systems | |
| Hu et al. | A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |