CN114245985A - Comparator, related image sensor and electronic device - Google Patents
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Abstract
The application discloses a comparator, a related image sensor and an electronic device. The comparator, which is used for generating a comparator output signal according to the ramp signal and the pixel output signal, comprises: an input stage receiving the ramp signal and the pixel output signal, wherein when the ramp signal changes from being greater than the pixel output signal to being less than the pixel output signal or when the ramp signal changes from being less than the pixel output signal to being greater than the pixel output signal, a first signal output by the input stage changes from a first voltage level to a second voltage level; a gain stage to provide gain to the first signal and output a second signal; an output stage for outputting a third signal according to the second signal; and an arithmetic unit for outputting the comparator output signal according to the second signal and the third signal.
Description
Technical Field
The present disclosure relates to circuits, and particularly to a comparator, and a related image sensor and an electronic device.
Background
With the advance of technology, the CMOS image sensor needs to have a large-scale pixel array and also requires a high signal processing speed, but as the scale of the pixel array increases, the size of a single pixel in the pixel array is continuously reduced, which makes the design of a single analog-to-digital conversion circuit difficult to implement, and thus a column-based analog-to-digital conversion circuit is generated. However, the conventional column analog-to-digital conversion circuit for the CMOS image sensor has a problem of high power consumption due to the fact that the value of the counter is read at any time, and thus how to solve the problem is one of the problems to be solved in the art.
Disclosure of Invention
An objective of the present application is to disclose a comparator, a related image sensor and an electronic device, so as to solve the above problems.
An embodiment of the present application discloses a comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, comprising: an input stage receiving the ramp signal and the pixel output signal, wherein when the ramp signal changes from being greater than the pixel output signal to being less than the pixel output signal or when the ramp signal changes from being less than the pixel output signal to being greater than the pixel output signal, a first signal output by the input stage changes from a first voltage level to a second voltage level; a gain stage to provide gain to the first signal and output a second signal; an output stage for outputting a third signal according to the second signal; and an arithmetic unit for outputting the comparator output signal according to the second signal and the third signal.
An embodiment of the present application discloses a comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, comprising: an input stage receiving the ramp signal and the pixel output signal, wherein when the ramp signal changes from being greater than the pixel output signal to being less than the pixel output signal or when the ramp signal changes from being less than the pixel output signal to being greater than the pixel output signal, a first signal output by the input stage changes from a first voltage level to a second voltage level; a gain stage to provide gain to the first signal and output a second signal; an output stage for outputting a third signal according to the second signal; a replica gain stage to provide gain to the first signal and output a fourth signal; and an arithmetic unit for outputting the comparator output signal according to the fourth signal and the third signal.
An embodiment of the present application discloses an image sensor, including: the pixel array comprises at least one pixel row; an analog-to-digital conversion unit comprising: the comparator is coupled to the at least one pixel row; and at least one latch coupled to the at least one comparator; a row decoder for controlling the at least one pixel column to output the pixel output signal; a ramp signal generating circuit for generating the ramp signal; and a counter for performing a counting operation and outputting a counting result; wherein the at least one comparator generates the comparator output signal to control an enable time of the at least one latch, which continuously latches the count result of the counter when enabled.
An embodiment of the present application discloses an electronic device, including: the image sensor described above.
The comparator, the related image sensor and the electronic device can reduce the power consumption of the column analog-to-digital converter in the image sensor.
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FIG. 1 is a schematic diagram of an embodiment of an image sensor.
Fig. 2 is a schematic diagram of a first embodiment of a comparator according to the present application.
Fig. 3 is an operation timing diagram of the comparator of the present application.
Fig. 4 is a schematic diagram of a second embodiment of the comparator proposed in the present application.
Fig. 5 is a schematic diagram of a third embodiment of the comparator proposed in the present application.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
FIG. 1 is a schematic diagram of an embodiment of an image sensor. The image sensor 100 includes a pixel array 102, an analog-to-digital conversion unit 106, a row decoder 104, a ramp signal generation circuit 108, and a counter 110. The pixel array 102 includes a plurality of pixel rows and a plurality of pixel rows, and the analog-to-digital conversion unit 106 includes a plurality of analog-to-digital conversion circuits correspondingly coupled to the plurality of pixel rows, wherein each of the analog-to-digital conversion circuits includes a comparator and a latch. It should be noted that fig. 1 illustrates a plurality of pixel rows and a plurality of analog-to-digital conversion circuits for illustrative purposes, and the application is not limited thereto, and the image sensor 100 may only include one pixel row and one analog-to-digital conversion circuit.
The row decoder 104 is used for controlling each pixel column in the pixel array 102 to output a pixel output signal, and the counter 110 is used for performing a counting operation and outputting a counting result. Taking the leftmost pixel column of the pixel array 102 and the comparator 1062 and the latch 1064 in the analog-to-digital conversion circuit as an example, the output pixel output signal PXO and the ramp signal Vramp generated by the ramp signal generation circuit 108 are compared by the comparator 1062, and the comparator output signal Scmp is output to control the enabling time of the latch 1064. Since latch 1064 will continuously latch the count result of counter 110 only when enabled. The embodiment of the comparator provided in the present application can reduce the power consumption of the column adc by reducing the enable time of the latch 1064 without affecting the performance of the image sensor 100. The details thereof are explained below.
Fig. 2 is a schematic diagram of a first embodiment of a comparator according to the present application. The comparator 200 is used to generate a comparator output signal Scmp according to the ramp signal Vramp and the pixel output signal PXO, and the comparator 200 may be used to implement all or part of the comparator of fig. 1. Comparator 200 includes an input stage 202, a gain stage 204, an output stage 206, and an arithmetic unit 208.
Referring to fig. 3, fig. 3 is a timing diagram illustrating an operation of the comparator according to the present application. Specifically, the input stage 202 is used as a differential amplifier for receiving the ramp signal Vramp and the pixel output signal PXO, and when the ramp signal Vramp changes from being larger than the pixel output signal PXO to being smaller than the pixel output signal PXO (time T0, not shown), the output signal S1 of the input stage 202 is triggered to fall from the high voltage level to the low voltage level at time T1, and the time T1 is slightly later than the time T0.
The input stage 202 includes an input stage current source 2022, a transistor M1, a transistor M2, a transistor M3, and a transistor M4 to form a differential amplifier, wherein a source of the transistor M1 is coupled to the input stage current source 2022, and a gate of the transistor M1 is used for receiving a ramp signal Vramp. The source of the transistor M2 is coupled to the input stage current source 2022, the gate of the transistor M2 is used for receiving the pixel output signal PXO, and the drain of the transistor M2 is used for outputting the signal S1. The drain and gate of the transistor M3 are coupled to each other, and the drain of the transistor M3 is also coupled to the drain of the transistor M1. The gate of the transistor M4 is coupled to the gate of the transistor M3, and the drain of the transistor M3 is also coupled to the drain of the transistor M2.
Since other possible implementations and variations of the differential amplifier are numerous, detailed description is omitted here, and the implementation of the input stage 202 in the present application is not limited to fig. 2. In addition, the operation timing diagram of fig. 3 may be modified to obtain different aspects, and still fall within the scope of the present application. For example, the ramp signal Vramp may be from bottom to top, such that the signal S1 output by the input stage 202 ramps from a low voltage level to a high voltage level when the ramp signal Vramp changes from being smaller than the pixel output signal PXO to being larger than the pixel output signal.
The gain stage 204 is configured to provide gain to the signal S1 and output a signal S2. The gain stage 204 comprises a gain stage current source 2042 and a transistor M5, wherein the drain of the transistor M5 is coupled to the gain stage current source 2042, the gate of the transistor M5 is configured to receive the signal S1, and the drain of the transistor M5 is further configured to output the signal S2. As shown in fig. 3, when the signal S1 goes from the high voltage level to the low voltage level at time T1, the signal S2 output by the gain stage 204 goes from the low voltage level to the high voltage level at time T2, and time T2 is slightly later than time T1. It should be noted that the implementation of the gain stage 204 in the present application is not limited to fig. 2.
The output stage 206 is used for outputting a signal S3 according to the signal S2. The output stage 206 includes an output stage current source 2062 and a transistor M6, wherein the drain of the transistor M6 is coupled to the output stage current source 2062, the gate of the transistor M6 is used for receiving the signal S2, and the drain of the transistor M6 is also used for outputting the signal S3. As shown in fig. 3, when the signal S2 climbs from a low voltage level to a high voltage level at time T2, the output signal S3 output by the output stage 206 falls from the high voltage level to the low voltage level at time T3, and time T3 is slightly later than time T2. It should be noted that the embodiment of the output stage 206 in the present application is not limited to fig. 2.
The operation unit 208 is used for outputting the comparator output signal Scmp according to the signal S2 and the signal S3. In the present embodiment, the arithmetic unit 208 includes an and gate 2082, and the and gate 2082 is used to and the signal S2 and the signal S3 to obtain the signal Scmp. As shown in fig. 3, the signal Scmp is at a high voltage level between time T2 and time T3, and is at a low voltage level for the rest of the time. It should be noted that the timing diagram in figure 3 does not take into account the delay time of and gate 2082 for ease of illustration.
For the latch 1064, only the counting result of the counter 110 at the moment when the value of the signal Scmp changes needs to be latched, so that when the comparator 1062 of fig. 1 is applied, the comparator 200 of the present application enables the latch 1064 only after the relationship between the ramp signal Vramp and the pixel output signal PXO changes, specifically, enables the latch 1064 only between the time point T2 and the time point T3, and does not need to fixedly enable the latch 1064 before the relationship between the ramp signal Vramp and the pixel output signal PXO changes (for example, the time point Tz). Therefore, the latch 1064 can be prevented from performing an unnecessary latch operation, in other words, power consumption of the column analog-to-digital converter can be reduced.
In the present embodiment, the input stage 202 and the gain stage 204 belong to a first power domain (corresponding to the reference voltages VDD1 and VSS1), and the output stage 206 and the operation unit 208 belong to a second power domain (corresponding to the reference voltages VDD2 and VSS2), wherein the operating voltage of the second power domain is lower than that of the first power domain, i.e., the reference voltage VDD2 is lower than the reference voltage VDD 1. However, the present application is not limited thereto.
Fig. 4 is a schematic diagram of a second embodiment of the comparator proposed in the present application. The difference between comparator 400 and comparator 200 is that comparator 400 additionally adds a replica gain stage 404, and the replica gain stage 404 may be substantially identical in structure to gain stage 204. Specifically, replica gain stage 404 is configured to provide gain to signal S1 and output signal S4. The replica gain stage 404 comprises a replica gain stage current source 4042 and a transistor M7, wherein the drain of the transistor M7 is coupled to the replica gain stage current source 4042, the gate of the transistor M7 is configured to receive the signal S1, and the drain of the transistor M7 is further configured to output the signal S4.
The main function of replica gain stage 404 is to provide signals to the arithmetic unit 208 instead of the gain stage 204, so that the and gate 2082 of fig. 4 and the signal S4 and the signal S3 to obtain the signal Scmp. This has the advantage that the arithmetic unit 208 is not loaded by the gain stage 204, and the influence of the thrust of the signal S2 on the signal S3 output by the output stage 206 is avoided.
In this embodiment, the width-to-length ratio (W/L) of the channel of the transistor M7 is smaller than that of the channel of the transistor M5, so that the ability of the transistor M7 to pull the voltage down is suppressed, and equivalently, the ability of the replica gain stage 404 to pull the voltage up is enhanced, so that the time for the signal S4 to ramp from the low voltage level to the high voltage level is slightly earlier than the time T2 compared to the signal S2, so as to avoid the time for the interval between the time T2 and the time T3 to cause the high voltage level of the comparator output signal mp Scmp to be too short, and thus it is better ensured that the latch 1064 correctly latches the counting result of the counter 110.
Fig. 5 is a schematic diagram of a third embodiment of the comparator proposed in the present application. The difference between comparator 500 and comparator 400 is that replica gain stage 504 of comparator 500 additionally includes transistor M8 as compared to replica gain stage 404. Specifically, the transistor M8 is used as a switch and is connected in series with the transistor M7, for example, the drain of the transistor M8 is coupled to the source of the transistor M7. The gate of the transistor M8 is used to receive the enable signal EN. The difference between the comparator 500 and the comparator 400 is that the operation unit 508 further includes a multiplexer 5084 for outputting the signal S3 or the signal S5 output by the and gate 2082 as the comparator output signal Scmp according to the enable signal EN.
The comparator 500 can be switched between a normal mode and a power saving mode, for example, in the normal mode, the enable signal EN is 0, the transistor M8 is not conductive, and thus the replica gain stage 504 is turned off. The multiplexer 5084 now directly outputs the signal S3 output by the output stage 206 as the comparator output signal Scmp. In the power saving mode, the enable signal EN is 1, and the transistor M8 is turned on, so that the replica gain stage 504 can operate normally and output the signal S4. The and gate 2082 generates a signal S5 according to the signal S4 and the signal S3, and the multiplexer 5084 outputs the signal S5 as the comparator output signal Scmp according to the enable signal EN.
The present application also proposes an electronic device comprising the image sensor 100, wherein the image sensor 100 comprises the comparator 200/400/500. In particular, the electronic apparatus includes, but is not limited to, mobile communication devices, ultra-mobile personal computer devices, portable entertainment devices, and other electronic devices having data interaction functionality. Mobile communication devices are characterized by mobile communication capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others. The ultra-mobile personal computer equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads. The portable entertainment device may display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
When the comparator 200/400/500 of the present application is applied to the comparator 1062 of fig. 1, the latch 1064 is enabled only after the relationship between the ramp signal Vramp and the pixel output signal PXO changes. Therefore, the latch 1064 can be prevented from performing an unnecessary latch operation, in other words, power consumption can be reduced. And comparator 200/400/500 synthesizes comparator output signal Scmp with reference to the signals output by gain stage 204 or replica gain stage 404/504 to minimize the cost and delay time of comparator output signal Scmp.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (19)
1. A comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, comprising:
an input stage receiving the ramp signal and the pixel output signal, wherein when the ramp signal changes from being greater than the pixel output signal to being less than the pixel output signal or when the ramp signal changes from being less than the pixel output signal to being greater than the pixel output signal, a first signal output by the input stage changes from a first voltage level to a second voltage level;
a gain stage to provide gain to the first signal and output a second signal;
an output stage for outputting a third signal according to the second signal; and
and the arithmetic unit is used for outputting the comparator output signal according to the second signal and the third signal.
2. The comparator of claim 1, wherein the input stage comprises a differential amplifier.
3. The comparator as claimed in claim 2, wherein the differential amplifier includes an input stage current source;
a first transistor, a source of the first transistor being coupled to the input stage current source, a gate of the first transistor being used for receiving the ramp signal;
a second transistor, a source of which is coupled to the input stage current source, a gate of which is used for receiving the pixel output signal, and a drain of which is used for outputting the first signal;
a third transistor having a drain and a gate coupled to each other, the drain of the third transistor being further coupled to the drain of the first transistor; and
a fourth transistor, a gate of the fourth transistor being coupled to a gate of the third transistor, a drain of the third transistor also being coupled to a drain of the second transistor.
4. The comparator of claim 1, wherein the gain stage comprises:
a gain stage current source;
a fifth transistor, a drain of the fifth transistor being coupled to the gain stage current source, a gate of the fifth transistor being configured to receive the first signal, and a drain of the fifth transistor being configured to output the second signal.
5. The comparator of claim 1, wherein the output stage comprises:
an output stage current source;
a sixth transistor, a drain of which is coupled to the output stage current source, a gate of which is used for receiving the second signal, and a drain of which is used for outputting the third signal.
6. The comparator of claim 1, wherein the input stage and the gain stage belong to a first power domain, and the output stage and the arithmetic unit belong to a second power domain, wherein an operating voltage of the second power domain is lower than an operating voltage of the first power domain.
7. The comparator according to any one of claims 1 to 6, wherein the arithmetic unit includes:
and the AND gate is used for generating the comparator output signal according to the second signal and the third signal.
8. A comparator for generating a comparator output signal according to a ramp signal and a pixel output signal, comprising:
an input stage receiving the ramp signal and the pixel output signal, when the ramp signal changes from being greater than the pixel output signal to being less than the pixel output signal,
or when the ramp signal is changed from being smaller than the pixel output signal to being larger than the pixel output signal, the first signal output by the input stage is changed from a first voltage level to a second voltage level;
a gain stage to provide gain to the first signal and output a second signal;
an output stage for outputting a third signal according to the second signal;
a replica gain stage to provide gain to the first signal and output a fourth signal; and
and the arithmetic unit is used for outputting the comparator output signal according to the fourth signal and the third signal.
9. The comparator of claim 8, wherein the input stage comprises a differential amplifier.
10. The comparator of claim 9, wherein the differential amplifier comprises an input stage current source;
a first transistor, a source of the first transistor being coupled to the input stage current source, a gate of the first transistor being used for receiving the ramp signal;
a second transistor, a source of which is coupled to the input stage current source, a gate of which is used for receiving the pixel output signal, and a drain of which is used for outputting the first signal;
a third transistor having a drain and a gate coupled to each other, the drain of the third transistor being further coupled to the drain of the first transistor; and
a fourth transistor, a gate of the fourth transistor being coupled to a gate of the third transistor, a drain of the third transistor also being coupled to a drain of the second transistor.
11. The comparator of claim 8, wherein the gain stage comprises:
a gain stage current source;
a fifth transistor, a drain of the fifth transistor being coupled to the gain stage current source, a gate of the fifth transistor being configured to receive the first signal, and a drain of the fifth transistor being configured to output the second signal.
12. The comparator of claim 8, wherein the output stage comprises:
an output stage current source;
a sixth transistor, a drain of which is coupled to the output stage current source, a gate of which is used for receiving the second signal, and a drain of which is used for outputting the third signal.
13. The comparator of claim 11, wherein the replica gain stage comprises:
replicating a gain stage current source;
a seventh transistor, a drain of the seventh transistor being coupled to the replica gainstage current source, a gate of the seventh transistor being configured to receive the first signal, and a drain of the seventh transistor being configured to output the fourth signal.
14. The comparator of claim 8, wherein the input stage, the gain stage, and the replica gain stage belong to a first power domain, the output stage and the arithmetic unit belong to a second power domain, wherein an operating voltage of the second power domain is lower than an operating voltage of the first power domain.
15. The comparator of claim 13, wherein a width-to-length ratio of a channel of the seventh transistor is less than a width-to-length ratio of a channel of the fifth transistor.
16. The comparator according to any one of claims 8 to 15, wherein the arithmetic unit includes:
and the AND gate is used for generating the comparator output signal according to the fourth signal and the third signal.
17. The comparator of claim 13, wherein the replica gain stage further comprises:
an eighth transistor, a gate of the eighth transistor being configured to receive an enable signal, a drain of the eighth transistor being coupled to a source of the seventh transistor; and
the arithmetic unit includes:
the AND gate is used for generating a fifth signal according to the fourth signal and the third signal; and
a multiplexer for outputting the third signal or the fifth signal as the comparator output signal according to the enable signal.
18. An image sensor, comprising:
the pixel array comprises at least one pixel row;
an analog-to-digital conversion unit comprising:
at least one comparator according to any one of claims 1 to 17, coupled to the at least one row of pixels; and
at least one latch coupled to the at least one comparator;
a row decoder for controlling the at least one pixel column to output the pixel output signal;
a ramp signal generating circuit for generating the ramp signal; and
a counter for performing a counting operation and outputting a counting result;
wherein the at least one comparator generates the comparator output signal to control an enable time of the at least one latch, which continuously latches the count result of the counter when enabled.
19. An electronic device, comprising:
the image sensor of claim 18.
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| Publication number | Publication date |
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| CN114245985B (en) | 2024-07-05 |
| WO2023039840A1 (en) | 2023-03-23 |
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