CN215934835U - 16-bit serial input low-power-consumption digital-to-analog converter - Google Patents
16-bit serial input low-power-consumption digital-to-analog converter Download PDFInfo
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Abstract
The utility model relates to a 16-bit serial input low-power-consumption digital-to-analog converter, which comprises a 24-bit serial-to-parallel conversion module, a logic control module, a data buffer module, a register module, a data conversion module and an operational amplifier module, wherein eight pins are arranged at the input end and the output end of the digital-to-analog converter, the digital-to-analog converter adopts a serial data input mode, a Din serial input signal is output to the 24-bit serial-to-parallel conversion module, the 24-bit serial-to-parallel conversion module comprises a shift register, a counter and a digital logic gate, a core in the digital-to-analog conversion module comprises a digital decoding module, and the digital decoding module is used for decoding binary data and translating the binary data into unique corresponding analog quantity. The novel digital-to-analog converter has a low power consumption mode and a flexible serial input interface, rail-to-rail output within a power supply range of 2.7V-5.5V can be realized on each chip, and an external reference voltage is required to set the output range of the digital-to-analog converter.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a 16-bit serial input low-power-consumption digital-to-analog converter.
Background
With the rapid development of technology, integrated circuits are developed towards low power consumption and small size following moore's law, and digital-to-analog converters are a very important class. Digital-to-analog converters are widely used in many places such as computers, mobile phones, earphones and the like, and are used for realizing conversion from digital signals to analog signals, thereby playing a crucial role in various fields and systems.
The resolution is one of the key parameters of the digital-to-analog converter, and the higher the resolution is, the higher the precision of the converter is, so that the digital-to-analog converter is more suitable for chips requiring high-precision operation, and the stronger function is realized. As shown in fig. 1, a conventional digital-to-analog converter generally uses resistors connected in series to divide voltage as input, divides a reference voltage equally, selects a voltage value on a corresponding resistor by inputting different digital signals, and outputs an analog voltage by using an operational amplifier as a buffer. A large number of resistors are required to obtain high resolution, and in practice, too many resistors cause a problem of matching, and a slightly poor matching degree causes a decrease in resolution accuracy. This type of digital-to-analog converter therefore generally limits the resolution to between 6-8 bits, which is difficult to apply in high precision fields.
SUMMERY OF THE UTILITY MODEL
Therefore, the technical problem to be solved by the utility model is to overcome the problem that the precision of the resistor string type DAC in the portable power supply system, the closed loop servo control system, the data acquisition system and the notebook computer is not high, thereby providing the 16-bit serial input low-power digital-to-analog converter.
In order to solve the technical problem, the 16-bit serial input low-power-consumption digital-to-analog converter provided by the utility model comprises a 24-bit serial-to-parallel conversion module, a logic control module, a data cache module, a register module, a data conversion module and an operational amplifier module, wherein eight pins are arranged at the input and output ends of the digital-to-analog converter, and are respectively a VDD power supply, a VREF reference input voltage, a VOUTA output channel A, VOUTB output channel B, SYNC enabling end input, an SCLK clock input signal, a Din serial input signal and GND ground, the digital-to-analog converter adopts a serial data input mode, wherein the Din serial input signal is output to the 24-bit serial-to-parallel conversion module (namely a 24-bit register), the 24-bit serial-to-parallel conversion module comprises a shift register, a counter and a digital logic gate, and the input port of the 24-bit serial-to-parallel conversion module is connected with three pins, the VREF standard input voltage conversion circuit comprises a SYNC enabling end input circuit, a SCLK clock input signal circuit and a Din serial input signal circuit, wherein the output port of the 24-bit serial-to-parallel conversion module is respectively connected with a logic control module and a data cache module, a channel selection end in the logic control module is connected with the data cache module, a core in the data conversion module comprises a digital decoding module, the digital decoding module is used for decoding binary data and translating the binary data into unique corresponding analog quantity, the data conversion module comprises a high-4-bit decoding circuit, a medium-6-bit decoding circuit and a low-6-bit decoding circuit, and one end of the data conversion module receives pin voltage information of VREF standard input voltage.
In an embodiment of the present invention, the shift register includes a counter, and after counting 24 bits each time, the shift register outputs a control signal through a logic circuit in the digital logic gate to control operations of other internal digital modules, thereby implementing data decoding and data conversion processes.
In one embodiment of the present invention, the Din serial input signal inputs serial data in which 24 data are grouped together, i.e., D0 to D23, wherein D0 to D15 are input 16-bit digital bits, and D16 to D23 are 8-bit control bits.
In an embodiment of the present invention, the Din serial input signal D0-D15, i.e. the input 16-bit data bits, may be divided into three groups of data, i.e. high 4 bits, medium 6 bits and low 6 bits, the three groups of data, i.e. high, medium and low, are transmitted to the resistor array in the data conversion module after passing through the register module, and the switch of the resistor array is opened according to the data decoding, so as to obtain the analog voltage corresponding to the data code under the action of the reference voltage.
In one embodiment of the utility model, the high-order 4-bit, medium-order 6-bit and low-order 6-bit decoding circuits in the data conversion module divide the voltage of VREF/2 into 16 × 64 × 64=65536 parts, so that the decoding of analog quantity is realized.
In an embodiment of the present invention, the operational amplifier module is a three-stage operational amplifier, the first stage of the operational amplifier is a folded cascode amplifier stage, the second stage of the operational amplifier is a common-source stage single-stage operational amplifier with negative feedback of a resistor R1, and the third stage is a rail-to-rail output stage.
In an embodiment of the present invention, the operational amplifier module is an operational amplifier applied in a closed loop with twice gain, and the whole circuit decodes the 16-bit binary data and outputs the corresponding analog voltage quantity by the operational amplifier.
Compared with the prior art, the utility model has the advantages that: the novel digital-to-analog converter has a low power consumption mode and a flexible serial input interface. Rail-to-rail output in the 2.7V-5.5V supply range can be achieved on each chip, while an external reference voltage is required to set the output range of the digital-to-analog converter. The power consumption is extremely low during normal operation, can be used for the low-power consumption field, and typical power consumption is only 2.5mW during 5V work, and the mode power consumption of getting off is 1 uW.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.
Fig. 1 is a circuit diagram of a 16-bit serial input low power consumption digital-to-analog converter in a use state.
Fig. 2 is an overall circuit block diagram of a 16-bit serial-input low-power digital-to-analog converter.
Fig. 3 is a schematic diagram of an output operational amplifier of a 16-bit serial-input low-power digital-to-analog converter.
Detailed Description
As shown in fig. 2, this embodiment provides a 16-bit serial input low power consumption digital-to-analog converter, which includes a 24-bit serial-to-parallel conversion module, a logic control module, a data buffer module, a register module, a data conversion module, and an operational amplifier module, where the input and output ends of the digital-to-analog converter are provided with eight pins, which are respectively VDD power supply, VREF reference input voltage, VOUTA output channel A, VOUTB output channel B, SYNC enable input, SCLK clock input signal, Din serial input signal, and GND ground, the digital-to-analog converter adopts a serial data input mode, where the Din serial input signal is output to the 24-bit serial-to-parallel conversion module (i.e., 24-bit register), the 24-bit serial-to-parallel conversion module includes a shift register, a counter, and a digital logic gate, the input port of the 24-bit serial-to-parallel conversion module is connected with three pins, which are respectively SYNC enable input, The output port of the 24-bit serial-to-parallel conversion module is respectively connected with a logic control module and a data cache module, a channel selection end in the logic control module is connected with the data cache module, the core in the data conversion module comprises a digital decoding module, the digital decoding module is used for decoding binary data and translating the binary data into unique corresponding analog quantity, the data conversion module comprises a high 4-bit decoding circuit, a middle 6-bit decoding circuit and a low 6-bit decoding circuit, and one end of the data conversion module receives pin voltage information of VREF reference input voltage.
Furthermore, the SYNC enable input is a level trigger input, the low level is active, and is used for controlling the writing of Din data, when the SYNC input is the high level, the serial-parallel module is in an interrupt holding state, the internal register does not allow data writing, and only holds the last written data. When SYNC jumps from high level to low level, the write function is started, and 24-bit serial data of Din enters the serial-to-parallel module. SCLK is the clock input end, can support the clock input frequency of 30MHz at most, and the falling edge of every clock cycle is valid, supports data write-in, forbids data write-in when the high level. Din is a 24-bit serial data input port, a counter is simultaneously contained in the whole register, and after 24 bits (one counting period) are counted each time, a control signal is output through a logic circuit to control the work of other internal digital modules, so that the data decoding and data conversion processes are realized.
Further, a register in the 16-bit serial input low-power digital-to-analog converter circuit adopts an asynchronous zero clearing mode, and a zero clearing port is effective at a low level. The power-on zero clearing and resetting principle of the upper graph is as follows: after the power supply voltage VDD is electrified, because the voltage of the charging capacitor cannot change suddenly, the output potential of the module keeps a low level for a period of time, and the internal register of the circuit is cleared and reset within a period of time after the power supply voltage VDD is electrified. The length of this period of time is determined by the magnitude of the charge/discharge capacitance and the magnitude of the charge/discharge current, and it is necessary to reduce the charge current or increase the charge capacitance to extend the time of the zero clearing reset, as indicated by C × dV = dI × dT. When VDD is given a step, the output control signal will remain low for a period of time, so that the internal registers of the circuit are cleared and reset during the period of time.
The bias current source inside the circuit is a self-bias current source: the current source internally comprises a starting circuit, so that the second degeneracy point of the circuit can be effectively avoided. The circuit adopts a self-biasing structure irrelevant to power supply voltage, and the expression of output current is as follows:
Iout=2L/μn*COX*W*RS 2 × (1-1/√K)2
therefore, the required current can be adjusted by adjusting the size of the series resistor RS or the proportionality coefficient K of the PMOS mirror tube. And then output through the current sources with equal proportion.
The shift register internally comprises a counter, and after 24 bits are counted each time, a control signal is output through a logic circuit in the digital logic gate to control the work of other internal digital modules, so that the data decoding and data conversion processes are realized.
The Din serial input signal inputs 24 data in total from D0 to D23 as serial data, wherein D0-D15 are input 16-bit digital bits, and D16-D23 are 8-bit control bits. Further, during operation, 16 bit data bits of D0-D15 enter the input buffer module, are transmitted to the register module through the data control end according to control signal information of the D16-D23 logic control module, and finally enter the data conversion module, and unique corresponding voltage is selected and output through the operation module with double gain. The data bits determine the value of the input digital signals, each digital signal has its corresponding analog voltage, and the control bits determine the channel of data transmission and the operating mode of the circuit.
D0-D15 in the Din serial input signal, namely, the input 16-bit data bit can be divided into three groups of data including high 4 bits, middle 6 bits and low 6 bits, the high, middle and low three groups of data are transmitted to a resistor array in a data conversion module after passing through a register module, a switch of the resistor array is opened according to data decoding, and analog voltage corresponding to a data code is obtained under the action of reference voltage.
The high-order 4-bit, medium-order 6-bit and low-order 6-bit decoding circuits in the data conversion module divide VREF/2 into 16 × 64 × 64=65536 parts, and decoding of analog quantity is achieved.
Further, as shown in fig. 1, in the 16 segments of the resistor array module, VREF/2 is divided into 16 parts by equal 16 segments of segmented resistors, so as to form a high 4-bit voltage selection, and then resistance division is performed in each voltage difference to form 64 step voltages, so as to form medium 6-bit voltage data, and one of the step voltages is selected by medium 6-bit data. The high 4-bit decoder is a 1-out-of-16 decoder, the output is normally low, and only the selected bit is normally high. The high level of the output can turn on the corresponding NMOS tube switch, and a certain equal voltage (containing 16 step voltages) in the 16 segmented electronic array is selected. When the input is incremented in binary (0000- > 1111), the output code bits sequentially output '1' from low to high.
The middle 6-bit decoder is a 64-to-1 decoder, the output of the decoder is a switch array formed by MOS (metal oxide semiconductor) tubes, the switch array has 64 groups of switches, and each group of switches corresponds to one of 64 step voltages. After each data decoding, a unique corresponding switch array signal is output, two adjacent switches are opened, and a selected step voltage (comprising high and low analog voltages) is output. When the input is increased in binary (000000- > 111111), the code bit of the output switch sequentially opens two adjacent switches and outputs the high and low analog voltages of the step voltage (if VREF =5V, the voltage difference of each step is about 2.4mV, namely the difference between the high and low analog voltages is 2.4 mV).
The lower 6-bit decoder is a 64-bit thermometer decoder, and the high level is active. The 64 thermometers decode and output to control the right 64 differential input pair switch arrays with the same tail current source, the negative port of each differential input pair is connected with the common feedback end (the feedback of the output end of the operational amplifier), the positive port is connected with the 64 switch arrays, and the voltage transmitted by each switch is the high-low analog voltage of the step voltage difference. The higher the symbol input is, the more the thermometer decoder outputs the active high level, the more channels of the switch array select the analog high voltage, so that the input voltage of the overall differential input end is closer to the analog high voltage, and the step voltage difference is subdivided into 64 parts again. When the input is incremented in binary (000000- > 111111), the more active high levels the thermometer decoder outputs, the more analog high voltages in the 64 selected switch arrays, and the larger the voltage at the differential pair input.
As shown in fig. three, the operational amplifier module is a three-stage operational amplifier, the first stage of the operational amplifier is a folding cascode amplifier stage, the second stage of the operational amplifier is a common-source stage single-stage operational amplifier with negative feedback of a resistor R1, and the third stage is a rail-to-rail output stage.
Furthermore, since the operational amplifier output end needs to drive a large current load and the power consumption of the whole circuit is small, the MOS transistor of the third-stage output stage needs to set a small bias current. In order to ensure that a large-area NMOS tube of an output stage works in a saturation region, the bias current of an output power tube is set to be 90uA through the structure of a transconductance linear ring, the output power tube is ensured to be in the saturation region, and meanwhile, the amplification and low power consumption performance are considered. If the gain of the operational amplifier is high, so that the operational amplifier works in deep negative feedback, the relationship between the output voltage Vout and the input step voltage Vin is as follows: vout =2 Vin.
The operational amplifier module is an operational amplifier applied by a double-gain closed loop, the whole circuit decodes the 16-bit binary data, and then the operational amplifier outputs a corresponding analog voltage quantity, which is specifically as follows:
Vout=Vin×2 =｛[（VREF/2）*D]/65536｝×2=VREF*D/65536
meanwhile, the stability of the loop of the closed-loop operational amplifier system is considered.
Because the operational amplifier is a three-stage amplification structure and works in a closed-loop mode, higher requirements are put on the stability of a loop. In order to maintain the stability of the system, a Miller compensation capacitor and a loop feedback compensation capacitor are added internally to ensure the stability of the closed-loop system.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the utility model may be made without departing from the spirit or scope of the utility model.
Claims (7)
1. A16-bit serial input low-power digital-to-analog converter comprises a 24-bit serial-parallel conversion module, a logic control module, a data buffer module, a register module, a data conversion module and an operational amplifier module, and is characterized in that: the input and output ends of the digital-to-analog converter are provided with eight pins which are respectively a VDD power supply, a VREF reference input voltage, a VOUTA output channel A, VOUTB output channel B, SYNC enable end input, an SCLK clock input signal, a Din serial input signal and GND ground, the digital-to-analog converter adopts a serial data input mode, wherein the Din serial input signal is output to a 24-bit serial-to-parallel conversion module, the 24-bit serial-to-parallel conversion module comprises a shift register, a counter and a digital logic gate, the input port of the 24-bit serial-to-parallel conversion module is connected with three pins which are respectively a SYNC enable end input, an SCLK clock input signal and a Din serial input signal, the output port of the 24-bit serial-to-parallel conversion module is respectively connected with a logic control module and a data buffer module, and the channel selection end in the logic control module is connected with the data buffer module, the core in the data conversion module comprises a digital decoding module, the digital decoding module is used for decoding binary data and translating the binary data into unique corresponding analog quantity, the data conversion module comprises a high-4 bit decoding circuit, a medium-6 bit decoding circuit and a low-6 bit decoding circuit, and one end of the data conversion module receives pin voltage information of VREF reference input voltage.
2. The 16-bit serial-input low-power digital-to-analog converter according to claim 1, wherein: the shift register internally comprises a counter, and after 24 bits are counted each time, a control signal is output through a logic circuit in the digital logic gate to control the work of other internal digital modules, so that the data decoding and data conversion processes are realized.
3. The 16-bit serial-input low-power digital-to-analog converter according to claim 1, wherein: the Din serial input signal inputs 24 data in total from D0 to D23 as serial data, wherein D0-D15 are input 16-bit digital bits, and D16-D23 are 8-bit control bits.
4. The 16-bit serial-input low-power digital-to-analog converter according to claim 3, wherein: D0-D15 in the Din serial input signal, namely, the input 16-bit data bit can be divided into three groups of data of high 4 bits, medium 6 bits and low 6 bits, the three groups of data of high, medium and low are transmitted to a resistor array in a data conversion module after passing through a register module, a switch of the resistor array is opened according to data decoding, and analog voltage corresponding to binary data codes is obtained under the action of reference voltage.
5. The 16-bit serial-input low-power digital-to-analog converter according to claim 1, wherein: the high-order 4-bit, medium-order 6-bit and low-order 6-bit decoding circuits in the data conversion module divide VREF/2 into 16 × 64 × 64=65536 parts, and decoding of analog quantity is achieved.
6. The 16-bit serial-input low-power digital-to-analog converter according to claim 1, wherein: the operational amplifier module is a three-stage operational amplifier, the first stage of the operational amplifier is a folding cascode amplifier stage, the second stage of the operational amplifier is a common-source stage single-stage operational amplifier with a resistor R1 negative feedback, and the third stage is an output stage from a rail to a rail.
7. The 16-bit serial-input low-power digital-to-analog converter according to claim 6, wherein: the operational amplifier module is an operational amplifier applied by a double-gain closed loop, and the whole circuit outputs corresponding analog voltage quantity by the operational amplifier after decoding 16-bit binary data.
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| CN116401199A (en) * | 2023-06-09 | 2023-07-07 | 珠海智融科技股份有限公司 | Signal conversion circuit, transmission method, device, electronic apparatus, and storage medium |
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| CN116401199A (en) * | 2023-06-09 | 2023-07-07 | 珠海智融科技股份有限公司 | Signal conversion circuit, transmission method, device, electronic apparatus, and storage medium |
| CN116401199B (en) * | 2023-06-09 | 2024-03-05 | 珠海智融科技股份有限公司 | Signal conversion circuit, transmission method, device, electronic apparatus, and storage medium |
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