CN102237874B - Analog-to-digital converter and relevant calibration comparer thereof - Google Patents
Analog-to-digital converter and relevant calibration comparer thereof Download PDFInfo
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Abstract
The invention relates to a successive approximation type analog-to-digital converter, in particular to a successive approximation type analog-to-digital converter which can be used for greatly lowering the power consumption and reducing the utilization area of a chip. The successive approximation type analog-to-digital converter comprises a sample-and-hold unit, an approximation control unit, a search memory and a calibration comparer, wherein the calibration comparer comprises a positive input end, a negative input end, a time sequence signal input end, a digital data port, a bolt-lock unit, a starting switch, a first controllable variable resistor, a second controllable variable resistor, a reset switch module, a controllable-capacitance device and an output end.
Description
Technical field
The present invention relates to a kind ofly simulate to digital quantizer and relevant calibration comparator thereof for a successive approximation, relate to especially a kind of power consumption and successive approximation that reduces chip usable floor area of can significantly reducing and simulate to digital quantizer and relevant calibration comparator thereof.
Background technology
Analog-to-digital converter (Analog to Digital Converter) can be converted to numerical data by the simulating signal in real world, then transfers to digital signal processing device processing.Along with science and technology is increasingly universal, many products all possess multimedia function, for example, the compression of image and voice signal or identification, just must comprise the simulating signal of image and sound, is converted to numerical data via analog-to-digital converter, then export to digital signal processor, carry out the computing of data, then be stored in numerical data memory mechanism, or via Internet communication.In addition, the use of all types of sensing components, for example, digital clinical thermometer utilizes temperature sensor exactly, produces the temperature signal of simulation, via analog-to-digital converter, temperature signal is changed into digital pattern, in addition computing, correction and demonstration.In addition,, in fields such as medical science, communication and controls, the use of analog-to-digital converter is also more and more frequent, almost can be described as omnipresent.Wherein, successive approximation is simulated to digital quantizer (Successive Approximation Analog to Digital Converter, referred to as SAR ADC) be a kind of common custom design of analog-to-digital converter, be common in that sampling frequency belongs to medium data volume or compared with the application of low speed.
Please refer to Fig. 1, Fig. 1 is that in known technology, a successive approximation is simulated to the schematic diagram of digital quantizer 10.Analog-to-digital converter 10 comprises a sample-and-hold circuit 100, a comparer 102, approaches calculation control module 104 and a digital to analog converter 106.The mode of operation of analog-to-digital converter 10 is as follows, and first, sample-and-hold circuit 100 is by an input signal VIN sampling and maintain a sampling voltage VSIN.Comparer 102 is relatively inputted the size of sampling voltage VSIN and an analog voltage VCOM, and its comparative result is outputed to and approaches calculation control module 104.Approach the comparative result that calculation control module 104 is exported according to comparer 102, produce a numerical data DK, digital to analog converter 106 is converted to analog voltage VCOM by numerical data DK, and outputs to comparer 102.
In analog-to-digital converter 10, approach calculation control module 104 according to the comparative result of comparer 102, once to produce the mode of a significance bit, successively produce and there is the numerical data DK of multiple significance bits, make analog voltage VCOM that digital to analog converter 106 produces level off to sampling voltage VSIN.Circulation according to this, until produce all significance bits.Generally speaking, the number of significance bit is relevant with the precision of analog-to-digital converter 10, and the more, conventionally precision is just higher for the number of significance bit, and above-mentioned numeral to the cycle index of analog-converted and comparison procedure also just the more.
But, traditional successive approximation simulate to digital quantizer must possess one independently numeral to analog-converted (DAC) unit, thereby derive some technical difficulty, after Will Details is set forth in.Please refer to Fig. 2, Fig. 2 one simulates take seven (7-bit) as the capacitor charging-successive approximation of example to the schematic diagram of digital quantizer (Charge-Redistribution SAR ADC) 20.Analog-to-digital converter 20 comprises a sample-and-hold circuit 200 (in this figure without indicate), a comparer 202, approaches calculation control module 204, a numeral to analog-converted unit 206 and a reference voltage output unit 208.The framework of analog-to-digital converter 20 and function mode are 10 1 kinds of special and common patterns of analog-to-digital converter, and special character is that analog-to-digital converter 20 utilizes a kind of technology of charge redistribution, reach the function of numeral to analog-converted.In addition, numeral, to analog-converted unit 206, is formed by capacitor C 1～C7 and the contactor S0～S7 with different capacitances.Due in the time that the end points of capacitor C 1～C7 is positioned at same voltage, capacitance determines to store the quantity of electric charge, therefore numeral needs to have proportionate relationship accurately between the capacitance of the included different electric capacity in analog-converted unit 206, and then can make the stored amount of charge of capacitor C 1～C7, and the Mo that numeral is exported to analog-converted unit 206 intends the raw enough accuracys of electricity Ya Productivity.Therefore, the amount of charge of capacitor C 1～C7 must be very good with respect to the linearity of voltage, to obtain accurate simulation to digital conversion results, and metal-insulator-metal type (Meta1-Insulator-Metal, MIM) electric capacity just meets above-mentioned condition.In known semiconductor technology, with the electric capacity of metal-insulator-metal type institute construction, its amount of charge is good far beyond metal-oxide semiconductor electric capacity (MOS Capacitor) with respect to the linearity of voltage.But, unit-area capacitance value approximately 1～2 (the fF/ μ m of metal-insulator-metal capacitor
2), much smaller than unit-area capacitance value (the about 7fF/ μ m of metal-oxide semiconductor electric capacity
2).In other words,, with respect to same capacitance, metal-insulator-metal capacitor need possess the chip area of large several times.But the linearity of metal-oxide semiconductor electric capacity, not as metal-insulator-metal capacitor, is not therefore used in the design of analog-to-digital converter 20.
In addition, no matter be the particular architectures of framework or the analog-to-digital converter 20 of analog-to-digital converter 10, numeral wherein to analog-converted unit 206 all needs to use reference voltage output unit 208 that reference voltage VREF is provided.Show that according to experimental result the electric power that reference voltage output unit 208 is spent accounts for greatly the half of overall analog-digital converter 20 spent electric power.But numeral is analog-to-digital converter 20 indispensable parts while operating to analog-converted unit 206, therefore spent a large amount of electric power can not be exempted.Meanwhile, because the power consumption of reference voltage output unit 208 is larger, analog-to-digital converter 20 also needs to expend larger electric energy to maintain its normal operation.
Summary of the invention
Therefore, the present invention proposes a kind of successive approximation and simulates to digital quantizer and relevant calibration comparator thereof.
The present invention discloses an a kind of analog-to-digital converter of saving electrical source consumption, comprises a sampling keeping unit, is connected in an external differential input signal, according to a sampling frequency signal, and sampling, maintenance and output one differential sampled signal; One approaches control module, is connected in this calibration comparator, according to the comparative result of this comparer, and output one memory address, and in simulating while completing to digital conversion, output one transformation result; One searches internal memory, is connected in this calibration comparator and this approaches control module, and according to this memory address, output one numerical data is to the plurality of numerical data input port of this calibration comparator; An and calibration comparator, be connected in this sampling keeping unit, this approaches control module and this searches internal memory, relatively this differential sampled signal and a built-in equivalent drift voltage, output one comparative result, comprise a positive input terminal, be used for receiving a forward signal of a differential sampled signal; One negative input end, is used for receiving a negative-going signal of this differential sampled signal; One clock signal input end, is used for receiving a clock signal; One digital data port, is used for receiving a numerical data; One bolt-lock unit, comprise one first relatively end, one second relatively end, one first output terminal and one second output terminal, be used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output terminal and this second output terminal; One starting switch, comprises a first end, and one second end is connected in this clock signal input end, and one the 3rd end is connected in a ground end, is used for according to the size of this clock signal, controls this first end to the signal of the 3rd end and links; One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for according to this forward signal of this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch; One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for according to this negative-going signal of this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch; One Resetting Switching module, is connected in this clock signal input end and this bolt-lock unit, is used for, according to the size of this clock signal, controlling the state of this bolt-lock unit; One controlled capacitance device, is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And an output terminal, be connected in this first output terminal of this bolt-lock unit, be used for exporting a comparative result.
The another exposure of the present invention is a kind of simulates the calibration comparator to digital quantizer for a successive approximation, comprises a positive input terminal, is used for receiving a forward signal of a differential sampled signal; One negative input end, is used for receiving a negative-going signal of this differential sampled signal; One clock signal input end, is used for receiving a clock signal; One digital data port, is used for receiving a numerical data; One bolt-lock unit, comprise one first relatively end, one second relatively end, one first output terminal and one second output terminal, be used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output terminal and this second output terminal; One starting switch, comprises a first end, and one second end is connected in this clock signal input end, and one the 3rd end is connected in a ground end, is used for according to the size of this clock signal, controls this first end to the signal of the 3rd end and links; One first controlled variable resistor, be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit, be used for according to this forward signal of this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch; One second controlled variable resistor, be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit, be used for according to this negative-going signal of this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch; One Resetting Switching module, is connected in this clock signal input end and this bolt-lock unit, is used for, according to the size of this clock signal, controlling the state of this bolt-lock unit; One controlled capacitance device, is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And an output terminal, be connected in this first output terminal of this bolt-lock unit, be used for exporting a comparative result.
Accompanying drawing explanation
Fig. 1 is that in known technology, a successive approximation is simulated the schematic diagram to digital quantizer.
Fig. 2 is that in known technology, one capacitor charging-successive approximation is simulated the schematic diagram to digital quantizer.
Fig. 3 A is that a successive approximation according to the present invention is simulated the Knot structure schematic diagram to digital quantizer.
Fig. 3 B is that a successive approximation according to the present invention is simulated to the schematic diagram of digital quantizer alignment module.
Fig. 3 C is one according to calibration comparator Knot structure schematic diagram of the present invention.
Fig. 4 is the embodiment schematic diagram of the calibration comparator of a single position.
Fig. 5 A is the embodiment schematic diagram of the calibration comparator of one or two.
Fig. 5 B is the embodiment schematic diagram of the calibration comparator of a multidigit.
Wherein, description of reference numerals is as follows:
10,20 analog-to-digital converter 102,202 comparers
100 sample-and-hold circuits 104,204 approach calculation control module
106,206 digital to analog converters
208 reference voltage output unit
30 calibration comparators
300 Resetting Switching module 302 starting switches
304 bolt-lock unit 306 first controlled variable resistors
308 second controlled variable resistor 310 controlled capacitance devices
312 digital data port 314 clock signal input ends
60 analog-digital converters
600 sampling keeping units 602 approach control module
604 search internal memory
70 calibration modules
700 standard voltage source 702 voltage-selected switches
704 controller calibration 706 counters
708 internal memories
IN_P positive input terminal IN_N negative input end
Scale value VB voltage subscript value on VA voltage
CT1 first relatively holds CT2 second relatively to hold
OP1 first output terminal OP2 the second output terminal
VCC power supply GND ground end
R_1～R_K resistance
C1～C7 electric capacity
S0～S7 contactor
INV1 first phase inverter INV2 the second phase inverter
VD_1～VD_N, SVD normal voltage
EOV equivalent drift voltage
CU_1～CU_N controlled capacitance sub-cell
MP1～MP6, MP_N1 PMOS crystal
Pipe
MN1～MN9, MN_N1 nmos pass transistor
The marginal switch of the positive limit of SP_1～SP_N switch S N_1～SN_N
INV_1～INV_N phase inverter CC_1～CC_N electric capacity
VIN input signal VSIN sampling voltage
VCOM analog voltage CLK clock signal
DK, D numerical data
D_1～D_N bit data
The anti-phase letter of YD_1～YD_N D_1～D_N
Number
Embodiment
Analog-to-digital converter in known technology must adopt the electric capacity with the construction of metal-insulator-metal type institute, causes chip area to increase.Trace it to its cause, in fact by the restriction on the analog-to-digital converter framework in known technology is caused.Wherein, topmost reason is that known technology must adopt the electric capacity that voltage is good with respect to the electric charge linearity, otherwise simulation to digital transformation result just has sizable error.In addition, the existence of reference voltage VREF, also makes the analog-to-digital converter power consumption in known technology larger.
Described in summary of the invention of the present invention, object of the present invention is to provide a successive approximation to simulate the brand-new framework to digital quantizer, use a calibration mode and method, successive approximation is simulated to digital quantizer and can adopt the poor electric capacity of the linearity, and do not affect the degree of accuracy of transformation result.And brand-new framework of the present invention uses as the reference voltage VREF in known technology because not needing, thereby can make the problem that power consumption is large be resolved in the lump.For convenience of clear statement method of operating of the present invention and embodiment thereof, by implementation method of the present invention, principle and formation important document, be described in down:
Please refer to Fig. 3 A, Fig. 3 A is that a successive approximation of the present invention is simulated to the configuration diagram of digital quantizer 60.Analog-digital converter 60 comprises that a sampling keeping unit 600, approaches control module 602, and searches internal memory 604 and calibration comparator 30.Wherein, sampling keeping unit 600, according to a sampling frequency signal (nothing indicates in this figure), receives an outside input differential wave VIN, is sampled, and becomes differential sampled signal VSIN, and is sent to calibration comparator 30.Approach control module 602 and be connected in calibration comparator 30 and search internal memory 604, be used for the running of control simulation to digital quantizer 60.Approach control module 602 according to the comparative result COMP of comparer, one memory address ADDR is to searching internal memory 604 in output, and in the time that simulation to digital action all completes, the transformation result to digital conversion is simulated in output.In addition, search internal memory 604 and be connected in calibration comparator 30 and approach control module 602, according to the memory address ADDR that approaches control module 602 and give, one numerical data D is to calibration comparator 30 in output.
For providing analog-to-digital converter 60 suitable calibration function, must an additional calibration module.Please refer to Fig. 3 B, Fig. 3 B is the schematic diagram for a calibration module 70 of successive approximation simulation digital quantizer 60.Calibration module 70 operates in calibration mode.Wherein, calibration module 70 comprises a standard voltage source 700, a voltage-selected switch 702, a controller calibration 704, a counter 706 and an internal memory 708.In the time that analog-digital converter 60 enters calibration mode operation, standard voltage source 700 is used between scale value VA and a voltage subscript value VB, providing the normal voltage VD_1～VD_N of some on a voltage.Preferably, these normal voltages are evenly distributed on voltage between scale value VA and voltage subscript value VB, its embodiment is resistance in series R_1～R_K, wherein one end is connected in scale value VA on voltage, the other end is connected in voltage subscript value VB, between resistance and resistance, can be connected required normal voltage VD_1～VD_N.Voltage-selected switch 702 is connected in standard voltage source 700, is used for from above-mentioned normal voltage VD_1～VD_N, selects a normal voltage SVD wherein to export calibration comparator to.Counter 706 is connected in calibration comparator 30, is used to provide numerical data DD.This numerical data DD is used for adjusting an equivalent drift voltage EOV (about equivalent drift voltage EOV, please readding in detail following explanation).Preferably, in the time that voltage-selected switch 702 is connected in a new normal voltage VD_1～VD_N, counter 706 starts up to count or start down to count from maximal value from minimum value, is used for according to the comparative result of calibration comparator 60, determines whether counter 706 should continue counting.In the time that comparative result display standard magnitude of voltage and equivalent drift voltage EOV equate (in fact, only can judge reach the most approaching equate or inferiorly approach equal state), counter 706 stops counting, and is connected to next normal voltage.
In addition, in Fig. 3 B, internal memory 708 is connected in counter 706 and voltage-selected switch 702, be used in the time that calibration comparator 30 shows that equivalent drift voltage EOV equates with standard voltage value, the count value of counter 706 now of record and standard voltage value in internal memory 708 index value or the numbering of standard voltage value (or corresponding to).Preferably, internal memory 708 is searched internal memory 704 for what share with analog-to-digital converter 60.For example, have N normal voltage VD_1～VD_N, in the time that calibration completes, internal memory 708 should have N data.In addition, controller calibration 704 is connected in voltage-selected switch 702, counter 706 and internal memory 708, is used for according to the comparative result of calibration comparator 30, controls the action of voltage-selected switch 702, counter 706 and internal memory 708.In the time that voltage-selected switch 702 is connected to a new normal voltage VD_1～VD_N, controller calibration 704 command counters 706 restart counting.In the time that calibration comparator 30 shows that equivalent drift voltage EOV and standard voltage value reach the most approaching or inferior approaching state, controller calibration 704 order internal memories 708 record the count value of standard voltage value now one index value or the numbering of standard voltage value (or corresponding to) and counter 706, until all normal voltage VD_1～VD_N calibrate end.
After successive approximation simulation digital quantizer alignment module 70 completes calibration actions, the present invention will be converted to the normal manipulation mode of the analog-to-digital converter 60 in Fig. 3 A automatically.Wherein, about surely belonging to this area tool general knowledge person, required modulation control (Switching Control) circuit of the conversion of data routing between calibration mode and normal manipulation mode (Data Path) knows, and be achieved according to above-listed description, therefore do not repeat or express in figure.
About the thin portion structure of calibration comparator 30, please refer to Fig. 3 C, Fig. 3 C is depicted as the schematic diagram of one of embodiment of the present invention calibration comparator 30.Calibration comparator 30 comprises a positive input terminal IN_P, a negative input end IN_N, a clock signal input end 314, a digital data port 312, a Resetting Switching module 300, a starting switch 302, a bolt-lock unit 304, one first controlled variable resistor 306, one second controlled variable resistor 308 and a controlled capacitance device 310.Positive input terminal IN_P and negative input end IN_N are used for respectively receiving the positive and negative to signal of differential sampled signal.Preferably, outside input differential wave VIN is after sampling, become differential sampled signal VSIN, the positive phase signals of differential sampled signal VSIN is connected in the positive input terminal IN_P of calibration comparator 30, and the negative signal of differential sampled signal VSIN is connected in the negative input end IN_N of calibration comparator 30; In addition, also normal voltage SVD can be exported to the positive input terminal IN_P of calibration comparator for the voltage-selected switch 702 of calibration mode, and by the negative input end IN_N ground connection of calibration comparator, the voltage standard that calibration comparator is used when as calibration.Secondly, clock signal input end 314 is used for receiving a clock signal CLK, as the sequential benchmark of controlling calibration comparator 30.Digital data port 312 is used for receiving a numerical data D, and it comprises the N such as D_1～D_N position.Bolt-lock unit 304 comprises that one first relatively holds CT1, one second relatively to hold CT2, one first output terminal OP1 and one second output terminal OP2, be used for the difference that comparison first relatively holds CT1 and second relatively to hold CT2 circuit numerical value, to determine the state value of the first output terminal OP1 and the second output terminal OP2.Starting switch 302 is used for according to the voltage of clock signal CLK, controls the first controlled variable resistor 306 and the second controlled variable resistor 308 to the signal between ground end and links, to start comparison.The first controlled variable resistor 306 and the second controlled variable resistor 308 are connected to positive input terminal IN_P and the negative input end IN_N of differential sampled signal, be used for according to the forward signal of differential sampled signal and negative-going signal, adjust respectively first and relatively hold CT1 and second relatively to hold CT2 to the resistance value between starting switch 302.Resetting Switching module 300 is used for according to the size of clock signal CLK, controls the state of bolt-lock unit 304.Preferably, in the time that clock signal CLK arrives a default voltage (an in this case low-voltage), Resetting Switching module 300 relatively holds CT1, second relatively to hold the voltage of the end points such as CT2, the first output terminal OP1 and the second output terminal OP2 by first, is refitted in the magnitude of voltage that approaches power supply VCC.Controlled capacitance device 310 is connected in first and relatively holds CT1, second relatively to hold CT2 and ground end GND, is used for according to numerical data D, controls the first capacitance of relatively holding CT1 and second relatively to hold CT2 extremely to hold.In addition, it should be noted that deviser can select to export a comparative result by the first output terminal OP1 or the second output terminal OP2.Please refer to Fig. 3 C, Fig. 3 C utilizes the first output terminal OP1 to export comparative result COMP.And preferably, the first controlled variable resistor 306 and the second controlled variable resistor 308 are N-type MOS (metal-oxide-semiconductor) transistor (NMOS).
In simple terms, Resetting Switching module 300 conducting in the time of clock signal CLK electronegative potential, makes first relatively to hold CT1, second relatively to hold CT2, the first output terminal OP1 and the second output terminal OP2 all to draw high noble potential, with the action of the bolt-lock unit 304 of resetting.Starting switch 302 is controlled by clock signal CLK also, different from Resetting Switching module 300, and starting switch 302 conducting in the time of clock signal CLK noble potential, in order to start the comparison of calibration comparator 30.In addition, bolt-lock unit 304 relatively first relatively holds CT1 and second relatively to hold the difference of CT2 circuit coefficients value, preferably can be the gap of difference, the difference of capacitance or the product of resistance value and capacitance of resistance value.In the time that calibration comparator 30 starts, first input end CT1 is refitted in identical voltage (approximating power supply VCC) with the second input end CT2, but, because the difference of the circuit coefficients of first input end CT1 and the second input end CT2, the voltage that impels first input end CT1 and the second input end CT2 with different speed to low-voltage convergence.Wherein, one end that the product of resistance value and capacitance is larger, its speed to low-voltage convergence is slower.Otherwise, smaller one end of product of resistance value and capacitance, velocity of approach is very fast.Relatively hold CT1 and second relatively to hold the velocity of approach difference at the two ends such as CT2 due to first, can make bolt-lock unit 304 toward different steady state (SS) convergences.For example, first relatively holds the speed of CT1 to low-voltage convergence, reaches while stablizing in bolt-lock unit 304 states, and the first output terminal OP1 is high voltage, and second relatively to hold CT2 be low-voltage.Otherwise, if second relatively hold the speed of CT2 to low-voltage convergence, reaching while stablizing in bolt-lock unit 304 states, the first output terminal OP1 is low-voltage, and second relatively to hold CT2 be to be high voltage.Preferably, because the output terminal of calibration comparator 30 is connected in the first output terminal OP1.Finally, the comparative result of calibration comparator 30 is exactly the steady-state voltage value of the first output terminal OP1.
Therefore,, by the controlled variable resistor 306 of differential sampled signal control first and the second controlled variable resistor 308, the present invention can control respectively the resistance value of first input end CT1 and the second input end CT2.Meanwhile, the numerical data D being received by digital data port 312, controls controlled capacitance device 310, and then controls respectively the capacitance of first input end CT1 and the second input end CT2.Finally, by comparing first input end CT1 and the resistance value of the second input end CT2 and the product size of capacitance, determine the output voltage of calibration comparator 30.In addition, in the time that the resistance value of first input end CT1 and the second input end CT2 is individually fixed in certain value, also can be by only adjusting its other capacitance to determine the comparative result of calibration comparator 30; Or, when the capacitance of first input end CT1 and the second input end CT2 is individually fixed in to certain value, also can be by adjusting separately its other resistance value to determine the comparative result of calibration comparator 30.
Such as the present invention can, by fixing differential sampled signal, make the resistance value of first input end CT1 and the second input end CT2 be individually fixed in certain value.Meanwhile, the numerical data D being received by digital data port 312, controls controlled capacitance device 310, progressively changes first and relatively holds CT1 relatively to hold the capacitance of CT2 with respect to second, and read successively the comparative result of calibration comparator 30., in the time that the comparative result of calibration comparator 30 shows that the circuit coefficients of first input end CT1 and the second input end CT2 is the most approaching or inferior approaching state, record the corresponding relation between differential sampled signal and numerical data D.Preferably, any one the numerical data D in this corresponding relation, can be used to corresponding to a normal voltage.Thus, the present invention can utilize this phenomenon, by calibration comparator 30 is carried out to calibration actions.About calibrating mode and the device of calibration comparator 30, will be in hereinafter describing in detail.
It should be noted that the numerical data being received by digital data port 312, control controlled capacitance device 310, can be considered in first and relatively hold CT1 and second relatively to hold between CT2, produce a corresponding magnitude of voltage.The present invention claims this because the corresponding voltage difference of imbalance is for " equivalent drift voltage " (EquivalentOffset Voltage) EOV.The phenomenon of a kind of Voltage unbalance of former two input ends that betided before this general operation amplifier of equivalent drift voltage EOV, this energy imbalance is generally led due to the error because producing in circuit design or chip manufacturing.The present invention utilizes the energy imbalance that artificially deliberately causes two inlet circuit coefficients, produces a voltage differences in the input end of calibration comparator 30, and the comparison signal size that is used.Therefore, calibration comparator 30 also can be considered the device in order to more differential sampled signal and equivalent drift voltage EOV.Preferably, in the time that differential sampled signal is greater than equivalent drift voltage EOV, the comparative result of calibration comparator 30 is a high voltage (logical value is 1); Otherwise in the time that differential sampled signal is less than equivalent drift voltage EOV, the comparative result of calibration comparator 30 is a low-voltage (logical value is 0).
In brief, the numerical data that calibration comparator 30 is received by voltage and the digital data port 312 of positive input terminal IN_P and negative input end IN_N, determines the steady state (SS) of bolt-lock unit 304, and as the comparative result of calibration comparator 30.Calibration comparator 30 both can be used for converting a stroke numeral data D to an equivalent drift voltage EOV, was used for doing with an external voltage comparison of voltage swing.In addition, also can be by changing numerical data D, for a normal voltage, the work of calibrating, obtains the corresponding equivalent drift voltage EOV of numerical data D.
Should be noted, the embodiment schematic diagram that the calibration comparator 30 shown in Fig. 3 C is the present invention, this area tool knows that the knowledgeable, when can be according to different demands, does suitable modification, and is not limited to this conventionally.For instance, please refer to Fig. 4, Fig. 4 is the circuit diagram of calibration comparator 30.In Fig. 4, the first controlled variable resistor 306 and the second controlled variable resistor 308 are formed by transistor MN3 and transistor MN4 respectively.The gate of transistor MN3 and transistor MN4 is connected to positive input terminal IN_P and negative input end IN_N, is used for receiving differential sampled signal.Starting switch 302 is formed by transistor MN5, and its conducting in the time that clock signal CLK is high voltage, to start the comparison of calibration comparator 30.Resetting Switching module 300 is formed by transistor MP3, MP4, MP5 and MP6, respectively in order to realize a Resetting Switching, take in clock signal CLK conducting during as low-voltage, thereby relatively hold CT1, second relatively to hold CT2, the first output terminal OP1 and the second output terminal OP2 to be refitted in high voltage by first.Bolt-lock unit 304 is formed by transistor MN1, MP1, MN2 and MP2.Wherein, transistor MN1 and MP1 form one first phase inverter INV1, and transistor MN2 and MP2 form one second phase inverter INV2.The input end of the output terminal of the first phase inverter INV1 and the second phase inverter INV2 is connected, and the input end of the output terminal of the second phase inverter INV2 and the first phase inverter INV1 is connected, and forms the latch assembly 304 that can keep in a data.Because first input end CT1 is connected in the source electrode of transistor MN1 in bolt-lock unit 304, if the source voltage of transistor MN1 is higher, the driving force of the first phase inverter INV1 being formed by transistor MP1 and transistor MN1 diminishes.If the same time, the source voltage of transistor MN2 that is connected in the second input end CT2 is lower, and it is large that the driving force of the second phase inverter INV2 being formed by transistor MP2 and transistor MN2 becomes.Thus, the phase inverter that has a stronger driving force will determine the steady state (SS) of bolt-lock unit 304.Take said circumstances as example, the driving force of the second phase inverter INV2 that transistor MP2 and transistor MN2 form is larger, will make the first output terminal OP1 be output as low-voltage.Otherwise if the source voltage of transistor MN1 is lower, the driving force of the first phase inverter INV1 being formed by transistor MP1 and transistor MN1 is larger, will make the first output terminal OP1 be output as high voltage.
It should be noted that, according to circuit theory, electrical conductivity (conductivity) between field-effect transistor drain and source electrode can increase with drain to the enhancing of the passage electric field intensity between source electrode, therefore via controlling transistorized gate to the voltage difference of source electrode, can change the electrical conductivity between drain and the source electrode of transistor.Therefore, in all identical situation of the length and width of transistor MN3 and MN4, the electrical conductivity between transistor drain and source electrode will be proportional to transistorized aisle resistance, thereby can be poor to source voltage by transistorized gate, adjust transistorized aisle resistance.Therefore controlled variable resistor 306 and 308 can be realized with transistor MN3 and MN4 respectively.
In addition, for convenience of clear interpretation controlled capacitance device 310, please continue to refer to Fig. 4.Controlled capacitance device 310 in Fig. 4 is controlled by the numerical data D_1 of single position, wherein comprises positive limit switch S P_1, marginal switch S N_1, phase inverter INV_1 and capacitor C C_1.Positive limit switch S P_1 and marginal switch S N_1 are formed by transistor MN6 and MN7 respectively, are used for controlling first and relatively hold CT1 and second relatively to hold the link of CT2 to capacitor C C_1.Phase inverter INV_1 is formed by transistor MP_N1 and MN1_N1, in order to produce the inversion signal YD_1 of bit data D_1.Capacitor C C_1 is formed by a metal-oxide semiconductor formula electric capacity, as the first capacitance of relatively holding CT1 or second relatively to hold CT2 to observe is provided.
In Fig. 4, controlled capacitance device 310 only comprises an electric capacity, and in fact, controlled capacitance device 310 also can, according to different demands, exceed more than one electric capacity and have.Please refer to Fig. 5 A, Fig. 5 A shows another embodiment schematic diagram of calibration comparator 30.For the circuit of the clear controlled capacitance device 310 that shows more than one controlled capacitance sub-cell connects receiving method, in Fig. 5 A, controlled capacitance device 310 comprises controlled capacitance sub-cell CU_1 and CU_2, and controls this two controlled capacitance sub-cells (CU_1 and CU_2) by the numerical data D (comprising a D_1 and D_2) of two.Controlled capacitance sub-cell CU_1 comprises the positive limit switch that transistor MN6 forms, marginal switch, a phase inverter (not being shown in figure) and the capacitance component CC_1 who is formed by metal-oxide semiconductor formula electric capacity that transistor MN7 forms.The gate of transistor MN6 is connected in the position D_1 of numerical data D, and the gate of transistor MN7 is connected in the inversion signal YD_1 of a D_1.Controlled capacitance sub-cell CU_2 comprises the positive limit switch that a transistor MN8 forms, marginal switch, a phase inverter (not being shown in figure) and the capacitance component CC_2 who is formed by metal-oxide semiconductor formula electric capacity that a transistor MN9 forms.The gate of transistor MN8 is connected in the position D_2 of numerical data D, and the gate of transistor MN9 is connected in the inversion signal YD_2 of a D_2.Wherein, the capacitance of capacitance component CC_2 is a times of capacitance component CC_1; Therefore, can, by control bit D_1 and position D_2, relatively hold CT1 and second relatively to hold in first and between CT2, produce the capacitance that quadravalence (i.e. two quadratic power rank) varies in size.In addition, other How It Works is all entirely identical to aforementioned, therefore it will not go into details.
Please refer to Fig. 5 B, Fig. 5 B is another embodiment schematic diagram of calibration comparator 30.In Fig. 5 B, controlled capacitance device 310 comprises controlled capacitance sub-cell CU_1～CU_N.Wherein, each controlled capacitance sub-cell of controlled capacitance sub-cell CU_1～CU_N all comprises a positive limit switch, a marginal switch, a phase inverter and an electric capacity.Therefore, N controlled capacitance sub-cell CU_1～CU_N comprises N positive limit switch S P_1～SP_N, N marginal switch S N_1～SN_N, N phase inverter INV_1～INV_N and N capacitor C C_1～CC_N altogether.Wherein, the capacitance of capacitor C C_1～CC_N is scale-of-two proportionate relationship.In addition,, in Fig. 5 B, a digital data port 312 is used for receiving digital data D (containing D_1～D_N equipotential).Preferably, the figure place of numerical data D is corresponding to the number of controlled capacitance device 310, and it represents the numeral of a scale-of-two, and in order to represent the size of specific physical quantity or numeral, the position of for example voltage is accurate etc.Because the capacitance in controlled capacitance sub-cell CU_1～CU_N is one to be the sequence of scale-of-two proportionate relationship, make each controlled capacitance sub-cell CU_1～CU_N corresponding one to one with each the D_1～D_N in numerical data D, and connect one to one, for example, D_1 be connected in CU_1, D_2 be connected in CU_2 ..., and D_N be connected in CU_N etc.Thus, the size of numerical data D representative can the man-to-man various combination corresponding to capacitance in all controlled capacitance sub-cells.Therefore, can pass through control bit D_1～D_N, in the first capacitance of relatively holding CT1 and second relatively to hold the Nth power rank of CT2 generation two to vary in size.Therefore, can further pass through input digital data D, control the first electric capacity number of relatively holding CT1 and second relatively to hold CT2 to observe, the equivalent drift voltage EOV varying in size to produce two Nth power rank, as comparing than use with differential sampled signal.In addition,, in Fig. 5 B, except obvious sign controlled capacitance sub-cell CU_1～CU_N, remaining circuit and How It Works are all entirely identical to aforementioned, therefore it will not go into details.
Therefore, in the time that needs increase the digital precision to analog-converted, calibration comparator 30 Only need increase the figure place of numerical data D and the number of controlled capacitance sub-cell CU_1～CU_N, can increase the precision of numeral to analog-converted.Wherein, because the capacitor C C_1～CC_N in controlled capacitance sub-cell all can be formed by metal-oxide semiconductor formula electric capacity (MOS Capacitor), with saving chip area.According to experimental measurement result, the unit-area capacitance value of metal-oxide semiconductor formula electric capacity is about 7fF/ μ m
2.Therefore, metal-oxide semiconductor formula electric capacity shared chip area can far beyond general used metal-insulator-metal type formula electric capacity, (unit-area capacitance value be about 1～2fF/ μ m
2) reduce many.
Be more than implementation method, principle and the constitutive requirements of the calibration comparator that used in the present invention.According to above-mentioned calibration comparator, the present invention is set up the brand-new framework of an analog-to-digital converter.Calibration comparator 30 can be according to multistage comparison and judgment mode, differential sampled signal VSIN after each sampling is carried out to the inferior comparison of plural number, comparison each time all can produce a new significance bit, makes the progressively differential sampled signal VSIN of convergence of the corresponding equivalent drift voltage EOV of numerical data D.The corresponding numerical data D of memory address ADDR is corresponding to the equivalent drift voltage EOV of calibration comparator 30.In brief, the control module 602 that approaches of analog-to-digital converter 60 judges the corresponding memory address ADDR of equivalent drift voltage EOV of next stage according to the comparative result COMP of calibration comparator 30, and exports to and search internal memory 604.Calibration comparator 30 is according to searching the numerical data D that internal memory 604 is exported, to control controlled capacitance sub-cell CU_1～CU_N (relevant numerical data D and controlled capacitance sub-cell CU_1～CU_N, please refer to Fig. 5 B), produce the equivalent drift voltage EOV of next stage, with the differential sampled signal VSIN of convergence.Approach control module 602 and often do the once action of judgement, analog-to-digital converter 60 just produces a new significance bit, and circulation according to this, until produce all significance bits.It should be noted that the requirement for meeting degree of accuracy, the figure place of searching the numerical data D that internal memory 604 exports should at least be greater than calibration comparator exports the figure place of memory address ADDR.
Hence one can see that, and the calibration comparator 30 being used due to the disclosed analog-to-digital converter 60 of the present invention is integrated numeral to analog-converted function, thereby can exempt in known technology numeral to analog-converted unit 106, and then the consumption of saving electric power.In addition, analog-to-digital converter 60 can be in when start, and the situation that needs to recalibrate is while occurring, carries out the calibration actions of calibration comparator 30, to set up or to upgrade the corresponding relation of searching numerical data D and equivalent drift voltage EOV in internal memory 604.
In sum, one of the present invention and known technology major technique difference, is that the present invention uses the comparer of an integration numeral to analog-converted function, and numeral in known technology is removed to analog-converted unit.
Meanwhile, exempted the digital reference voltage circuit to the required use in analog-converted unit in known technology, thereby saved much electric power.Via distinctive calibration procedure, the present invention's analog-to-digital converter can store the numerical data of comparer and the funtcional relationship of equivalent drift voltage, makes the present invention without using the good capacitive means of the linearity, can simulate accurately to digital conversion.Via the metal-oxide semiconductor formula electric capacity that uses high unit-area capacitance value, the chip area that electric capacity is shared thereby significantly minimizing.
Generally speaking, by designing the unique architecture and the comparer of integration numeral to analog-converted function of an analog-to-digital converter, to replace known numeral to analog-converted unit, the present invention can effectively reach significantly saves energy and the effect that reduces chip area.
The foregoing is only the preferred embodiments of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (29)
1. save an analog-to-digital converter for electrical source consumption, it is characterized in that comprising:
One sampling keeping unit, is connected in an external differential input signal, according to a sampling frequency signal, and sampling, maintenance and output one differential sampled signal;
One approaches control module, is connected in a calibration comparator, according to the comparative result of this comparer, and output one memory address, and in simulating while completing to digital conversion, output one transformation result;
One searches internal memory, is connected in this calibration comparator and this approaches control module, and according to this memory address, output one numerical data is to a digital data port of this calibration comparator; And
This calibration comparator, is connected in this sampling keeping unit, this approaches control module and this searches internal memory, relatively this differential sampled signal and a built-in equivalent drift voltage, and output one comparative result, comprising:
One positive input terminal, is used for receiving a forward signal of a differential sampled signal;
One negative input end, is used for receiving a negative-going signal of this differential sampled signal;
One clock signal input end, is used for receiving a clock signal;
This digital data port, is used for receiving a numerical data;
One bolt-lock unit; comprise one first relatively end, one second relatively end; one first output terminal and one second output terminal, be used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output terminal and this second output terminal;
One starting switch, comprises a first end, and one second end is connected in this clock signal input end, and one the 3rd end is connected in a ground end, is used for according to the size of this clock signal, controls this first end to the signal of the 3rd end and links;
One first controlled variable resistor; be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit; be used for according to this forward signal of this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch;
One second controlled variable resistor; be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit; be used for according to this negative-going signal of this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch;
One Resetting Switching module, is connected in this clock signal input end and this bolt-lock unit, is used for, according to the size of this clock signal, controlling the state of this bolt-lock unit;
One controlled capacitance device, is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And
One output terminal, is connected in this first output terminal of this bolt-lock unit, is used for exporting a comparative result.
2. analog-to-digital converter as claimed in claim 1, is characterized in that separately comprising a calibration module, is used for calibrating this analog-to-digital converter.
3. analog-to-digital converter as claimed in claim 2, is characterized in that this calibration module comprises: a standard voltage source, is used between scale value and a voltage subscript value, providing multiple standard voltage value on a voltage;
One voltage-selected switch, is connected in this standard voltage source and this positive input terminal, with selecting a standard voltage value to export this positive input terminal in the plurality of standard voltage value of cause;
One counter, is connected in a controller calibration and this calibration comparator, is used for producing a count results;
One internal memory, is connected in this counter, is used in the time that this calibration comparator shows that this comparative result equates, records this count results of this counter in one corresponding to a memory address of this standard voltage value; And
This controller calibration, is connected in this calibration comparator, is used in the time that this calibration comparator shows that this comparative result equates, controls this internal memory and record this count results of this counter.
4. analog-to-digital converter as claimed in claim 1, it is characterized in that this first controlled variable resistor, this second controlled variable resistor and this starting switch are all N-type MOS (metal-oxide-semiconductor) transistor, one drain of this first controlled variable resistor and this second controlled variable-resistance this N-type MOS (metal-oxide-semiconductor) transistor be connected in this bolt-lock unit this first relatively end, one gate is connected in this positive input terminal, and one source pole is connected in this first end of this starting switch.
5. analog-to-digital converter as claimed in claim 1, is characterized in that this Resetting Switching module comprises:
One first Resetting Switching, comprises that a first end is connected in a power supply, and one second end is connected in this clock signal input end, and one the 3rd end be connected in this bolt-lock unit this first relatively end, be used for according to clock signal, this first end of conducting is to the link of the 3rd end;
One second Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end is connected in this first output terminal of this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the link of the 3rd end;
One the 3rd Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end is connected in this second output terminal of this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the link of the 3rd end; And
One the 4th Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end be connected in this bolt-lock unit this second relatively end, be used for according to clock signal, this first end of conducting is to the link of the 3rd end.
6. analog-to-digital converter as claimed in claim 5, it is characterized in that this first Resetting Switching, this second Resetting Switching, the 3rd Resetting Switching and the 4th Resetting Switching are all P type MOS (metal-oxide-semiconductor) transistor, and this first end of each Resetting Switching is one source pole, this second end is a gate, and the 3rd end is a drain.
7. analog-to-digital converter as claimed in claim 1, is characterized in that this bolt-lock unit comprises:
One first phase inverter, is connected in a power supply, this first relatively end, this first output terminal and this second output terminal, is used for according to the relatively signal of end of this power supply and this first, exports the anti-phase result of signal of this first output terminal to this second output terminal; And
One second phase inverter, is connected in this power supply, this second relatively end, this first output terminal and this second output terminal, is used for the signal relatively held according to this power supply and second, exports the anti-phase result of signal of this second output terminal to this first output terminal.
8. analog-to-digital converter as claimed in claim 7, is characterized in that this first phase inverter and this second phase inverter all respectively comprise:
One P type MOS (metal-oxide-semiconductor) transistor, one gate is connected in this first output terminal, and one source pole is connected in this power supply, and a drain is connected in this second output terminal; And
One N-type MOS (metal-oxide-semiconductor) transistor, one gate is connected in this first output terminal, and one source pole is connected in this first end relatively, and a drain is connected in this second output terminal.
9. analog-to-digital converter as claimed in claim 1, is characterized in that this controlled capacitance device comprises:
One electric capacity, comprises a first end, and one second end is connected in this ground end;
One positive limit switch; comprise a first end be connected in this bolt-lock unit this first relatively end, one second end is connected in this numerical data, and one the 3rd end is connected in this electric capacity; be used for according to the signal magnitude of this numerical data, this first end of conducting to the signal of the 3rd end links;
One phase inverter, is used for producing the anti-phase result of this numerical data; And
One marginal switch, comprise a first end be connected in this bolt-lock unit this second relatively end, one second end is connected in this phase inverter, and one the 3rd end is connected in this electric capacity, be used for according to the inversion signal size of this numerical data, this first end of conducting to the signal of the 3rd end links.
10. analog-to-digital converter as claimed in claim 9, it is characterized in that this positive limit switch and this marginal switch are all N-type MOS (metal-oxide-semiconductor) transistor, this first end of this positive limit switch or this marginal switch is a drain, and this second end is a gate, and the 3rd end is one source pole.
11. analog-to-digital converters as claimed in claim 1, is characterized in that this circuit coefficients value is a resistance value, or a capacitance, or the product of a capacitance and a resistance value.
12. analog-to-digital converters as claimed in claim 1, is characterized in that this controlled capacitance device comprises:
Multiple electric capacity, each electric capacity comprises a first end, and one second end is connected in this ground end;
Multiple positive limits switch; each positive limit switch comprise a first end be connected in this bolt-lock unit this first relatively end; one second end is connected in this numerical data; and one the 3rd end be connected in an electric capacity of the plurality of electric capacity; be used for according to the signal magnitude of this numerical data, this first end of conducting to the signal of the 3rd end links;
Multiple phase inverters, each phase inverter is used for producing the anti-phase result of this numerical data; And
Multiple marginal switches, each marginal switch comprise a first end be connected in this bolt-lock unit this second relatively end, one second end is connected in a phase inverter of the plurality of phase inverter, and one the 3rd end be connected in an electric capacity of the plurality of electric capacity, be used for according to the inversion signal size of this numerical data, this first end of conducting to the signal of the 3rd end links.
13. analog-to-digital converters as claimed in claim 12, is characterized in that the capacitance of the plurality of electric capacity is scale-of-two proportionate relationship.
14. analog-to-digital converters as claimed in claim 12, it is characterized in that the plurality of positive limit switch and the plurality of marginal switch are all N-type MOS (metal-oxide-semiconductor) transistor, this first end of each positive limit switch or marginal switch is a drain, and this second end is a gate, and the 3rd end is one source pole.
15. 1 kinds of calibration comparators for an analog-to-digital converter, is characterized in that comprising:
One positive input terminal, is used for receiving a forward signal of a differential sampled signal;
One negative input end, is used for receiving a negative-going signal of this differential sampled signal;
One clock signal input end, is used for receiving a clock signal;
One digital data port, is used for receiving a numerical data;
One bolt-lock unit; comprise one first relatively end, one second relatively end; one first output terminal and one second output terminal, be used for relatively this first relatively end and this second size of a circuit coefficients value of end relatively, to determine the state value of this first output terminal and this second output terminal;
One starting switch, comprises a first end, and one second end is connected in this clock signal input end, and one the 3rd end is connected in a ground end, is used for according to the size of this clock signal, controls this first end to the signal of the 3rd end and links;
One first controlled variable resistor; be connected in this first relatively end and this first end of this starting switch of this positive input terminal, this bolt-lock unit; be used for according to this forward signal of this differential sampled signal, this that adjust this bolt-lock unit first relatively held to the resistance value between this first end of this starting switch;
One second controlled variable resistor; be connected in this second relatively end and this first end of this starting switch of this negative input end, this bolt-lock unit; be used for according to this negative-going signal of this differential sampled signal, this that adjust this bolt-lock unit second relatively held to the resistance value between this first end of this starting switch;
One Resetting Switching module, is connected in this clock signal input end and this bolt-lock unit, is used for, according to the size of this clock signal, controlling the state of this bolt-lock unit;
One controlled capacitance device, is connected in this first relatively this second relatively end and this ground end of end, this bolt-lock unit of this bolt-lock unit, is used for according to a numerical data, control this first relatively end and this second relatively hold the capacitance of holding to this ground; And
One output terminal, is connected in this first output terminal of this bolt-lock unit, is used for exporting a comparative result.
16. calibration comparators as claimed in claim 15, it is characterized in that this first controlled variable resistor and this second controlled variable resistor are N-type MOS (metal-oxide-semiconductor) transistor, one drain of this N-type MOS (metal-oxide-semiconductor) transistor be connected in this bolt-lock unit this first relatively end, one gate is connected in this positive input terminal, and one source pole is connected in this first end of this starting switch.
17. calibration comparators as claimed in claim 15, is characterized in that this starting switch is a N-type MOS (metal-oxide-semiconductor) transistor, and this first end of this starting switch is a drain, and this second end is a gate, and the 3rd end is one source pole.
18. calibration comparators as claimed in claim 15; it is characterized in that this Resetting Switching module comprises: one first Resetting Switching; comprise that a first end is connected in a power supply; one second end is connected in this clock signal input end; and one the 3rd end be connected in this bolt-lock unit this first relatively end; be used for according to clock signal, this first end of conducting is to the link of the 3rd end;
One second Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end is connected in this first output terminal of this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the link of the 3rd end;
One the 3rd Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end is connected in this second output terminal of this bolt-lock unit, is used for according to clock signal, and this first end of conducting is to the link of the 3rd end; And
One the 4th Resetting Switching, comprises that a first end is connected in this power supply, and one second end is connected in this clock signal input end, and one the 3rd end be connected in this bolt-lock unit this second relatively end, be used for according to clock signal, this first end of conducting is to the link of the 3rd end.
19. calibration comparators as claimed in claim 18, it is characterized in that this first Resetting Switching, this second Resetting Switching, the 3rd Resetting Switching and the 4th Resetting Switching are all P type MOS (metal-oxide-semiconductor) transistor, and this first end of each Resetting Switching is one source pole, this second end is a gate, and the 3rd end is a drain.
20. calibration comparators as claimed in claim 15, is characterized in that this bolt-lock unit comprises:
One first phase inverter, is connected in a power supply, this first relatively end, this first output terminal and this second output terminal, is used for according to the relatively signal of end of this power supply and this first, exports the anti-phase result of signal of this first output terminal to this second output terminal; And
One second phase inverter, is connected in this power supply, this second relatively end, this first output terminal and this second output terminal, is used for the signal relatively held according to this power supply and second, exports the anti-phase result of signal of this second output terminal to this first output terminal.
21. calibration comparators as claimed in claim 20, is characterized in that this first phase inverter and this second phase inverter all respectively comprise:
One P type MOS (metal-oxide-semiconductor) transistor, one gate is connected in this first output terminal, and one source pole is connected in this power supply, and a drain is connected in this second output terminal; And
One N-type MOS (metal-oxide-semiconductor) transistor, one gate is connected in this first output terminal, and one source pole is connected in this first end relatively, and a drain is connected in this second output terminal.
22. calibration comparators as claimed in claim 15, is characterized in that this controlled capacitance device comprises:
One electric capacity, comprises a first end, and one second end is connected in this ground end;
One positive limit switch; comprise a first end be connected in this bolt-lock unit this first relatively end, one second end is connected in this numerical data, and one the 3rd end is connected in this electric capacity; be used for according to the signal magnitude of this numerical data, this first end of conducting to the signal of the 3rd end links;
One phase inverter, is used for producing the anti-phase result of this numerical data; And
One marginal switch, comprise a first end be connected in this bolt-lock unit this second relatively end, one second end is connected in this phase inverter, and one the 3rd end is connected in this electric capacity, be used for according to the inversion signal size of this numerical data, this first end of conducting to the signal of the 3rd end links.
23. calibration comparators as claimed in claim 22, it is characterized in that this positive limit switch and this marginal switch are all N-type MOS (metal-oxide-semiconductor) transistor, this first end of this positive limit switch or this marginal switch is a drain, and this second end is a gate, and the 3rd end is one source pole.
24. calibration comparators as claimed in claim 15, is characterized in that this circuit coefficients value is a resistance value, or a capacitance, or the product of a capacitance and a resistance value.
25. calibration comparators as claimed in claim 15, is characterized in that this electric capacity is a metal-oxide semiconductor formula electric capacity.
26. calibration comparators as claimed in claim 15, is characterized in that this controlled capacitance device comprises: multiple electric capacity, and each electric capacity comprises a first end, and one second end is connected in this ground end; Multiple positive limits switch; each positive limit switch comprise a first end be connected in this bolt-lock unit this first relatively end; one second end is connected in this numerical data; and one the 3rd end be connected in an electric capacity of the plurality of electric capacity; be used for according to the signal magnitude of this numerical data, this first end of conducting to the signal of the 3rd end links;
Multiple phase inverters, each phase inverter is used for producing the anti-phase result of this numerical data; And
Multiple marginal switches, each marginal switch comprise a first end be connected in this bolt-lock unit this second relatively end, one second end is connected in a phase inverter of the plurality of phase inverter, and one the 3rd end be connected in an electric capacity of the plurality of electric capacity, be used for according to the inversion signal size of this numerical data, this first end of conducting to the signal of the 3rd end links.
27. calibration comparators as claimed in claim 26, is characterized in that the capacitance of the plurality of electric capacity is scale-of-two proportionate relationship.
28. calibration comparators as claimed in claim 26, is characterized in that the plurality of electric capacity is all metal-oxide semiconductor formula electric capacity.
29. calibration comparators as claimed in claim 26, it is characterized in that the plurality of positive limit switch and the plurality of marginal switch are all N-type MOS (metal-oxide-semiconductor) transistor, this first end of each positive limit switch or marginal switch is a drain, and this second end is a gate, and the 3rd end is one source pole.
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| TWI556585B (en) * | 2015-06-11 | 2016-11-01 | 矽創電子股份有限公司 | Analog-to-Digital Converting Device and Related Calibration Method and Calibration Module |
| CN105677295B (en) * | 2016-01-04 | 2018-06-26 | 湖南工业大学 | Seek the circuit of ratio value between two input voltages |
| TWI665875B (en) * | 2018-02-13 | 2019-07-11 | 新唐科技股份有限公司 | Digital background calibration circuit |
| CN113552793B (en) * | 2021-07-26 | 2022-04-05 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
| CN114245985B (en) * | 2021-09-17 | 2024-07-05 | 汇顶科技私人有限公司 | Comparator, related image sensor and electronic device |
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| US6400302B1 (en) * | 2001-02-26 | 2002-06-04 | Analog Devices, Inc. | Quasi-differential successive-approximation structures and methods for converting analog signals into corresponding digital signals |
| US6608582B2 (en) * | 2001-06-29 | 2003-08-19 | Intel Corporation | A/D conversion using a variable offset comparator |
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
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| CN102237874A (en) | 2011-11-09 |
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