Invention content
The purpose of the present invention is the division arithmetic between analog voltage provides a solution, two can be calculated
Ratio value and while the circuit of output digit signals and analog signal operation result between the bipolar voltage of input.
To achieve these goals, the present invention provides a kind of circuit for seeking ratio value between two input voltages, by ratio
It is worth computing unit, analog result output unit and four-quadrant adjustment and sequencing unit composition.
The ratio value computing unit is equipped with molecule voltage input end, denominator voltage input end and digital ratio value output
End.
The core of the ratio value computing unit is parallel A/D converter;The parallel A/D converter has analog voltage
Input terminal, reference voltage input terminal and parallel data output terminal;The parallel A/D converter is operated in automatic continuous modulus of conversion
Formula, mode include parallel A/D converter is arranged on automatic continuous translative mode or is converted by parallel A/D converter
End signal restarting A/D conversions next time or the recurrent pulse by additionally generating control parallel A/D converter to carry out
A/D is converted.
The analog voltage input of the parallel A/D converter is the molecule voltage input end of ratio value computing unit, is joined
The denominator voltage input end that voltage input end is ratio value computing unit is examined, parallel data output terminal is ratio value computing unit
Numerical scale value output terminal.
The analog result output unit is equipped with numerical scale value input terminal, scale factor voltage input end and analog voltage
Ratio value output terminal;The numerical scale value input terminal is connected to the numerical scale value output terminal of ratio value computing unit.
The core of the analog result output unit is parallel D/A converter;The parallel D/A converter has and line number
According to input terminal, reference voltage input and conversion voltage output end;The parallel data input terminal of the parallel D/A converter is mould
Intend the numerical scale value input terminal of result output unit, reference voltage input is scale factor voltage input end, converts voltage
Output terminal is analog voltage ratio value output terminal.
The four-quadrant adjustment and sequencing unit are made of voltage swing ranking circuit and absolute value and symbolic circuit, are equipped with
First input voltage input terminal, the second input voltage input terminal, molecule voltage output end, denominator voltage output end and size compare
As a result output terminal, ratio value symbol output terminal.
It is defeated that the voltage swing ranking circuit is equipped with the first input absolute value voltage input terminal, the second input absolute value voltage
Enter end and molecule voltage output end, denominator voltage output end and size comparison result output terminal.
When the first input absolute value voltage amplitude is more than the second input absolute value voltage, voltage swing ranking circuit is defeated
The denominator voltage gone out is equal to the first input absolute value voltage, and molecule voltage is equal to the second input absolute value voltage;Described first is defeated
When entering absolute value voltage amplitude less than the second input absolute value voltage, the denominator voltage of voltage swing ranking circuit output is equal to the
Two input absolute value voltages, molecule voltage are equal to the first input absolute value voltage.
It is defeated that the absolute value and symbolic circuit are equipped with the first input absolute value voltage output terminal, the second input absolute value voltage
Outlet and the first input voltage input terminal, the second input voltage input terminal and ratio value symbol output terminal.
The absolute value and symbolic circuit include the first absolute value circuit, the second absolute value circuit and symbolic operation circuit.
First input voltage is converted into the first input absolute value voltage and exported to voltage swing ranking circuit by the first absolute value circuit;The
Second input voltage is converted into the second input absolute value voltage and exported to voltage swing ranking circuit by two absolute value circuits.Symbol
Computing circuit is exported between two input voltages in the form of switching value according to the polarity of the first input voltage and the second input voltage
Ratio value symbol.
The numerical scale value of the numerical scale value output terminal output and the numerical scale of digital ratio value input terminal input
Value is binary number;When the binary digit digit of numerical scale value output terminal is equal to the binary digit of numerical scale value input terminal
During digit, directly the binary digit of numerical scale value input terminal is sequentially connected with the binary digit of numerical scale value output terminal;
When the binary digit digit of numerical scale value output terminal is more than the binary digit digit of numerical scale value input terminal, numerical scale
The binary digit of value input terminal is sequentially connected since a numerical scale value output terminal high position, and numerical scale value output terminal has more low
Position binary digit is not attached to numerical scale value input terminal;When the binary digit digit of numerical scale value output terminal is less than digital ratio
It is during the binary digit digit of example value input terminal, the binary digit of numerical scale value output terminal is high-order from numerical scale value input terminal
Start sequentially to be connected, the low level binary digit that numerical scale value input terminal has more is connected to low level.
If the first input voltage is UX;Second input voltage is UY;The numerical scale value of numerical scale value output terminal output
For Z, maximum value Zmax;The scale factor voltage of scale factor voltage input end input is UK;Analog voltage ratio value is defeated
The analog voltage ratio value of outlet output is U0;Then
When | UX |>| UY | when, have
When | UX |<| UY | when, have
When | UX |=| UY | when, have
Size comparison result output terminal output size comparison result in the form of switching value;The ratio value symbol is defeated
Outlet export ratio value symbol in the form of switching value.The form of the switching value is high and low level.
First input voltage and the second input voltage are all bipolar voltages.The parallel A/D converter is with reference to electricity
Pressure input terminal allows the reference voltage range of input all wider than the absolute value range of the first input voltage and the second input voltage.
The parallel D/A converter is in direct D/A transition status.
The voltage swing ranking circuit is made of binary channels two-way analog switch and comparator;The comparator is to first
Input absolute value voltage, the second amplitude size for inputting absolute value voltage are compared;The size comparison result output terminal is defeated
The size comparison result gone out is controlled by the output of comparator;The channel selecting of the binary channels two-way analog switch is by comparator
Output control.
The invention has the advantages that the ratio value between two bipolarity input voltages is asked for automatically, and simultaneously with number
The form of word signal and analog signal exports, and the size comparison result and ratio value symbol between two input voltages are with switching value
Form output.
Specific embodiment
With reference to embodiment and attached drawing, the present invention is described in further detail, but embodiments of the present invention are unlimited
In this.
A kind of structure diagram for seeking the circuit of ratio value between two input voltages is as shown in Figure 1, by ratio value computing unit
100th, analog result output unit 200 and four-quadrant adjustment and sequencing unit 300 form.
The core of ratio value computing unit 100 is parallel A/D converter, equipped with molecule voltage input end VIN, denominator voltage
Input terminal REF and number ratio value output terminal DB OUT.
The parallel A/D converter has analog voltage input, reference voltage input terminal and parallel data output terminal, work
Make in automatic continuous translative mode.The analog voltage input is the molecule voltage input end of ratio value computing unit 100
VIN, reference voltage input terminal are the denominator voltage input end REF of ratio value computing unit 100, and parallel data output terminal is ratio
It is worth the numerical scale value output terminal DB OUT of computing unit 100.
The embodiment 1 of ratio value computing unit 100 is as shown in Fig. 2, by parallel A/D converter 101, resistance 102, capacitance
103rd, it is formed with door 104.The model of parallel A/D converter 101 is 8 parallel-by-bit A/D converter ADC0841.The simulation of ADC0841
Voltage input end is VIN+, and reference voltage input terminal VREF, 8 bit parallel data output terminals are DB7~DB0.The WR of ADC0841
To start conversion inputs, negative pulse is effective;WR is connected to the output terminal with door 104;With one of door 104 input be connected to by
Resistance 102, capacitance 103 form power on pulse output end, another input be connected to ADC0841 conversion end signal it is defeated
Outlet INTR;When powering on, ADC0841 is started by upper electric pulse and carries out the conversion of first time A/D, after A/D conversion ends, INTR outputs
Negative pulse start ADC0841 and carry out new A/D conversions, in cycles, ADC0841 is operated in automatic continuous modulus of conversion
Formula.
The analog voltage input negative terminal VIN- of ADC0841, output Enable Pin RD, digitally chip select terminal CS, DGND, simulation ground
AGND is connected to publicly, and the power end VCC of ADC0841 is connected to positive supply+VDD.The output Enable Pin RD inputs of ADC0841
During low level, data output end DB7~DB0 maintains output effective.It, automatically will knot after ADC0841 conversion ends each time
Fruit exports from data output end DB7~DB0.
If the voltage for being connected to molecule voltage input end VIN is U1, being connected to the voltage of denominator voltage input end REF is
The digital signal of U2, numerical scale value output terminal DB OUT outputs is Z.In the embodiment 1 of ratio value computing unit 100, Z is number
According to z7~z0 that output terminal DB7~DB0 is exported, maximum value Zmax is 255.Then have
Ratio value i.e. between two input voltages U1, U2 is
The embodiment 2 of ratio value computing unit 100 is as shown in figure 3, by parallel A/D converter 111,555 time base apparatus parts
112nd, resistance 113, resistance 114, capacitance 115 form.The model of parallel A/D converter 111 is 8 parallel-by-bit A/D converters
ADC0841.The embodiment 2 of ratio value computing unit 100 and the embodiment 1 of ratio value computing unit 100 the difference lies in,
Oscillator is formed by 555 time base apparatus parts 112, resistance 113, resistance 114, capacitance 115, the recurrent pulse of oscillator output is connected to
The startup conversion inputs WR of A/D converter 111, each pulse start an A/D conversion, are operated in A/D converter 111
Automatic continuous translative mode.The other parts of the embodiment 2 of ratio value computing unit 100 and the reality of ratio value computing unit 100
Apply that example is identical, the ratio value between two input voltages U1, U2 is
The embodiment 3 of ratio value computing unit 100 is as shown in figure 4, by parallel A/D converter 121,555 time base apparatus parts
122nd, resistance 123, resistance 124, capacitance 125 form.The model of parallel A/D converter 121 is 12 parallel-by-bit A/D converters
AD7492.The analog voltage input of AD7492 be VIN, reference voltage input terminal be REF IN, 12 bit parallel data output terminals
For DB11~DB0.The CONVST of AD7492 starts A/D conversions to start conversion inputs, failing edge.555 time base apparatus parts
122nd, resistance 123, resistance 124, capacitance 125 form oscillator, and the recurrent pulse of oscillator output is connected to A/D converter 121
Startup conversion inputs CONVST, each pulse starts A/D conversion, A/D converter 121 made to be operated in automatically continuously
Translative mode.
The output Enable Pin RD of AD7492, chip select terminal CS, digitally suspend mode selection end PS/FS, DGND, simulation ground
AGND is connected to publicly, and analog power end AVDD, the digital power end DVDD of AD7492 are connected to positive supply+VDD.AD7492
Output Enable Pin RD input low levels when, data output end DB11~DB0 maintains output effective.When AD7492 turns each time
After changing, result is exported from data output end DB11~DB0 automatically.
In the embodiment 3 of ratio value computing unit 100, Z is z11~z0 of data output end DB11~DB0 outputs,
Its maximum value Zmax is 4095.Then have
Ratio value i.e. between two input voltages U1, U2 is
Parallel A/D converter reference voltage input terminal allows the reference voltage of input in the ratio value computing unit 100
Range is wider than the input voltage U2 ranges for being connected to 100 denominator voltage input end REF of ratio value computing unit.
In addition to translative mode automatic continuous used by A/D converter parallel in above-mentioned 3 embodiments, when it is selected simultaneously
When row A/D converter can be operated in automatic continuous translative mode by setting, preferably convert parallel A/D by set-up mode
Device is operated in automatic continuous translative mode.
The core of analog result output unit 200 is parallel D/A converter, equipped with numerical scale value input terminal DB IN, ratio
Example factor voltage input end VIN3 and analog voltage ratio value output terminal VOUT.The numerical scale value input terminal DB IN connections
To the numerical scale value output terminal DB OUT of ratio value computing unit 100.
The parallel D/A converter has parallel data input terminal, reference voltage input and conversion voltage output end.Institute
The numerical scale value input terminal DB IN that parallel data input terminal is analog result output unit 200 are stated, reference voltage input is
The scale factor voltage input end VIN3 of analog result output unit 200, converts voltage output end as analog result output unit
200 analog voltage ratio value output terminal VOUT.
The embodiment 1 of analog result output unit 200 parallel D/A converter 201 as shown in figure 5, be made of, parallel D/A
The model of converter 201 is 8 parallel-by-bit D/A converter AD5330.The parallel data input terminal of AD5330 be DB7~DB0, benchmark
Voltage input end is VREF, converts voltage output end as VOUT.
The buffer switch control terminal BUF of AD5330, export ratio control terminal GAIN, input register control terminal WR, DAC
Register control terminal LDAC, chip select terminal CS, ground terminal GND are connected to publicly, the clear terminal CLR of AD5330, low power consumption control end
PD, power end VDD are connected to positive supply+VDD.The input register control terminal WR and DAC register control terminal LDAC of AD5330
During input low level, in direct D/A transition status, when not considering transfer lag, conversion voltage output end VOUT reflects in real time
The data conversion result of parallel data input terminal DB7~DB0.
If the voltage for being connected to scale factor voltage input end VIN3 is UK, analog voltage ratio value output terminal VOUT outputs
Voltage be U0, the data of parallel data input terminal DB7~DB0 inputs are z7~z0 of Z, i.e., 8, and maximum value Zmax1 is
255, then have
When Zmax1 is equal with Zmax, have
When taking UK equal to 1V, have
Obviously, if analog result output unit 200 uses embodiment 1, ratio value computing unit 100 is using implementation
When example 1 or embodiment 2, Zmax1 is equal with Zmax.If analog result output unit 200 uses embodiment 1, ratio value
During the use embodiment 3 of computing unit 100, to make Zmax1 equal with Zmax, then it should 100 reality of selection percentage value computing unit
The most-significant byte applied in the 12-bit data of the numerical scale value output terminal DB OUT output terminals output of example 3 exports list as analog result
The numerical scale value input terminal DB IN signals of first 200 embodiments 1.
The embodiment 2 of analog result output unit 200 parallel D/A converter 211 as shown in fig. 6, be made of, parallel D/A
The model of converter 211 is 12 parallel-by-bit D/A converter AD5340.The parallel data input terminal of AD5340 be DB11~DB0, base
Quasi- voltage input end is VREF, converts voltage output end as VOUT.
The buffer switch control terminal BUF of AD5340, export ratio control terminal GAIN, input register control terminal WR, DAC
Register control terminal LDAC, chip select terminal CS, ground terminal GND are connected to publicly, the clear terminal CLR of AD5340, low power consumption control end
PD, power end VDD are connected to positive supply+VDD.The input register control terminal WR and DAC register control terminal LDAC of AD5340
During input low level, in direct D/A transition status, when not considering transfer lag, conversion voltage output end VOUT reflects in real time
The data conversion result of parallel data input terminal DB11~DB0.
If the voltage for being connected to scale factor voltage input end VIN3 is UK, analog voltage ratio value output terminal VOUT outputs
Voltage be U0, the data of parallel data input terminal DB11~DB0 inputs are the z11~z0, maximum value Zmax1 of Z, i.e., 12
It is 4095, then has
When Zmax1 is equal with Zmax, have
When taking UK equal to 1V, have
Obviously, if analog result output unit 200 uses embodiment 2, ratio value computing unit 100 is using implementation
During example 3, Zmax1 is equal with Zmax.If analog result output unit 200 uses embodiment 2, ratio value computing unit 100
During using embodiment 1 or embodiment 2, to make Zmax1 equal with Zmax, then it should be by 8 of ratio value computing unit 100
Numerical scale Value Data is connected to the most-significant byte in 12 bit digital ratio value input terminals of analog result output unit 200, simulation knot
Low 4 in 12 bit digital ratio value input terminals of fruit output unit 200 are connected to publicly.
In 3 embodiments of the ratio value computing unit 100 and 2 embodiments of analog result output unit 200, number
The data of word ratio value output terminal DB OUT and number ratio value input terminal DB IN are binary data.The molecule voltage
The voltage U2 of the voltage U1 and denominator voltage input end REF of input terminal VIN are positive voltage, and U1 is less than or equal to U2.
Four-quadrant adjusts and sequencing unit 300 is by voltage swing ranking circuit 301 and 302 groups of absolute value and symbolic circuit
Into.
The effect of voltage swing ranking circuit 301 is to treat two positive input voltages for seeking ratio value, i.e., the first input is exhausted
The amplitude size of threshold voltage UA, the second input absolute value voltage UB are compared, using the larger voltage of wherein amplitude as dividing
Voltage U2, the smaller voltage of amplitude of female voltage input end REF is connected to ratio as the voltage U1 of molecule voltage input end VIN
It is worth computing unit 100, while comparison result is exported in the form of switching value.
301 embodiment of voltage swing ranking circuit is as shown in figure 8, by binary channels two-way analog switch 311, comparator 312
Composition.Binary channels two-way analog switch 311 select double 4 select one multiway analog switch CD4052.
Comparator 312 compares the amplitude size of the first input absolute value voltage UA, the second input absolute value voltage UB
Compared with the effect one of size switch signal SW1 is to be exported in the form of switching value as comparative result, is acted on second is that being connected to
The channel selecting end A of CD4052.The channel selecting end B of CD4052, digitally enabled input terminal INH, VSS, simulation ground VEE connections
To publicly, the VDD of CD4052 is connected to positive supply+VDD.
UA>During UB, size switch signal SW1 output low levels;The output X selection connection X0 of CD4052, output Y selections connect
Logical Y0, i.e. U1=X=X0=UB, U2=Y=Y0=UA;Meet U1<U2.
UA<During UB, size switch signal SW1 output high level;The output X selection connection X1 of CD4052, output Y selections connect
Logical Y1, i.e. U1=X=X1=UA, U2=Y=Y1=UB;Meet U1<U2.
Size switch signal SW1 is exported in the form of switching value as comparative result, and the form of switching value is except aforementioned
Outside high and low level, the NPN triode of open collector, open collector can also be increased after size switch signal SW1
The custom circuit of the diversified forms such as PNP triode, relay obtains the switching value exported in the form of normally opened, normally closed switch etc..
The effect of absolute value and symbolic circuit 302 is that the first input voltage UX is converted into the first input absolute value voltage
UA, the second input voltage UY are converted into the second input absolute value voltage UB and export to voltage swing ranking circuit 301;According to first
The polarity of input voltage UX and the second input voltage UY export the ratio value symbol between two input voltages in the form of switching value
Signal SW2.
Absolute value and 302 embodiment of symbolic circuit are as shown in Figure 9.
Amplifier 321, amplifier 322, diode 323, diode 324, resistance 325, resistance 326, resistance 327, resistance 328,
Resistance 329 forms the first absolute value circuit, and input is the first input voltage UX, exports as the first input absolute value voltage UA;
That is UA is the absolute value of UX.
Amplifier 331, amplifier 332, diode 333, diode 334, resistance 335, resistance 336, resistance 337, resistance 338,
Resistance 339 forms the second absolute value circuit, and input is the second input voltage UY, exports as the second input absolute value voltage UB;
That is UB is the absolute value of UY.
First absolute value circuit, the second absolute value circuit can use other any absolute value circuits or precision complete
Wave rectification circuit.
Comparator 341, comparator 342, diode 343, diode 344, XOR gate 345 form symbolic operation circuit.
The positive and negative polarity of first input voltage UX is converted to low level, high level signal by comparator 341, diode 343
Export and be connected to an input terminal of XOR gate 345;Comparator 342, diode 344 are positive and negative by the second input voltage UY's
Dipole inversion is low level, high level signal exports and is connected to another input terminal of XOR gate 345;XOR gate with it is high,
Low level form export ratio value mark signal SW2;First input voltage UX is identical with the polarity of the second input voltage UY, then
Ratio value mark signal SW2 is low level;The polarity of first input voltage UX and the second input voltage UY differ, then ratio value
Mark signal SW2 is high level.XOR gate 345 is substituted with biconditional gate or by the first input voltage UX from shown in Fig. 9
The negative input end for being connected to comparator 341 is connected to the positive input terminal of comparator 341 or by the second input voltage UY instead
It is connected to the positive input terminal of comparator 342 instead from the negative input end shown in Fig. 9 for being connected to comparator 342, then the first input
When voltage UX is identical with the polarity of the second input voltage UY, ratio value mark signal SW2 is high level;First input voltage UX with
When the polarity of second input voltage UY differs, ratio value mark signal SW2 is low level.
Ratio value mark signal SW2 is exported in the form of switching value, and the form of switching value removes aforementioned high and low level
Outside, the NPN triode of open collector, tri- poles of PNP of open collector can also be increased after ratio value mark signal SW2
The custom circuit of the diversified forms such as pipe, relay obtains the switching value exported in the form of normally opened, normally closed switch etc..
Synthesis is noted earlier, when | UX |>| UY | when, have
When | UX |<| UY | when, have
When | UX |=| UY | when, no matter SW1 is high level or low level, has UA=UB and U1=U2, so having
Described device is of less demanding for comparative example value calculating speed, and UX, UY change shallower occasion.
The foregoing is merely the embodiment of the present invention, are not intended to restrict the invention, and those skilled in the art is come
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is any modification for being made, equivalent
Replace, improve etc., it should be included within scope of the presently claimed invention.