JP4272967B2 - Arithmetic circuit and operation control method thereof - Google Patents

Description

  The present invention relates to an analog / digital mixed type arithmetic circuit, for example, converts a digital signal into an analog signal, outputs a calculation result as an analog value after performing a product-sum operation on an input value in the analog arithmetic circuit, Further, the present invention relates to an analog / digital mixed type arithmetic circuit that performs processing by converting an output analog value into a digital value.

  Currently, computers are making great progress and are being used in various situations around the world. However, these Neumann computers are very poor at processing (such as human face recognition in real time) that can be easily performed by humans due to the characteristics of the processing method itself.

  In contrast, a neural network, which is an arithmetic processing model that imitates the information processing mode of the brain, has been studied.

  As a model of the neurons that make up the neural network, the multiplication value obtained by weighting the output values of other units (neurons) with the synaptic load value is input to the unit corresponding to the neuron, and the sum of the input values In general, a value obtained by further nonlinearly transforming is used as an output value.

  That is, in a general neural network, desired processing is realized by product-sum operation and non-linear transformation between each unit and between units.

  As a neural network architecture using this neuron model, so far associative memory in which units with non-linear input / output characteristics are connected to each other, and patterns in which units with non-linear input / output characteristics are connected in layers A recognition model has been proposed.

  Here, since the neural network is a massively parallel / distributed information processing model, execution on a Neumann computer, which is a sequential processing method, is extremely inefficient. Therefore, when a neural network is put into practical use, it is effective to make an integrated circuit as dedicated hardware.

  In addition, when integrated circuits are used, digital processing by digital circuits is suitable in terms of storage and controllability of input data, but analog arithmetic circuits are used as arithmetic circuits for realizing the product-sum operation and nonlinear conversion described above. By using it, the number of elements can be greatly reduced compared to a digital arithmetic circuit.

  That is, in practical use of neural networks, it is effective to apply a digital circuit and an analog circuit to an arithmetic processing unit in which each feature functions effectively, and finally aim for an integrated circuit in which both are mounted together.

  In that case, a digital pulse width conversion circuit, a D / A conversion circuit, an A / D conversion circuit, and the like are used in an interface unit that couples both the digital circuit and the analog circuit.

  Here, the digital pulse width conversion circuit refers to one having a function of converting a digital input value into a pulse having a time width proportional to the digital input value, and a count value and a digital input value output by a counter operated by a clock. Are well known to cause the pulse output to fall at a timing when both coincide with each other (see, for example, Patent Document 1).

  FIG. 28 is a diagram showing an example of a conventional digital pulse width conversion circuit (see FIG. 1 of Patent Document 1). The conventional digital pulse width conversion circuit shown in FIG. 28 includes a strobe detection circuit 101, a latch circuit 102, a counter 103, a digital comparator 104, and a JK flip-flop 105.

  When the strobe signal NOT (STB) is input, the strobe detection circuit 101 outputs timing enable signals E1 and E2 at the subsequent rising edge of the clock CLK. The timing enable signal E1 becomes L level at the next rising edge of the clock. On the other hand, the timing enable signal E2 is always at the H level while the clear signal NOT (reset) is at the H level.

The latch circuit 102 latches 16-bit digital data D _{0 to} D ₁₅ input from the outside, and outputs the latched data as latch data Q _{0 to} Q ₁₅ . Then, 16-bit counter 103 counts the clock CLK, and outputs the count value C ₀ -C _15. Further, the counter 103 outputs a count-out signal CO when the count value becomes FFFF.

Digital comparator 104 compares the latched data Q ₀ to Q ₁₅ and count value C ₀ -C _15, until the count value C ₀ -C ₁₅ exceeds latched data Q ₀ to Q _15, JK flip-flop outputs H level to 105, the count value C ₀ -C ₁₅ is when beyond the latched data Q ₀ to Q _15, inverts the output values to the L level.

  In the JK flip-flop 105, at the beginning of the processing cycle, the output signal of the digital comparator 104 is input to the input terminal J, and the output Q holds the H level. Further, at the rising timing of the first clock CLK after the output signal of the digital comparator 104 is inverted to the L level, the JK flip-flop 105 inverts the output Q to the L level. When the count out signal C.O. is input, the JK flip-flop 105 returns the output Q to the H level.

With such a configuration, a pulse having a time width proportional to the values of the digital data D _{0 to} D ₁₅ is output to the output Q of the JK flip-flop 105.

  As a D / A conversion circuit, a combination of the digital pulse width conversion circuit, a switched current source, and a capacitor has been conventionally used.

  That is, the digital value is converted into a pulse having a value proportional to the digital value by the digital pulse width conversion circuit. Further, the switched current source is turned on / off by the pulse, and a charge proportional to the pulse width is accumulated in the capacitor, so that the digital value is finally converted into an analog value as the voltage value of the capacitor.

  The A / D converter circuit is a combination of a comparator that converts an analog voltage into a pulse with a time width proportional to the analog voltage value, and a pulse width / digital conversion circuit that converts the time width of the pulse into a digital value. Is conventionally used.

  That is, the analog voltage value is converted into a pulse having information in the pulse width by the comparator. Further, A / D conversion is performed by converting the pulse into a digital value by a pulse width / digital conversion circuit.

  Here, the pulse width / digital conversion circuit has been widely used in integration type AD converters conventionally (see, for example, Patent Documents 2 and 3 and Non-Patent Document 1).

  FIG. 29 is a block diagram of a conventional pulse width / digital conversion circuit used in an integral AD converter.

The conventional pulse width / digital conversion circuit 111 has a simple configuration including an AND gate circuit 112 and a counter 113. The AND gate circuit 112 receives an input pulse PW that has been subjected to digital pulse width conversion and a clock CLK. The AND gate circuit 112 outputs to the counter 113 a gate signal g that is a logical product of the input pulse PW and the clock CLK. The counter 113 counts the rising edges of the input gate signal g and outputs the counted value as an m-bit digital output D = {D ₀ ,..., D _m−1 }.

With this configuration, the AND gate circuit 112 is enabled when the input pulse PW is at the H level, and the AND gate circuit 112 is disabled when the input pulse PW is at the L level. While the AND gate circuit 112 is valid, the clock CLK is output as the gate signal g. The counter 113 counts the clock output as the gate signal g. Thereby, a count value proportional to the width of the input pulse PW is obtained as a digital output D = {D ₀ ,..., D _m−1 }.
JP-A-4-2222 Japanese Patent Application Laid-Open No. 8-204466 JP-A-62-265820 Suzuki Hachiji, Yoshida Masaaki, “Introduction to Pulsed Digital Circuits”, Nikkan Kogyo Shimbun, July 26, 2001, p. 225-p. 232

  In an analog / digital mixed type arithmetic circuit, a digital / pulse width conversion circuit, a D / A conversion circuit using a digital / pulse width conversion circuit, and an A / D conversion circuit using a pulse width / digital conversion circuit are used. This is a very effective means because of its simple structure.

  However, when the digital pulse width conversion circuit is used in a device that performs digital pulse width conversion on a large number of digital input values in parallel and outputs a modulated pulse, the circuit area and power consumption operate in parallel. There is a problem that it increases in proportion to the number of digital pulse width conversion circuits.

  That is, when digital pulse width conversion is performed in parallel for a large number of digital input values, a plurality of digital pulse width conversion circuits shown in FIG. 28 are arranged in parallel, and each digital pulse width conversion circuit is arranged in each digital pulse width conversion circuit. In contrast, each digital input value may be input. Then, by extracting a pulse output from each digital pulse width conversion circuit, parallel digital pulse width conversion can be performed.

  However, in this case, in each digital pulse width conversion circuit, the circuit area increases in proportion to the number. Further, since the switching operation by the clock is frequently performed, a considerable amount of power is consumed when the driving power of all the digital pulse width conversion circuits is summed. Therefore, it is difficult to use the digital pulse width conversion of a large number of digital input values in parallel in an apparatus that requires area saving and low power consumption such as a portable device.

  Similarly, when the pulse width / digital conversion circuit is used in a device that digitally converts a large number of pulse inputs in parallel and outputs a digital value, the power consumption of each pulse width / digital conversion circuit 111 There is the problem that the sum of

  That is, when the pulse width / digital conversion circuit 111 as shown in FIG. 29 is used for each pulse input, a large number of counters 113 perform switching operations in parallel. Therefore, for example, even when the counter 113 is composed of CMOS, the charge / discharge power consumption when the counter 113 charges / discharges the load capacity during switching increases. This increase in charge / discharge power consumption becomes more significant as the number of pulse inputs increases.

  In addition, since many counters 113 operate in parallel, the switching noise of the counter 113 increases. Therefore, noise countermeasures for the entire circuit are required.

  Accordingly, an object of the present invention is to provide a digital pulse width conversion circuit that converts a plurality of digital input values into a pulse width in parallel with a small area and low power consumption, and operates with low power consumption, and noise generated from the circuit is small. An object is to provide an analog / digital mixed arithmetic circuit using a pulse width / digital conversion circuit.

  In order to achieve the above object, according to the present invention, a plurality of analog arithmetic circuits that perform arithmetic processing on information represented by an analog signal and an arithmetic circuit that calculates an accumulated value of arithmetic results obtained by parallel arithmetic processing, A capacitor for accumulating the sum of the calculation results of the plurality of analog arithmetic circuits as a charge amount, a comparator for converting the charge amount accumulated in the capacitor into a pulse signal having a corresponding pulse width, and digitally converting the pulse signal A pulse width / digital conversion circuit that converts the signal into a signal, and a digital arithmetic circuit that calculates an accumulated value based on the converted digital signal. A counter that outputs a numerical value as a digital signal and a common counter that the counter outputs at the end of each pulse signal that is input to each counter And having a plurality of end latch circuit for latching the value.

  According to another aspect of the present invention, in an operation control method for an arithmetic circuit that calculates an accumulated value of arithmetic results obtained by parallel arithmetic processing, information represented by an analog signal is arithmetically processed by a plurality of analog arithmetic circuits. An analog operation step, an accumulation step of accumulating the total value of the operation results of the analog operation step as a charge amount in a capacitor, and a voltage pulse conversion for converting the amount of charge accumulated in the capacitor into a pulse signal having a corresponding pulse width A pulse width / digital conversion step for converting the pulse signal into a digital signal, and an addition step for calculating an accumulated value based on the converted digital signal, the pulse width / digital conversion step, Counting the clock with a counter and outputting the count value as a digital signal, and input to each by multiple termination latch circuits Characterized by a step of the counter at the end of each pulse signal latches a common count value to be output to.

  According to the present invention, it is possible to realize an arithmetic circuit that calculates an accumulated value of calculation results subjected to parallel arithmetic processing with a small area and low power consumption.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is an overall configuration diagram of an analog / digital mixed arithmetic circuit 100 according to this embodiment.

  As shown in FIG. 1, the analog / digital mixed arithmetic circuit includes a digital memory 1, a digital / pulse width conversion circuit 2, an analog arithmetic circuit 3, and a capacitor 4.

  The analog / digital mixed operation circuit 100 realizes a function of calculating an accumulated value of a plurality of multiplication results.

  FIG. 2 illustrates in detail the configuration of the analog arithmetic circuit 3 and the capacitor 4 shown in FIG. As shown in FIG. 2, the analog arithmetic circuit 3 and the capacitor 4 in this embodiment are configured such that a plurality of analog arithmetic circuits 3 are connected in parallel to a bus connected to the capacitor 4.

  FIG. 3 shows a detailed circuit configuration of the analog arithmetic circuit 3 in the present embodiment. As shown in FIG. 3, the analog arithmetic circuit 3 in this embodiment has one PMOS transistor M1 that functions as a constant current source.

  FIG. 4 is a block diagram showing the configuration of the digital pulse width conversion circuit in the present embodiment. FIG. 5 is a block diagram showing the configuration of each pulse generation circuit in FIG. FIG. 6 is a timing chart showing the operation of the digital pulse width conversion circuit in this embodiment. Here, first, a process of converting digital data held in the memory into a pulse signal will be described with reference to FIGS. 4, 5, and 6.

  3 will be used to explain the arithmetic processing process of the analog arithmetic circuit 3, and then FIG. 2 will be used to explain how the arithmetic result of the analog arithmetic circuit 3 is held in the capacitor 4 as a partial sum. Further, how to calculate a desired accumulated value from the partial sum will be described with reference to FIG.

  As shown in FIG. 1, first, the digital value of the multiplied value A held in the digital memory 1 is inputted to the digital pulse width conversion circuit 2. The digital / pulse width conversion circuit 2 converts the input digital value into a pulse signal having a time width proportional to the digital input value and outputs the pulse signal.

Here, as shown in FIG. 4, the digital pulse width conversion circuit 2 according to the present embodiment includes a plurality of pulse generation circuits 10-0 to 10-(n−1) arranged in parallel and one counter 11. Have. The data input terminal Din of the pulse generating circuit 10-0~10- (n-1), each of the digital input values of m bits x ₀ ~x _n-1 are inputted. Then, from the pulse output terminal Pout of the pulse generating circuit 10-0~10- (n-1), PWM signal PWM ₀ ~PWM _n-1 is output proportional to the digital input value x ₀ ~x _n-1 Is done.

  The counter 11 counts a clock clock input from the outside and outputs it as an m-bit count value. This clock clock is also input in common to the clock input terminals clk of the pulse generation circuits 10-0 to 10- (n-1). The counter value output from the counter 11 is commonly input to the counter value input terminals CNT of the pulse generation circuits 10-0 to 10- (n-1).

Further, the m-bit reference value _xb is commonly input to the reference value input terminal Db of each of the pulse generation circuits 10-0 to 10- (n-1). This reference value _xb is a value that specifies the rising timing of the output PWM signals PWM _{0 to} PWM _n−1 .

  FIG. 5 is a block diagram showing the configuration of each pulse generation circuit of FIG. The pulse generation circuit 10-i (i∈ {0, 1,..., N−1}) includes a reference value register 12, an addition / subtraction circuit 13, a pulse width register 14, a switching circuit 15, a timing trigger generation circuit 16, and an output pulse. An inverting circuit 17 is provided.

Reference value register 12 latches the reference value x _b, and outputs the value of the reference value x _b was latched. The addition / subtraction circuit 13 outputs an addition value x _i + x _b between the reference value x _b and an input value x _i which is a digital value input from the outside. The pulse width register 14 latches the output value (addition value x _i + x _b ) of the addition / subtraction circuit 13 at the rising edge of the update input renew.

When the output PWM signal PWM _i output from the output pulse inversion circuit 17 is a false value (L level), the switching circuit 15 outputs the digital value _xb latched by the reference value register 12, and the output pulse inversion circuit 17 When the output PWM signal PWM _i to be output is a true value (H level), switching is performed so that the digital value x _i + x _b latched by the pulse width register 14 is output.

The timing trigger generation circuit 16 compares each bit of the digital value output from the switching circuit 15 with each bit of the count value CNT output from the counter 11, and generates a trigger when the two match completely. . The timing trigger generation circuit 16 includes m EXOR gates 18-0 to 18- (m-1) and one NOR gate 19. An output bit from the switching circuit 15 is input to one of the inputs of each EXOR gate 18-0 to 18- (m-1), and an output bit from the counter 11 is input to the other input. . The outputs P _{0 to} P _m-1 of the EXOR gates 18-0 to 18- (m-1) are input to the NOR gate 19. The NOR gate 19 outputs an inverted output of the logical sum of the outputs P _{0 to} P _m−1 of the EXOR gates 18-0 to 18- (m−1) to the output pulse inversion circuit 17.

That is, each digital input value x _i (i∈ {0, 1,..., N−1}), each reference value x _b , and the output value CNT of the counter are expressed by equations (1), (2), and (3), respectively. In this case, the output T _i of the timing trigger generation circuit 16 is expressed by equation (4) when the output value Pout of the output pulse inverter 17 is L level, and when the output value Pout of the output pulse inverter 17 is H level. It is expressed as equation (5).

x _i = (x _{i, 0} , x _{i, 1} , ..., x _{i, m-1} ) (1)
x _b = (x _{b, 0} , x _{b, 1} , ..., x _{b, m-1} ) (2)
CNT _i = (CNT _{i, 0} , CNT _{i, 1} , ..., CNT _{i, m-1} ) (3)

（4）

(Four)

（5）

(Five)

Output pulse inverting circuit 17, when the timing trigger generation circuit 16 has generated the trigger, to reverse the truth value of the output PWM signal PWM _i. The output pulse inverting circuit 17 is constituted by a synchronous T flip-flop (hereinafter referred to as “T-FF”). The output value from the NOR gate 19 is input to the trigger input terminal T of the output pulse inverting circuit 17. A common clock clock is input to the clock terminal clk of the T-FF. The output PWM signal PWM _i is output from the output terminal Q of the output pulse inverting circuit 17.

  The operation of the digital pulse width conversion circuit according to this embodiment configured as described above will be described below with reference to the timing chart of FIG.

First, at time t ₁ , the input value x _i and the reference value x _b are input from the external circuit to each pulse generation circuit 10-i. Then, update signal renew is input to the reset input node R and the clock input node CLK of the reference value register 12 and the pulse width register 14 of each pulse generator circuit 10-i of the counter 11 at time t _2. Reference value register 12 and the pulse width register 14, the update signal renew is input at the rising time, respectively, to latch the value of the reference value x _b and the input value x _i of that time. The reference value register 12 outputs the latched reference value _xb , and the pulse width register 14 outputs the latched addition value x _i + _xb .

On the other hand, at time t _1, the output of the output pulse inverting circuit is the L level, the switching circuit 15 outputs the value x _b input from the reference value register 12. Further, the counter 11 resets the count value CNT to 0 and starts counting at the rising edge of the update signal renew.

Then, the counter 11 counts up the count value CNT of the counter 11 at time t ₃ coincides with the reference value x _b is the output value of the switching circuit 15. At this time, the output T _i of the timing trigger generation circuit 16 is inverted to H level. As a result, the output Pout of the output pulse inverting circuit 17 is inverted from the L level to the H level, and the output of the output PWM signal PWM _i is started.

At time t _4, the output Pout of the output pulse inversion circuit 17 Invert the H level, the switched input of the switching circuit 15, so outputs a value x _{b +} x _i input from the pulse width register 14. As a result, the output values of the EXOR gates 18-0 to 18- (m-1) also change. If x _i ≠ 0, the output values of the EXOR gates 18-0 to 18- (m-1) It will never be zero. Accordingly, the output T _i of the timing trigger generation circuit is inverted to the L level.

Further counter 11 is counted up at time t _5, the count value CNT of the counter 11 coincides with the addition value x _{b +} x _i is an output value of the switching circuit 15. At this time, the output T _i of the timing trigger generation circuit 16 is inverted to H level. As a result, the output Pout of the output pulse inverting circuit 17 is inverted from the H level to the L level, and the output of the output PWM signal PWM _i is stopped. In this way, the output PWM signal PWM _i proportionate time width to the digital input value x _i is generated, the digital pulse width conversion is performed.

At time t _6, the output of the output pulse inversion circuit 17 Invert the L level, switches the input of the switching circuit 15, switching circuit 15 is to output a value x _b input from the reference value register 12. As a result, the output values of the EXOR gates 18-0 to 18- (m-1) also change. If x _i ≠ 0, the output values of the EXOR gates 18-0 to 18- (m-1) It will never be zero. Accordingly, the output T _i of the timing trigger generation circuit is inverted to the L level.

The counter 11 continues counting until it counts up. During this time, since the counter value and the output value _xb of the switching circuit do not match, the output of the output pulse inverting circuit 17 is held at the L level. When the counter 11 counts up, the counting is stopped and one cycle is completed. After counting up, the counter 11 maintains the output values (all at H level) when counting up until the reset input node R is inverted to H level again.

As described above, each pulse generation circuit 10-i outputs the output PWM signal PWM _i having a time width proportional to the value of the input value x _i . In this case, the pulse generating circuits 10-i, using the count value common counter 11 outputs, and compares the reference value x _b or the sum x _{b +} x _i. Therefore, compared with the case where all the pulse generation circuits 10-i are provided with a counter, the power consumption is extremely small, so that the power consumption of the digital pulse width conversion circuit can be reduced.

Further, in the present embodiment, the reference value register 12, the pulse width register 14, and the switching circuit 15 are used, and the rising and falling timings of the output PWM signal PWM _i are determined using the common timing trigger generation circuit 16. With the configuration of generating, the pulse width of the output PWM signal PWM _i can be accurately proportional to the input value x _i without being affected by the circuit delay.

In the present embodiment, the reference value x _b, although the configuration example to align the rising edge of the output pulses in each pulse generator 10-0~10- (n-1), in the present invention, the output It is good also as a structure which matches the falling point of a pulse. In this case, addition and subtraction circuit 13, and configured to output a subtracted value x _b -x _i of an input value x _i from the reference value x _b is a digital value input from the outside is subtracted. The switching circuit 15 outputs the digital value _xb latched by the reference value register 12 when the output PWM signal PWM _i output from the output pulse inversion circuit 17 is a true value (H level), and outputs the output pulse inversion circuit. When the output PWM signal PWM _i output from 17 is a false value (L level), the pulse width register 14 may be switched so as to output the digital value x _b −x _i latched.

Note that without providing the adding and subtracting circuit 11 in the pulse generating circuit 2-i, as a digital input signal x _i, may be given the result of the addition or subtraction from the reference value x _b the original input values.

  Subsequently, the analog arithmetic circuit shown in FIG. 3 realizes multiplication (A × B) of the multiplied value A and the multiplied value B in the present embodiment. (Note that A and B satisfy A ≧ 0 and B ≧ 0.) Here, the multiplied value A and the multiplied value B are the digital signals described above in order to realize the multiplication by the analog arithmetic circuit 3. The PWM signal PWM5 output from the pulse width conversion circuit 2 and the analog voltage Vw6 are input.

  The analog operation circuit 3 may be another analog operation circuit as long as it performs some operation (for example, non-linear conversion or the like) other than the one that realizes the multiplication.

  First, in FIG. 3, the PWM signal PWM5 output from the digital pulse width conversion circuit is input to the input terminal 7, and the analog voltage Vw6 obtained by performing a predetermined conversion on the multiplication value B is input to the input terminal 8.

  Here, the characteristics of the PWM signal will be briefly described. A pulse signal PWM (Pulse Width Modulation) is a modulation method in which information is provided in the width of a pulse waveform, and has a digital characteristic that is resistant to noise (a characteristic that binary information of High level and Low level is included in the voltage direction) ) And analog characteristics (characteristic of having continuous information in the time direction) that can express continuous information with one pulse.

  A voltage of Vw6 corresponding to the multiplication value B input to the input terminal 8 is applied to the gate terminal of M1. The PWM signal PWM5 is input from the input terminal 7 to the source terminal of M1. In the PWM signal, the Low level is set to 0 V, and the High level is set to the power supply voltage Vdd (3.3 V in this embodiment).

  Here, when the PWM signal is at a high level, that is, when Vdd is applied to the source terminal of M1, by setting the analog voltage Vw6 to an appropriate voltage range so that M1 operates in the saturation region, the PWM signal becomes During the high level, M1 can be operated as a constant current source.

  At this time, the amount of current flowing through M1 is determined by the gate-source voltage, that is, (Vdd-Vw). At this time, the pulse width of the PWM signal PWM5 is converted to be proportional to the multiplied value A. The analog voltage Vw6 is converted so that the amount of current determined by (Vdd−Vw) is proportional to the multiplication value B.

  Therefore, since M1 passes a current determined by (Vdd−Vw) only while the PWM signal is at a high level, the total amount of charge that M1 flows while the PWM signal is at a high level is proportional to A × B. It becomes. Other analog arithmetic circuits may be used as long as the multiplication can be realized using a PWM signal.

  Next, how the calculation result by the analog calculation circuit 3 is held in the capacitor 4 will be described with reference to FIG. In FIG. 2, the amount of charge that M1 flows as described above is stored in the capacitor 4 connected to the analog arithmetic circuit 3 by the bus.

  Here, since a plurality of analog arithmetic circuits 3 that perform arithmetic operations independently from each other are connected to the bus, the arithmetic results executed in parallel by each analog arithmetic circuit 3, that is, the charge amount described above is It is stored in the capacitor 4 through the bus and added.

  Therefore, the total amount of electric charge accumulated in the capacitor 4 every time one parallel arithmetic process is completed indicates the sum of the arithmetic results of the plurality of analog arithmetic circuits 3 connected to the capacitor 4 through a common bus. Yes.

  Next, the above arithmetic processing flow will be described with reference to the flowchart of FIG. In the description, an arithmetic circuit that executes each processing step is also referred to.

  In FIG. 7, first, a digital signal input step S1 is executed, and then, in each digital pulse width conversion circuit, a step S5 for converting the digital signal into a PWM signal is executed. Next, Bi (voltage Vw) input step S2 is executed, and in each analog arithmetic circuit, step S3 of multiplying the PWM signal output from step S5 by the analog voltage Vw is executed. Next, step S4 is performed in which the multiplication values calculated in parallel in the respective analog arithmetic circuits are accumulated as charge amounts in the capacitors and are held as partial sums Σ (Ai × Bi).

  A desired accumulated value is calculated by repeating the operation flow described above as many times as necessary for calculating the accumulated value (three times in the present embodiment).

  The calculation flow may be repeated a plurality of times as necessary, and the calculation result may be additionally accumulated as a charge in the capacitor (in FIG. 7, S4 is a partial sum calculation, but the calculation result is In the case of additional accumulation as charge in the capacitor, the amount of charge corresponding to the finally calculated accumulated value is accumulated in the capacitor).

  Alternatively, the calculation result once stored as a charge in the capacitor may be stored in another storage circuit, and then the calculation flow may be newly performed.

  As described above, by using a digital pulse width conversion circuit that converts multiple digital input values into pulse widths in parallel with low power consumption, low power consumption and a small layout area can be combined. An arithmetic circuit can be realized.

(Second embodiment)
The analog / digital mixed arithmetic circuit in this embodiment is different from the analog / digital mixed arithmetic circuit in the first embodiment only in the digital pulse width conversion circuit. Accordingly, only the digital pulse width conversion circuit different from that of the first embodiment will be described below, and the other parts are the same as those of the first embodiment, and the description thereof will be omitted.

Here, as shown in FIG. 30, the digital pulse width conversion circuit 51 according to this embodiment includes a plurality of pulse generation circuits 52-0 to 52-(n−1) arranged in parallel, and one counter 53. Have. The data input terminal Din of the pulse generating circuit 52-0~52- (n-1), each of the digital input values of m bits x ₀ ~x _n-1 are inputted. Then, the pulse from the output terminal Pout, pulse PWM ₀ ~PWM _n-1 time width proportional to the digital input value x ₀ ~x _n-1 of each pulse generating circuit 52-0~52- (n-1) Is output. The counter 53 counts the clock clock input from the outside and outputs it as an m-bit count value. In addition, the count value output from the counter 53 is commonly input to the counter value input terminals CNT of the pulse generation circuits 52-0 to 52- (n-1).

FIG. 31 is a block diagram showing the configuration of each pulse generation circuit of FIG. The pulse generation circuit 52-i (i∈ {0, 1,..., N−1}) includes a pulse width register 62, a timing trigger generation circuit 64, and an output pulse inversion circuit 65. Pulse width register 62 latches the rising of the input value x _i update input renew an m-bit digital value input from the outside, and outputs the value to the output node. The timing trigger generation circuit 64 compares each bit of the m-bit digital value output from the pulse width register 62 with each bit of the m-bit count value output from the counter 53, and the two match completely. When trigger occurs.

The timing trigger generation circuit 64 includes m EXOR gates 66-0 to 66- (m-1) and one NOR gate 67. An output bit from the pulse width register 62 is input to one of the inputs of each EXOR gate 66-0 to 66- (m−1), and an output bit from the counter 53 is input to the other input. The The outputs P _{0 to} P _m−1 of the EXOR gates 66-0 to 66- (m−1) are input to the NOR gate 67. The NOR gate 67 outputs an inverted output of the logical sum of the outputs P _{0 to} P _m−1 of the EXOR gates 66-0 to 66- (m−1) to the output pulse inversion circuit 65.

That is, when each digital input value x _i (i∈ {0, 1,..., N−1}) and the counter output value CNT are expressed by the equations (1) and (3), the output of the timing trigger generation circuit 64 T _i is expressed as in Equation (6). Here, it is assumed that x _i is not 0.

（6）

(6)

From Expression (6), it can be seen that the output T _i of the timing trigger generation circuit 64 becomes 1 when the digital input value x _i and the output value CNT of the counter match in all bits. The output pulse inversion circuit 65 inverts the truth value of the output pulse PWM _i when the timing trigger generation circuit 64 generates a trigger. The output pulse inversion circuit 65 is constituted by a T flip-flop (hereinafter referred to as “T-FF”). The output value from the NOR gate 67 is input to the trigger input terminal T of the output pulse inverting circuit 65. The pulse PWM _i is output from the output terminal Q of the output pulse inverting circuit 65.

  The operation of the digital pulse width conversion circuit according to this embodiment configured as described above will be described below with reference to the timing chart of FIG.

First, in the initial state immediately after the power is turned on, it is assumed that all the count values CNT of the counter 53 are at the H level and the input value x _i is 0. In this state, at time t ₀ , the reset input reset input to the counter 53 and the pulse width register 62 is made valid (L level). As a result, all the count values CNT of the counter 53 are reset to zero. The pulse width register 62 resets all stored values to 0 when the reset signal reset is set to L level. Then, the output value of the count value CNT and the pulse width register 62 of the counter 53 and the match, the output T _i of the timing trigger generation circuit 64 is inverted from L level to H level. Accordingly, the output Pout _i of the output pulse inverting circuit 65 is inverted to H level, and a pulse starts to be output to the output Pout _i .

Next, at time t _1, for each pulse generating circuit 52-i, the input value from the external circuit _{x i (X i ≠ (0,0} , ..., 0)) is input. At this time, since the reset signal reset input to the pulse width register 62 is at the L level, all outputs of the pulse width register 62 remain zero.

Then, at time t _2, the the reset input reset is disabled (H level), the update signal renew is inverted from L level to H level. The update signal renew is input to the clock CLK input node of each pulse width register 62. When the update signal renew is inverted to the H level, the pulse width register 62 latches the value of the input value x _i at that time. . Accordingly, the output value of the pulse width register 62 is the input value x _i. On the other hand, since the count value CNT of the counter 53 is still 0, the output of the pulse width register 62 and the count value CNT of the counter 53 do not match, and the output T of the timing trigger generation circuit 64 is inverted from H level to L level. The counter 53 starts counting the clock clock when the reset signal reset is inverted from the L level to the H level. At this time, the pulse width register 62 continues to output the latched sum value x _i.

The counter 53 counts up with the clock clock, and the count value CNT of the counter 53 coincides with x _i that is the output value of the switching circuit 63 at time t ₃ . At this time, the output value T of the timing trigger generation circuit 64 is inverted from the L level to the H level. As a result, the output Pout _i of the output pulse inverting circuit 65 is inverted from the H level to the L level. Thereby, the width of the pulse PWM _i of the output Pout _i of the output pulse inverting circuit 65 is determined. Since this pulse width is proportional to the digital input value x _i , digital pulse width conversion is performed.

Further, at time t ₄ when the time t ₃ has elapsed one clock, the counter 53 count CNT of counting up the counter 53 becomes the output value x _i and mismatch of the switching circuit 63, the output T of the timing trigger generation circuit 64 _i is inverted from H level to L level.

The counter 53 continues counting until it counts up. During this time, the count value CNT of the counter 53 and the input value x _i do not match, so the output T _i of the timing trigger generation circuit 64 holds the L level and the output of the output pulse inversion circuit 65 also holds the L level. Is done. When the counter 53 counts up, all count values of the counter 53 become 0, and one cycle is completed. Subsequently, the same cycle is repeated.

As described above, each pulse generation circuit 52-i (i = 0,..., N−1) outputs the output pulse PWM _i having a time width proportional to the input value x _i . (However, this time width is strictly offset by 2 clocks during the period when the reset signal is L. This can be dealt with by subtracting 2 from x _{i in} advance.)

In this case, the pulse generating circuits 52-i, using the count value CNT to a common counter 53 outputs, and compares the digital input value x _i. Therefore, the power consumption is extremely small as compared with the case where all the pulse generation circuits 52-i are provided with counters. That is, when all the pulse generation circuits 52-i are provided with counters, at least one of the switching elements in each counter is switched every clock. Therefore, for example, when a CMOS is used as the switching element, a through current and a charge / discharge current to the load flow along with the switching. Therefore, the power consumption of the entire digital pulse width conversion circuit is increased.

  On the other hand, as in the present embodiment, when one counter 53 is driven and each pulse generation circuit 52-i refers to the output value of the common counter 53 to switch the pulse, There are few through currents and charge / discharge currents to the load caused by switching of the switching elements, and power consumption is also small. Therefore, the power consumption of the digital pulse width conversion circuit 51 can be reduced. Since the counter 53 is shared, the circuit layout area is reduced, and the digital pulse width conversion circuit 51 can be downsized.

(Third embodiment)
FIG. 8 shows a configuration example of an analog / digital mixed arithmetic circuit 200 according to the third embodiment.

  As can be seen from FIG. 8, in the analog / digital mixed arithmetic circuit 100 described in the first and second embodiments, the present embodiment includes a digital memory 20 and a D memory in front of each analog arithmetic circuit 3. The difference between the first and second embodiments is that the / A conversion circuit 300 is added.

  Therefore, in the description of the present embodiment, only the processing of the D / A conversion circuit 300 different from the first and second embodiments will be described, and the other processing is the same as in the first and second embodiments. Description is omitted.

  As shown in FIG. 9, the D / A conversion circuit 300 includes a digital pulse width conversion circuit 21, a current source 22, a capacitor 23, and a buffer 24. Regarding the processing of the D / A conversion circuit 300, the processing performed in parallel in the digital / pulse width conversion circuit 21 is the same as that in the first and second embodiments, and thus the description thereof is omitted.

  As shown in FIG. 9, first, in the D / A conversion circuit 300, a digital value corresponding to the multiplication value B is input from the digital memory to the digital / pulse width conversion circuit 21. The digital pulse width conversion circuit 21 to which the digital value is input performs the same processing as in the first and second embodiments and outputs a PWM signal. Subsequently, the PWM signal controls the on / off operation of the current source 22, respectively.

  That is, in the present embodiment, the current source 22 is turned on while the PWM signal is High, and a predetermined current flows into the capacitor 23. Further, during the period when the PWM signal is low, the current source 22 is turned off, and the current flow into the capacitor 23 is stopped. As a result, the capacitor 23 accumulates a charge amount proportional to the time width of each PWM signal. In the capacitor 23, the accumulated charge amount can be referred to as a voltage value via the buffer 24, so that it is input as an analog voltage value corresponding to the multiplication value B to the analog arithmetic circuit as shown in FIG. .

  Next, the above arithmetic processing flow will be described with reference to the flowchart of FIG.

  In FIG. 10, first, the input step S1 of the digital signal Ai is executed, and then the step of converting the digital signal into a PWM signal is executed in each digital pulse width conversion circuit. Next, the input step S6 of the digital signal Bi (voltage Vw) is executed, and then the D / A conversion step S7 for converting the digital signal into an analog signal is executed in the D / A conversion circuit.

  Subsequently, in each analog arithmetic circuit, step S3 for multiplying the PWM signal, which is the output from steps S5 and S7, and the analog voltage Vw is executed. Next, step S4 is performed in which the multiplication values calculated in parallel in the respective analog arithmetic circuits are accumulated as charge amounts in the capacitors and are held as partial sums Σ (Ai × Bi).

  A desired accumulated value is calculated by repeating the operation flow described above as many times as necessary for calculating the accumulated value (three times in the present embodiment).

  The calculation flow may be repeated a plurality of times as necessary, and the calculation result may be additionally accumulated as a charge in the capacitor (in FIG. 10, S4 is a partial sum calculation. In the case of additional accumulation as charge in the capacitor, the amount of charge corresponding to the finally calculated accumulated value is accumulated in the capacitor). Alternatively, the calculation result once stored as a charge in the capacitor may be stored in another storage circuit, and then the calculation flow may be newly performed.

  As described above, by using a digital pulse width conversion circuit that converts multiple digital input values into pulse widths in parallel with low power consumption in the D / A converter circuit, low power consumption and a small layout area It is possible to realize a digital mixed type arithmetic circuit.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described in detail with reference to the drawings. FIG. 11 is an overall configuration diagram of an analog / digital mixed arithmetic circuit 400 according to this embodiment.

  As shown in FIG. 11, the analog / digital mixed type arithmetic circuit includes a plurality of analog arithmetic circuits 3, a capacitor 4 connected to the plurality of analog arithmetic circuits 3, a comparator 28 shown in FIG. An A / D conversion circuit 500 including a circuit 29, a digital addition circuit 25, and a digital memory 26 are included. This analog / digital mixed arithmetic circuit 400 realizes a function of calculating an accumulated value of a plurality of multiplication results.

  FIG. 2 illustrates in detail the configuration of the analog arithmetic circuit 3 and the capacitor 4 shown in FIG. As shown in FIG. 2, the analog arithmetic circuit 3 and the capacitor 4 in this embodiment are configured such that a plurality of analog arithmetic circuits 3 are connected in parallel to a bus connected to the capacitor 4.

  FIG. 3 shows a detailed circuit configuration of the analog arithmetic circuit 3 in the present embodiment. As shown in FIG. 3, the analog arithmetic circuit 3 in this embodiment has one PMOS transistor M1 that functions as a constant current source.

  FIG. 12 illustrates the configuration of the A / D conversion circuit 500 in the present embodiment. FIG. 13 is a block diagram showing the configuration of the pulse width / digital conversion circuit 29 constituting the A / D conversion circuit 500. FIG. 14 is a block diagram showing the internal configuration of the termination latch circuits 32-1 to 32- (n-1) in the pulse width / digital conversion circuit 29. FIG. 15 is a block diagram showing an internal configuration of the latch circuits 33-0 to 33- (n-1). FIG. 16 is a time chart showing changes in each signal level of the pulse width / digital conversion circuit 29.

  Here, the arithmetic processing process of the analog arithmetic circuit 3 will be described first with reference to FIG. 3, and then how the arithmetic operation result by the analog arithmetic circuit 3 will be held in the capacitor 4 as a partial sum with reference to FIG. Next, how to calculate a desired accumulated value from a partial sum will be described with reference to FIG. Subsequently, the processing steps of the A / D conversion circuit 500 will be described in more detail with reference to FIGS. 13, 14, 15, and 16.

  The analog arithmetic circuit 3 shown in FIG. 3 realizes multiplication (A × B) of the multiplied value A and the multiplied value B in this embodiment. A and B satisfy A ≧ 0 and B ≧ 0.

  Here, the multiplied value A and the multiplied value B are respectively input as a PWM signal PWM5 subjected to predetermined conversion and an analog voltage Vw6 as will be described later in order to realize the multiplication by the analog arithmetic circuit 3.

  The PWM signal and the analog voltage input to the analog arithmetic circuit 3 can be input by an external power supply device as necessary. For example, as described in the first, second, and third embodiments. Similar to the input process of the PWM signal and the analog voltage, the digital value can be converted and input.

  In the present embodiment, it is assumed that the PWM signal and the analog voltage are input in the same manner as the input process described in the first, second, and third embodiments. The description is the same as that in the second and third embodiments. The analog arithmetic circuit 3 may be another analog arithmetic circuit as long as it performs some arithmetic (for example, non-linear conversion) other than the one that realizes the multiplication.

  First, in FIG. 3, a PWM signal PWM5 obtained by performing a predetermined conversion on the multiplied value A is input to the input terminal 7, and an analog voltage Vw6 obtained by performing a predetermined conversion on the multiplied value B is input to the input terminal 8.

  A voltage of Vw6 corresponding to the multiplication value B input to the input terminal 8 is applied to the gate terminal of M1. The PWM signal PWM5 is input from the input terminal 7 to the source terminal of M1. In the PWM signal, the Low level is set to 0 V, and the High level is set to the power supply voltage Vdd (3.3 V in this embodiment).

  Here, when the PWM signal is at a high level, that is, when Vdd is applied to the source terminal of M1, by setting the analog voltage Vw6 to an appropriate voltage range so that M1 operates in the saturation region, the PWM signal becomes During the high level, M1 can be operated as a constant current source.

  At this time, the amount of current flowing through M1 is determined by the gate-source voltage, that is, (Vdd-Vw). At this time, the pulse width of the PWM signal PWM5 is converted to be proportional to the multiplied value A. The analog voltage Vw6 is converted so that the amount of current determined by (Vdd−Vw) is proportional to the multiplication value B.

  Therefore, since M1 passes a current determined by (Vdd−Vw) only while the PWM signal is at a high level, the total amount of charge that M1 flows while the PWM signal is at a high level is proportional to A × B. It becomes.

  Next, how the calculation result by the analog calculation circuit 3 is held in the capacitor 4 as a partial sum will be described with reference to FIG. In FIG. 2, the amount of charge that M1 flows as described above is stored in the capacitor 4 connected to the analog arithmetic circuit 3 by the bus.

  Here, since a plurality of analog arithmetic circuits 3 that perform arithmetic operations independently are connected to the bus, the arithmetic result executed in parallel by each analog arithmetic circuit, that is, the charge amount described above is Is accumulated in the capacitor 4 and added.

  Therefore, the total amount of electric charge accumulated in the capacitor 4 every time one parallel arithmetic process is completed indicates the sum of the arithmetic results of the plurality of analog arithmetic circuits 3 connected to the capacitor 4 through a common bus. Yes. As will be described later, this total value corresponds to a partial sum of accumulated values to be finally calculated.

  Other analog arithmetic circuits may be used as long as the multiplication can be realized using a PWM signal.

  Next, a process of calculating a desired accumulated value from the partial sum will be described with reference to FIG.

  In the present embodiment, it is assumed that a desired accumulated value is represented by the following arithmetic expression (7).

(7)

(7)

  On the other hand, in order to obtain the final accumulated value, a configuration in which the four analog arithmetic circuits 3 shown in FIG. 2 are connected to the capacitor 4 via the bus is used. At this time, even if the total number of operations (12 in this embodiment) is not a multiple of the number of analog operation circuits (4), the analog voltage Vw6 corresponding to the multiplication value B = 0 is input. The number of operations can be adjusted.

  Here, as described with reference to FIG. 2, the calculation represented by the following calculation expression (8) is performed in parallel by the four analog calculation circuits 3, and the calculation result is held in the capacitor 4 as a charge amount. .

(8)

(8)

  The calculation result here can be regarded as a partial sum for a desired calculation (calculation expression (7)).

  Subsequently, the calculation result held in the capacitor 4 in an analog manner as the charge amount is converted into a digital value by the A / D conversion circuit 500. Further, the digital addition circuit 25 adds the digital value to the digital value stored in the digital memory 26 and holds the calculation result in the digital memory 26.

  Since the above calculation is the first partial sum calculation for the desired calculation (calculation expression (7)), there is no partial sum held in advance in the digital memory 26 and all 0s are held. Yes. Accordingly, the digital value held in the digital memory 26 here is equal to the calculation result of the calculation formula (8).

  Subsequently, the second partial sum operation is performed by the analog operation circuit 3 in the same manner as described above. That is, as described with reference to FIG. 2, the four analog operation circuits 3 perform the operation represented by the following operation expression (9) in parallel, and the operation result is held in the capacitor 4 as a charge amount.

(9)

(9)

  The calculation result here can be regarded as a partial sum for a desired calculation (calculation expression (7)).

  Subsequently, the calculation result held in the capacitor 4 in an analog manner as the charge amount is converted into a digital value by the A / D conversion circuit 500.

  Further, the digital addition circuit 25 adds the digital value to the digital value stored in the digital memory 26 and holds the calculation result in the digital memory 26.

  Here, since the digital value held in advance in the digital memory 26 corresponds to the calculation result of the calculation formula (8), the result of adding the calculation result of the calculation formula (9) and storing it in the digital memory 26 is Is expressed by the following arithmetic expression (10).

(10)

(Ten)

  Subsequently, the calculation of the third partial sum is performed by the analog arithmetic circuit 3 as described above. That is, as described with reference to FIG. 2, the four analog arithmetic circuits 3 perform the operation represented by the following arithmetic expression (11) in parallel, and the operation result is held in the capacitor 4 as a charge amount.

(11)

(11)

  The calculation result here can be regarded as a partial sum for a desired calculation (calculation expression (7)).

  Subsequently, the calculation result held in the capacitor 4 in an analog manner as the charge amount is converted into a digital value by the A / D conversion circuit 500.

  Further, the digital addition circuit 25 adds the digital value to the digital value stored in the digital memory 26 and holds the calculation result in the digital memory 26.

  Here, since the digital value previously held in the digital memory 26 corresponds to the calculation result of the calculation formula (10), the result of adding the calculation result of the calculation formula (11) and storing it in the digital memory 26 is As shown by the following arithmetic expression (12), a desired accumulated value is obtained.

(12)

(12)

  As described above, a plurality of multiplications are performed in an analog manner by the analog arithmetic circuit 3, and the respective results are added in an analog manner by the capacitor 4 to calculate a partial sum for a desired accumulated value.

  Further, after the partial sum calculated as described above is converted into digital data by the A / D converter 500, the digital addition circuit 25 digitally adds the digital sum to the value held in the digital memory 26, thereby performing a desired calculation. Realize.

  Next, processing performed in the A / D conversion circuit 500 will be described in detail.

  As shown in FIG. 12, the A / D conversion circuit 500 includes a comparator 28 and a pulse width / digital conversion circuit 29. The calculation result stored as electric charge in the capacitor 4 is referred to as a voltage value in the capacitor 4. Here, the voltage value is input to the comparator 28 and compared with an arbitrary voltage waveform separately input in the comparator 28.

  Here, the arbitrary voltage waveform may be the ramp voltage waveform 27 in which the voltage value rises linearly, or may be another nonlinear voltage waveform. In the case of the ramp voltage waveform 27 used in the present embodiment, the calculation result stored in the capacitor is linearly converted to set the PWM signal width. In the case of other nonlinear voltage waveforms, the calculation result stored in the capacitor is nonlinearly converted to set the PWM signal width.

  That is, the output value of the comparator 28 rises to a high level at the start of the ramp voltage waveform 27 and falls to a low level when the ramp voltage value 27 and the voltage value of the capacitor 4 become equal, thereby being converted into a PWM signal.

  The conversion process of the analog voltage into the PWM signal by the comparator 28 is a generally well-known technique and is not the main point of the present invention. Subsequently, the PWM signal output from the comparator 27 is input to the pulse width / digital conversion circuit 29.

  FIG. 13 is a block diagram showing the configuration of the pulse width / digital conversion circuit 29.

The pulse width / digital conversion circuit 29 in the present embodiment includes a counter 31 and n (n> 2) termination latch circuits 32-0 to 32- (n-1). The pulse width / digital conversion circuit 29 receives a clock CLK, a pulse output trigger XRST, and n PWM signals PW _{0 to} PW _n−1 from the outside. Further, a power supply voltage V _DD and a substrate voltage V _SS are applied.

A pulse train having a constant cycle is input to the clock CLK. The PWM signals PW _{0 to} PW _n−1 are outputs from the comparator 28 described above. The pulse output trigger XRST is a trigger that instructs the start of output of the PWM signals PW _{0 to} PW _n−1 . The pulse output trigger XRST outputs an inverted pulse having a time width corresponding to the clock cycle in a cycle M times the cycle of the clock CLK (M ≧ 2 ^m ).

The counter 31 counts the clock CLK input from the outside and outputs the count values CNT _{0 to} CNT _m-1 as m-bit digital signals. Each termination latch circuit 32-i (i∈ {0,..., N-1}) latches the count values CNT _{0 to} CNT _m-1 output by the counter 31 at the termination of the PWM signal PW _i input from the outside. To do. Each termination latch circuits 32-i, respectively, and outputs the latched count value CNT ₀ to CNT _m-1 digital output m bit D _{i, 0} to D _i, as _m-1.

  FIG. 14 is a block diagram showing the internal configuration of the termination latch circuit of FIG.

  The termination latch circuit 32-i (iε {0,..., N−1}) is configured by m latches 33-0 to 33- (m−1) and one inverter 34.

PWM signal PW _i input to the terminal latch circuit 32-i is level inverted by the inverter 34 is input to the clock input terminal clk of each latch 33-0~33- (m-1). The count values CNT _{0 to} CNT _m−1 of the counter 31 are input to the data input terminals D of the latches 33-0 to 33- (m−1), respectively. The pulse output trigger XRST is input to the reset input terminal NOT (R) of each latch 33-0 to 33- (m-1). The data output from the output terminal Q of each latch 33-0 to 33- (m-1) is output to the outside as _m- bit digital output data D _i = {D _{i, 0 to} D _{i, m-1} } Is done.

  Each latch circuit 33-0 to 33- (m-1) uses a synchronous D flip-flop with an asynchronous reset input as shown in FIG.

  The operation of the pulse width / digital conversion circuit 29 according to the present embodiment configured as described above will be described below.

  FIG. 16 is a time chart showing changes in each signal level of the pulse width / digital conversion circuit 29 according to this embodiment.

Pulses having a width T / 2 are continuously input to the clock CLK at a constant period T. Pulse output trigger XRST at time t _1, and outputs the inverted pulse width T. Thus, the output of each latch 33-0~33- (m-1) is reset, the digital output data D _i is all 0 reset.

Then, the output of each PWM signal PW _i (i∈ {0, 1,..., N−1}) is started from the rise time (time t ₂ ) of the pulse output trigger XRST. At the same time, the counter 31 starts counting the clock CLK. The counter 31 increases the count value by 1 at the rising edge of the clock CLK.

PWM signal PW _i is the output signal from the comparator 28. At this time, in the comparator 28, by synchronizing the start point of each of the ramp waveform 27, it is possible to output a PWM signal PW _i in synchronization with the count start of the counter 31.

At time t _3, PWM signal PW _i is inverted from H level to L level. As a result, the level of the output NOT (PW _i ) of the inverter 34 rises from the L level to the H level. Each latch 33-j (j∈ {0, 1,..., M−1}) has a count value CNT _j input to the data input terminal D at the rising edge of the output NOT (PW _i ) of the inverter 34. The level is latched and output from the data output terminal Q.

As a result, each terminal latch circuit 32-i (i∈ {0,..., N−1}) has a count value CNT ⁽ⁱ⁾ = {CNT ⁽ⁱ⁾ of the counter 31 at the falling point of the PWM signal PW _{i. 0} , CNT ⁽ⁱ⁾ ₁ , ..., CNT ⁽ⁱ⁾ _m-1 } are latched. The count value CNT ⁽ⁱ⁾ is a value proportional to the pulse width of the PWM signal PW _i.

When at least 2 ^m · T has elapsed since the counter 31 started counting, the digital output values of all the termination latch circuits 32-0 to 32- (n-1) are determined (of course, before that) In some cases). Therefore, after this determination time, a digital value proportional to the pulse width of the PWM signals PW _{0 to} PW _n-1 is obtained by taking out the digital output values of the termination latch circuits 32-0 to 32- (n-1). be able to. That is, the pulse width digital conversion is completed.

In this way, each termination latch circuit 32-i (iε {0,..., N−1}) latches the count value CNT output from the common counter 31 at the termination of the PWM signal PW _i . Therefore, the counter 31 only switches the output value (coefficient value CNT) against the parasitic capacitance of the wiring for outputting the count value CNT to each terminal latch circuit 32-i. Power consumption is small. Therefore, it is possible to significantly reduce the power consumption as compared with the case where the conventional pulse width digital conversion is used.

As a result of actual computer simulation evaluation, when 80 PWM signals PW _{0 to} PW ₇₉ are subjected to pulse width digital conversion in parallel, a conventional pulse width / digital conversion circuit as shown in FIG. 29 is used as a termination latch circuit. When used, it was estimated that 226mW of power would be consumed. On the other hand, when the pulse width / digital conversion circuit 29 according to this embodiment is used, the power consumption when the same PWM signal is subjected to pulse width digital conversion is 6.6 mW. Therefore, it was found that the power consumption can be reduced to about 1/50.

  Further, by using one counter 31, switching noise generated when the counter 31 is switched can be reduced. Therefore, the SN ratio of the circuit is improved. Therefore, jitter errors that occur during pulse width digital conversion due to jitter noise added to the pulse width can be minimized. Thereby, it can also be used for high-speed pulse width digital conversion.

Further, each terminal latch circuits 32-0~32- (n-1), so to latch the output value CNT of the common counter 31, the timing of switching of count value CNT for the PWM signal PW ₀ ~PW _n-1 There is no variation. Therefore, it is possible to prevent the timing error between the PWM signals PW _{0 to} PW _n−1 due to jitter at the time of switching of the counter 31 from being varied.

  Next, the above arithmetic processing flow will be described with reference to the flowchart of FIG. In the description, an arithmetic circuit that executes each processing step is also referred to.

  In FIG. 17, first, the input step S1 of the digital signal Ai is executed, and then the step S5 of converting the digital signal into the PWM signal is executed in each digital pulse width conversion circuit.

Next, the input step S6 of the digital signal Bi (voltage Vw) is executed, and then the D / A conversion step S7 for converting the digital signal into an analog signal is executed in the D / A conversion circuit.
Subsequently, in each analog arithmetic circuit, step S3 for multiplying the PWM signal, which is the output from steps S5 and S7, and the analog voltage Vw is executed.

  Next, step S4 is performed in which the multiplication values calculated in parallel in the respective analog arithmetic circuits are accumulated as charge amounts in the capacitors and are held as partial sums Σ (Ai × Bi).

  Next, the charge amount (voltage value) corresponding to the partial sum Σ (Ai × Bi) is A / D converted by the A / D conversion circuit to obtain a digital value, and step S9 is executed.

  Next, the digital value corresponding to the partial sum and the accumulated value output in step S11 and already stored in the digital memory (corresponding to the accumulated value in the middle of the operation) are added by the digital addition circuit. Then, step S10 for calculating as a new accumulated value is executed.

  Finally, step S11 is executed in which the accumulated value calculated as described above is rewritten and held in the digital memory. In this case, the accumulated value is overwritten on the corresponding part in the digital memory (the part where the accumulated value during the calculation is held).

  A desired accumulated value is calculated by repeating the operation flow described above as many times as necessary for calculating the accumulated value (three times in the present embodiment).

  In the above description, the processing is described as being completed when the desired accumulated value is stored in the digital memory. However, it is possible to perform further desired arithmetic processing on the accumulated value. . For example, a non-linear conversion circuit may be connected after the digital memory to output a value obtained by non-linear conversion of the accumulated value.

  In this case, the nonlinear conversion circuit can be realized by a look-up table circuit or the like. As described above, the analog / digital mixed arithmetic circuit described in the present embodiment can perform arbitrary arithmetic processing on the calculated accumulated value. The nonlinear conversion circuit may be connected to the subsequent stage of the digital adder circuit.

  In this case, the nonlinear conversion circuit can be realized by a look-up table circuit or the like.

  That is, the accumulated value calculated in the digital adder circuit is input to the lookup table circuit, nonlinearly converted by the lookup table circuit, and held in the digital memory.

  In this case, non-linear conversion is performed only on a desired calculation value calculated in the digital addition circuit (an accumulated value finally calculated, that is, a value represented by the calculation expression (7) or (12)). Non-linear conversion may not be performed on the accumulated values (arithmetic expressions (8) and (10)) calculated during the arithmetic processing.

  Further, any other configuration may be used as long as the accumulated value can be nonlinearly transformed.

  As described above, analog / digital power consumption is low and layout area is small by using a pulse width / digital conversion circuit that converts multiple PWM signals to digital values in parallel with low power consumption in the A / D converter circuit. It is possible to realize a mixed operation circuit.

(Fifth embodiment)
The analog / digital mixed type arithmetic circuit in this embodiment is a terminal latch circuit 32-0 to 32- (n of the pulse width / digital conversion circuit 29 constituting the analog / digital mixed type arithmetic circuit in the fourth embodiment. -1) is replaced with the circuit shown in FIG.

  Hereinafter, only the parts different from the fourth embodiment will be described, and the other parts are the same as those of the fourth embodiment, and the description thereof will be omitted.

  18, the configuration of the termination latch circuit 32-i (i∈ {0,..., N−1}), the latches 33-0 to 33- (m−1), and the inverter 34 is the same as that in FIG. Therefore, explanation is omitted. In addition to these, the pulse width / digital conversion circuit according to the present embodiment further includes a start-end latch circuit 35-i (i∈ {0, 1,..., N-1}) and a subtraction circuit 36-i. It is characterized by being.

Start latch circuits 35-i, in the beginning of the PWM signal PW _i (rising edge), latches the count value CNT outputted from the counter 31. The subtraction circuit 36-i calculates the digital output value S _i = {S _{i of the start} latch circuit 35-i from the digital output value E _i = {E _{i, 0 to} E _{i, m-1} } of the termination latch circuit 32- _{i. , 0 to} S _{i, m−1} } is calculated and output as a digital output value D _i = {D _{i, 0 to} D _{i, m−1} }.

Similarly to the termination latch circuit 32-i, the start-end latch circuit 35-i has latches 37-0 to 37- (m−1) corresponding to the respective bits CNT _{0 to} CNT _m−1 of the _m- bit count value. ). Like the latches 33-0 to 33- (m-1), these latches 37-0 to 37- (m-1) are constituted by synchronous D flip-flops with asynchronous reset inputs shown in FIG. ing.

However, to the clock terminal clk of the latch 37-0~37- (m-1) of the start latch circuit 35-i, without passing through the inverter 34, PWM signal PW _i is directly input. Therefore, the latch 37-0~37- (m-1) latches the count value CNT of the counter 31 at the time the rise of the PWM signal PW _i.

  The operation of the pulse width / digital conversion circuit according to this embodiment configured as described above will be described below.

  FIG. 19 is a time chart showing changes in each signal level of the pulse width / digital conversion circuit according to this embodiment.

As in the case of the fourth embodiment, pulses having a width T / 2 are continuously input to the clock CLK. Pulse output trigger XRST at time t _1, and outputs the inverted pulse width T. As a result, the outputs of the latches 33-0 to 33- (m-1) and 37-0 to 37- (m-1) are reset, and the digital output data E _i and S _i are all reset to zero.

The counter 31 starts counting the clock CLK from the time when the pulse output trigger XRST rises (time t ₂ ). The counter 31 increases the count value by 1 at the rising edge of the clock CLK.

At an appropriate time t ₃ after time t ₂ , the output of the PWM signal PW _i (i∈ {0, 1,..., N−1}) is started. Due to the rise of the PWM signal PW _i at time t _3, the latch 37-j (j∈ {0, 1,..., M−1}) of the start end latch circuit 35-i latches the output CNT _{j of the} counter 31. This is output from the data output terminal Q as a digital output value S _i = {S _{i, 0 to} S _{i, m-1} }.

At time t _4, PWM signal PW _i is inverted from H level to L level. As a result, the level of the output NOT (PW _i ) of the inverter 34 rises from the L level to the H level. Each latch 33-j (j∈ {0, 1,..., M−1}) has a count value CNT _j input to the data input terminal D at the rising edge of the output NOT (PW _i ) of the inverter 34. The level is latched and output from the data output terminal Q as a digital output value E _i = {E _{i, 0 to} E _{i, m-1} }.

The subtraction circuit 36-i calculates the digital output value S _i = {S _{i of the start} latch circuit 35-i from the digital output value E _i = {E _{i, 0 to} E _{i, m-1} } of the termination latch circuit 32- _{i. , 0 to} S _{i, m−1} } is calculated and output as a digital output value D _i = {D _{i, 0 to} D _{i, m−1} }. Therefore, after time t ₃ , the digital output value D _i = {D _{i, 0 to} D _{i, m−1} } is a value that is directly proportional to the pulse width of the PWM signal PW _i .

When at least 2 ^m · T has elapsed since the counter 31 started counting, all the terminal latch circuits 32-0 to 32-(n-1) and the subtraction circuits 36-0 to 36- (n- The digital output value of 1) is determined (of course, it may be determined before that). Therefore, after this fixed time point, the digital value D _i proportional to the pulse width of each PWM signal PW _{0 to} PW _n-1 is obtained by taking out the digital output value of each subtraction circuit 36-0 to 36- (n-1). = {D _{i, 0 to} D _{i, m-1} } can be obtained. That is, the pulse width digital conversion is completed.

Thus, in the present embodiment, the count value of the counter 31 at the beginning and end of each input pulse latches, by calculating the difference between by a digital output value, the rise of the PWM signal PW _i Need not be synchronized. Moreover, it is not necessary to count start timing of the rising and the counter 31 of the PWM signal PW _i also synchronized.

Instead of preparing the subtracting circuit 36-i, the digital output values S _i and E _i may be directly output to the outside, and the subtraction may be performed by an externally prepared subtracter.

(Sixth embodiment)
FIG. 20 shows a configuration example 600 of an analog / digital mixed arithmetic circuit according to the sixth embodiment.

  In this embodiment, in the mixed analog / digital arithmetic circuit described in the fourth and fifth embodiments, the digital adder circuit is replaced with the digital adder / subtractor circuit 38, and the analog arithmetic circuit 3 performs multiplication having positive and negative signs. The value B is multiplied separately for each sign, the sign bit 39 representing the sign of the multiplied value B is input to the digital adder / subtractor circuit 38, and the partial sum of the operation results for the negative multiplied value B is In the calculation with the digital data stored in the digital memory 26, the digital addition / subtraction circuit 38 performs the subtraction from the digital data in the digital memory 26, which is different from the fourth and fifth embodiments.

  That is, the multiplication in the analog arithmetic circuit 3 in the present embodiment separately performs the multiplication of the positive sign and the multiplication of the negative sign for the positive and negative signs of the multiplication value B, respectively.

  Hereinafter, only the parts different from the fourth and fifth embodiments will be described, and the other parts will be omitted as they are the same as the fourth and fifth embodiments.

  When the calculation represented by the following calculation expression (13) is performed by the analog / digital mixed calculation circuit 600 of FIG. 20, the four analog calculation circuits 3 have the calculation expressions (14), (15), (16), and (17). ), The calculation of the sign of the multiplication value B is performed separately.

(13)

(13)

A _i ≧ 0,
B ₁ , B ₂ , B ₅ , B ₇ , B ₉ , B ₁₀ , B ₁₄ , B ₁₆ ≧ 0, B ₃ , B ₄ , B ₆ , B ₈ , B ₁₁ , B ₁₂ , B ₁₃ , B ₁₅ < 0
A ₁・ B ₁ + A ₂・ B ₂ + A ₅・ B ₅ + A ₇・ B ₇ (14)
A ₉ , B ₉ + A ₁₀ , B ₁₀ + A ₁₄ , B ₁₄ + A ₁₆ , B ₁₆ (15)
A ₃・ B ₃ + A ₄・ B ₄ + A ₆・ B ₆ + A ₈・ B ₈ (16)
A ₁₁ , B ₁₁ + A ₁₂ , B ₁₂ + A ₁₃ , B ₁₃ + A ₁₅ , B ₁₅ (17)
At this time, as in the first and second embodiments, even if the total number of operations (16 in the above case) is not a multiple of the number of analog operation circuits (4), the multiplication value B = 0. The number of operations can be adjusted by inputting an analog voltage Vw corresponding to.

  Subsequently, as in the fourth and fifth embodiments, the partial sum represented by the arithmetic expressions (14) to (17) is calculated by the analog arithmetic circuit 3. In this case, each partial sum is calculated as an absolute value that does not consider the sign of the multiplication value B.

  Next, the partial sum represented by the calculated arithmetic expressions (14) to (17) is converted into digital data by the A / D conversion circuit 500, and the converted digital data is input to the digital addition / subtraction circuit 38. . At this time, a sign bit 39 representing the sign of the multiplication value B is also input to the digital addition / subtraction circuit 38.

  Subsequently, in the digital addition / subtraction circuit 38, when the sign bit of the input partial sum digital data is 1 (the multiplication value B is positive), the digital memory 26 stores the same as in the fourth and fifth embodiments. The input partial sum digital data is added to the held digital data.

  On the other hand, when the sign bit of the input partial sum digital data is 0 (multiplication value B is negative), the input partial sum digital data is subtracted from the digital data held in the digital memory 26.

  As described above, the desired accumulated value is calculated by adding or subtracting the digital data held in the digital memory and the partial sum digital data according to the sign bit. Note that, as in the fifth embodiment, it is possible to perform further desired arithmetic processing on the accumulated value. That is, for example, a non-linear conversion circuit may be connected to the subsequent stage of the digital memory, and a value obtained by non-linear conversion of the accumulated value may be output. In this case, the nonlinear conversion circuit can be realized by a look-up table circuit or the like.

  As described above, the analog / digital mixed arithmetic circuit described in the present embodiment can perform arbitrary arithmetic processing on the calculated accumulated value. The nonlinear conversion circuit may be connected to the subsequent stage of the digital addition / subtraction circuit. In this case, the nonlinear conversion circuit can be realized by a look-up table circuit or the like.

  That is, the accumulated value calculated in the digital addition / subtraction circuit is input to the lookup table circuit, nonlinearly converted by the lookup table circuit, and held in the digital memory.

  In this case, non-linear conversion is performed only on a desired calculation value (accumulated value finally calculated, that is, a value indicated by the calculation formula (13)) calculated in the digital addition circuit, Non-linear transformation may not be performed on the calculated accumulated value. Further, any other configuration may be used as long as the accumulated value can be nonlinearly transformed.

  Next, the above arithmetic processing flow will be described with reference to the flowchart of FIG. In the description, an arithmetic circuit that executes each processing step is also referred to.

  In FIG. 21, first, the input step S1 of the digital signal Ai is executed, and then the step S5 of converting the digital signal into a PWM signal is executed in each digital pulse width conversion circuit. Next, the input step S6 of the digital signal Bi (voltage Vw) is executed, and then the D / A conversion step S7 for converting the digital signal into an analog signal is executed in the D / A conversion circuit. Subsequently, in each analog arithmetic circuit, step S3 for multiplying the PWM signal, which is the output from steps S5 and S7, and the analog voltage Vw is executed.

  Next, step S4 is performed in which the multiplication values calculated in parallel in the respective analog arithmetic circuits are accumulated as charge amounts in the capacitors and are held as partial sums Σ (Ai × Bi). Next, the charge amount (voltage value) corresponding to the partial sum Σ (Ai × Bi) is A / D converted by the A / D conversion circuit to obtain a digital value, and step S9 is executed. Next, in the digital addition / subtraction circuit, a digital value corresponding to the partial sum is obtained in accordance with the value of the sign bit input by executing step S13 of inputting the sign bit representing the sign of Bi to the digital addition / subtraction circuit. Step S12 for calculating is executed.

  That is, when the sign bit is 1 (Bi is positive), the digital value corresponding to the partial sum and the accumulated value output in step S11 and already held in the digital memory (accumulated during the operation). Is added by a digital addition / subtraction circuit to calculate a new accumulated value.

  If the sign bit is 0 (Bi is negative), the digital value corresponding to the partial sum is stored in the accumulated value already stored in the digital memory output in step S11 (accumulation during the operation). Is equivalent to a value) by a digital addition / subtraction circuit to calculate a new accumulated value.

  Finally, step S11 is executed in which the accumulated value calculated as described above is rewritten and held in the digital memory. In this case, the accumulated value is overwritten on the corresponding part in the digital memory (the part where the accumulated value during the calculation is held).

  A desired accumulated value is calculated by repeating the operation flow described above as many times as necessary for calculating the accumulated value (four times in the present embodiment).

  As described above, the partial sum is calculated separately by the analog arithmetic circuit 3 corresponding to the positive and negative signs of the multiplication value B, and the digital data held in the digital memory 26 corresponding to the positive and negative signs. It is possible to calculate an accumulated value of a multiplication result including a positive / negative sign as shown in the following arithmetic expression (18).

(18)

(18)

  Further, in the above calculation, as shown in the following calculation formula (19), when the calculation processing steps corresponding to the positive and negative signs of the multiplication value B are alternately performed, since the positive and negative partial sums cancel each other, The range of linear addition accuracy (accumulated value range) in the digital memory 26 is narrowed, and the bit length of the digital memory 26 can be reduced.

(19)

(19)

  For example, when the partial sums represented by the arithmetic expressions (14) to (17) are respectively (85, 53, 60, 71) in order, if the same sign is continuously added and subtracted, The values stored in the digital memory 26 over time are as follows.

Saved value by first calculation = 85
Saved value by second calculation = 85 + 53 = 138
Saved value by third calculation = 138−60 = 78
Saved value by the fourth calculation = 78−71 = 7
Therefore, since the maximum value in the course of adding and subtracting the partial sum in this case is 138, the bit length of the digital memory 26 is 8 bits.

  On the other hand, when calculations corresponding to positive and negative signs are alternately performed, values stored in the digital memory 26 in the middle of the calculation are as follows.

Saved value by first calculation = 85
Saved value by second calculation = 85−60 = 25
Saved value by third calculation = 25 + 53 = 78
Saved value by the fourth calculation = 78−71 = 7
Therefore, since the maximum value in the course of adding and subtracting the partial sum in this case is 85, the bit length necessary for the digital memory 26 is 7 bits, and it can be understood that a bit length smaller than the above example is sufficient. .

(Seventh embodiment)
A configuration example of the neural network circuit in the seventh embodiment is shown in FIG. As shown in FIG. 22, a neural network circuit 700 in this embodiment is characterized by including the analog / digital mixed arithmetic circuit described in the sixth embodiment and a digital pulse width conversion circuit.

  In order to perform the nonlinear conversion described in the sixth embodiment, a lookup table circuit is connected after the digital addition / subtraction circuit.

  Further, FIG. 23 shows a configuration diagram 800 of the neural network model realized in the present embodiment, and FIG. 24 shows characteristics of each neuron.

  In the following, first, the neural network model in the present embodiment will be described with reference to FIGS. 23 and 24, and then the neural network circuit 700 in the present embodiment will be described with reference to FIG.

  As shown in FIG. 23, in the neural network in this embodiment, a plurality of neurons 40 form a hierarchical structure, and neurons between different layers are connected to each other via a synapse 41.

  In addition to the present embodiment, there are neural network configurations in which neurons are arranged in an array, and there are also connections between neurons, such as those having connections between two neurons. . The neural network in the present invention is not limited by the configuration or the coupling method, and may have a structure and a coupling method other than the hierarchical structure shown in the present embodiment.

Subsequently, arithmetic processing in each neuron 40 will be described with reference to FIG. Each neuron 40 weights the output values of a plurality of neurons connected to the previous stage with a synaptic load, and then receives it as an input. Inside the neuron, the total value of the input values is calculated, and this is subjected to a predetermined conversion to obtain an output value. Here, the arithmetic processing in each neuron is expressed by the following equation (20).
y ＝ f (Σω ・ x) (20)
y: output value, f: transformation function, ω synaptic load, x: output value of the previous neuron

Various models have been proposed as conversion functions. In the present embodiment, a general sigmoid function expressed by the following equation (21) is applied. The characteristics of the sigmoid function are shown graphically in FIG.
f (u) = {1 + exp (−au)} ⁻¹ (21)
a: Parameter that determines the slope of the sigmoid function

  Note that the neural network in the present invention is not limited by the conversion method in the neuron, and a conversion function other than the sigmoid function shown in the present embodiment may be applied.

  Next, the neural network circuit in this embodiment will be described with reference to FIG. As can be seen from FIG. 22, the neural network circuit according to the present embodiment includes a hierarchically configured analog / digital mixed arithmetic circuit described in the sixth embodiment.

  As described above, in the arithmetic circuit in this embodiment, the look-up table circuit is connected to the subsequent stage of the adder / subtracter circuit. That is, the desired accumulation result calculated in the digital addition / subtraction circuit is held in the digital memory circuit after being subjected to sigmoid function conversion by the lookup table circuit. Note that the sigmoid function conversion by the look-up table circuit is performed only for a desired calculation result finally calculated, and is not performed for data in the middle of accumulation.

  Therefore, in FIG. 22, two systems are depicted: the output from the digital adder / subtractor circuit is input to the look-up table circuit, and the output is input directly to the digital memory.

  Furthermore, in the analog / digital mixed type arithmetic circuit described in the present embodiment, in order to perform hierarchical arithmetic processing, the calculation result calculated by the analog / digital mixed type arithmetic circuit of a certain level is used as the next level. It is used as an input for an analog / digital mixed arithmetic circuit. At this time, the digital pulse width conversion circuit reads out the calculation result held in the digital memory as a PWM signal. The generation process of the PWM signal is as described in the first and second embodiments.

  Note that the arithmetic processing steps in the analog / digital mixed arithmetic circuit in each layer are the same as those in the sixth embodiment. Although omitted in FIG. 22, an analog voltage Vw corresponding to the multiplication value B is input to the analog arithmetic circuit. The input process of the analog voltage Vw is the same as that of the sixth embodiment.

  In the arithmetic processing process of the analog / digital mixed arithmetic circuit of the present embodiment, the partial sum held in the capacitor indicates the sum of input values related to a part of the connection with the preceding neuron in each neuron. In addition, the accumulated value finally stored in the digital memory indicates the accumulated value of the input values of all the previous-stage neurons to be connected in each neuron. Note that the nonlinear transformation shown in FIG. 24 is realized in the nonlinear transformation circuit (lookup table circuit) as described above.

  Here, FIG. 25 shows the calculation processing flow described above. A one-dot chain line in the figure indicates a boundary between the previous layer and the subsequent layer in the arithmetic processing.

  First, the calculated desired accumulated value of the previous layer is subjected to sigmoid conversion S20, temporarily held as a digital value in a digital memory S11, and further converted to a PWM signal by a digital pulse width conversion circuit. In the present embodiment, the sigmoid conversion step S20 is executed by the lookup table circuit only once after the desired accumulated value is calculated. The processing steps other than the sigmoid conversion step S20 in the previous layer are the same as the arithmetic processing in the sixth embodiment.

  Subsequently, the PWM signal is input as an input signal Ai to the subsequent layer. The arithmetic processing performed in the subsequent layer is the same as the arithmetic processing described in the sixth embodiment, except for the processing step by the sigmoid conversion step S20, as in the arithmetic processing in the previous layer. A description of the same arithmetic processing flow as in the sixth embodiment will be omitted. Also, in FIG. 25, a plurality of other Ai input steps are omitted and depicted by a dotted arrow S14.

  As described above, the accumulated value in each neuron held in the digital memory is read out as a PWM signal by the digital pulse width conversion circuit and output to the neuron in the next layer, so that the neural network shown in FIG. A model can be realized. Note that the number of neuron elements and the number of layers in the present embodiment do not limit the configuration of the neural network in the present invention, and can be set to any number as necessary.

(Eighth embodiment)
A configuration example of the image signal processing circuit in the eighth embodiment is shown in FIG. As shown in FIG. 26, the image signal processing circuit in the present embodiment is characterized by including the neural network circuit described in the seventh embodiment. In FIG. 26, only the first level of the hierarchical structure described in the fifth embodiment is shown, and descriptions of the subsequent levels are omitted.

  The number of analog / digital mixed arithmetic circuits in the neural network circuit is different from that of the neural network circuit of FIG. 22 described in the seventh embodiment. The calculation operation itself is the same as in the seventh embodiment.

  In FIG. 26, the look-up table circuit, the digital memory, and the digital pulse width conversion circuit are depicted as a single unit, but this is merely on the space of the paper. This is exactly the same as the seventh embodiment.

  Here, a signal input as a PWM signal to the analog arithmetic circuit in the neural network circuit is an image signal which is a two-dimensional signal. That is, the image signal processing circuit in the present embodiment is intended to perform desired image processing (for example, pattern detection and pattern recognition) by performing a predetermined operation on the input image signal by a neural network circuit. It is what.

  It should be noted that the actual image processing content can be set so that desired processing content (for example, pattern detection and pattern recognition) is realized by appropriately adjusting circuit parameters of the neural network circuit. However, since the detailed adjustment method is not the main point of the present invention, the description is omitted.

  Here, in the present embodiment, the image signal is input as a PWM signal that is output from the image sensor 43 (for example, a CCD or CMOS image sensor) and converted from the signal intensity corresponding to each pixel to a pulse time width. ing.

  The output signal from the image sensor is an analog signal. When the signal is converted into a PWM signal, as shown in FIG. 26, the ramp voltage waveform input to the comparator 42 and the image read from the image sensor are read. Comparing the voltage value with the comparator 42, the output that has risen to the high level at the start of the ramp voltage waveform falls to the low level when the ramp voltage value becomes equal to the voltage value of the capacitor, and is converted into a PWM signal. The

  In addition, when the output signal from the image sensor 43 is a digital signal, and when the signal is converted into a PWM signal, the PWM signal is converted by the digital pulse width conversion circuit as described in the first and second embodiments. Convert to Although a CCD or CMOS image sensor is assumed as the image sensor, there is no problem even if another image sensor is used as long as it captures an image as a two-dimensional signal.

  Next, an image signal input method for the neural network circuit will be described.

  In the neural network circuit, as described in the sixth embodiment, each analog / digital mixed arithmetic circuit a, b performs a weighting operation on a predetermined plurality of input signals, and the accumulated value is obtained. The calculated value is used as the internal state value of the corresponding neuron, and further nonlinear conversion is performed.

  At this time, in the image processing circuit according to the present embodiment, a plurality of input signals to be processed by the analog / digital mixed arithmetic circuits a and b surrounded by a one-dot chain line are two-dimensionally arrayed. It corresponds to a part of the area.

  That is, as shown in FIG. 26, in each of the analog / digital mixed arithmetic circuits a and b, a region for performing non-linear conversion and weighting calculation and outputting an image signal that is a target for calculating the accumulated value is as follows. It is indicated by areas A and B surrounded by broken lines. Here, the image signal output from the image sensor 43 is output for each column.

  On the other hand, as described in the first to seventh embodiments, the calculation by the analog calculation circuit in the neural network circuit can be performed in parallel for the image signal output for one column.

  Therefore, the calculation result by the neural network circuit for the output signal for one column from the image sensor 43 corresponds to the partial sum for the internal state value of each neuron as described in the first to seventh embodiments. .

  Then, by repeating the above arithmetic processing several times (four times in the present embodiment) in the regions A and B, an accumulated value corresponding to the internal state value of each neuron can be finally calculated.

  Next, FIG. 27 shows the calculation processing flow described above.

  First, step S15 for inputting image signals for one column output from the image sensor is executed, and then step S16 for converting the input image signals into PWM signals by a circuit such as a comparator is executed. Subsequently, the PWM signal is input to the multiplication step S3 (upper side in the figure) as a PWM signal corresponding to Ai.

  The subsequent calculation processing flow is the same as that of the seventh embodiment, and only the calculation processing of a predetermined number of layers as a neural network circuit is different (in FIG. 27, the part surrounded by a dotted frame) S100 shows the same processing flow as in the seventh embodiment). A description of an arithmetic processing flow similar to that of the seventh embodiment is omitted, and the arithmetic processing of a predetermined number of layers is omitted because the arithmetic processing flow is repeated a predetermined number of times.

  As described above, desired arithmetic processing (for example, pattern detection and pattern recognition) can be achieved by repeating the arithmetic processing by the neural network circuit as many times as the number of columns in the calculation target region.

  In the above description, the image signal output from the image sensor is performed for each column. However, when the signal output from the image sensor is performed for each row, the calculation in the neural network circuit is performed for one row of output signals. By performing each in parallel, it is possible to perform the same processing as described above.

  As described above, the calculation by the neural network circuit in the present embodiment is applied to the image signal output for each column or row, and the internal state value of the neuron is determined for each column or row. By calculating as a partial sum, and calculating a final internal state value as an accumulated value of the partial sum, and further performing non-linear conversion thereof, it is possible to realize a desired calculation process.

It is a figure which shows the whole structure of the arithmetic circuit concerning 1st embodiment. It is a figure which shows the analog arithmetic circuit and capacitor which comprise the arithmetic circuit concerning 1st embodiment. It is a figure which shows the analog arithmetic circuit which comprises the arithmetic circuit concerning 1st embodiment. It is a figure which shows the digital pulse width conversion circuit which comprises the arithmetic circuit concerning 1st embodiment. It is a figure which shows each pulse generation circuit concerning 1st embodiment. It is a timing chart showing the operation of the digital pulse width conversion circuit according to the first embodiment. It is a figure which shows the arithmetic processing flowchart of the arithmetic circuit concerning 1st embodiment. It is a figure which shows the whole structure of the arithmetic circuit concerning 3rd embodiment. It is a figure which shows the D / A converter circuit concerning 3rd embodiment. It is a figure which shows the arithmetic processing flowchart of the arithmetic circuit concerning 3rd embodiment. It is a figure which shows the whole structure of the arithmetic circuit concerning 4th embodiment. It is a figure which shows the A / D conversion circuit concerning 4th embodiment. It is a figure which shows the pulse width and digital conversion circuit concerning 4th embodiment. It is a figure which shows the internal structure of the termination | terminus latch circuit concerning 4th embodiment. It is a figure which shows the internal structure of the latch circuit concerning 4th embodiment. It is a time chart showing the change of each signal level of the pulse width-digital conversion circuit concerning 4th embodiment. It is a figure which shows the arithmetic processing flowchart of the arithmetic circuit concerning 4th embodiment. It is a figure which shows the termination | terminus latch circuit of the pulse width and digital conversion circuit concerning 5th embodiment, a start end latch circuit, and a subtraction circuit. It is a time chart showing the change of each signal level of the pulse width digital conversion circuit concerning a 5th embodiment. It is a figure which shows the whole structure of the arithmetic circuit concerning 6th Embodiment. It is a calculation processing flowchart of the calculation circuit according to the sixth embodiment. It is a figure showing the composition of a neural network circuit. It is a figure which shows the structure of a neural network model. It is a figure which shows the characteristic of a neuron. It is a figure which shows the arithmetic processing flowchart of the arithmetic circuit concerning 7th Embodiment. It is a figure which shows the structure of an image signal processing circuit provided with a neural network circuit. It is a calculation processing flowchart of the calculation circuit according to the eighth embodiment. It is a figure which shows an example of the conventional digital pulse width conversion circuit. It is a figure which shows an example of the conventional pulse width and digital conversion circuit. It is a figure which shows the digital pulse width conversion circuit which comprises the arithmetic circuit concerning 2nd embodiment. It is a figure which shows each pulse generation circuit concerning 2nd embodiment. 6 is a timing chart showing the operation of the digital pulse width conversion circuit according to the second embodiment.

Explanation of symbols

1 Digital memory
2 Digital pulse width conversion circuit
3 Analog operation circuit
4 capacitors
5 PWM signal
6 Analog voltage Vw
7 Input terminal
8 Input terminal
10-0 to 10- (n-1) pulse generation circuit
11 counter
12 Reference value register
13 Adder circuit
14 Pulse width register
15 Switching circuit
16 Timing trigger generator
17 Output pulse inversion circuit
18-0 ~ 16- (m-1) EXOR gate
19 NOR gate
20 Digital memory
21 Digital pulse width conversion circuit
22 Current source
24 buffers
25 Digital adder circuit
26 Digital memory
27 Ramp voltage
28 Comparator
29 Pulse width / digital conversion circuit
31 counter
32-1 to 32-(n-1) Termination latch circuit
33-0 to 33- (m-1) Latch
34 Inverter
35-0 to 35- (n-1) Start latch circuit
36-0 to 36- (n-1) Subtraction circuit
37-0 to 37- (m-1) Latch
38 Digital addition / subtraction circuit
39 Sign bit
40 neurons
41 Synapse
42 Comparator
43 Image sensor
51 Digital pulse width conversion circuit
52-0 to 52- (n-1) Pulse generation circuit
53 counter
62 Pulse width register
64 Timing trigger generator
65 Output pulse inversion circuit
66-0 ~ 66- (m-1) EXOR gate
67 NOR gate
M1 PMOS transistor
100 Arithmetic circuit according to the first embodiment
200 Arithmetic circuit according to second embodiment
300 D / A converter circuit
400 Arithmetic Circuit According to Third Embodiment
500 A / D converter circuit
600 Arithmetic Circuit According to Fifth Embodiment
700 Neural network circuit
800 neural network model
900 Image signal processing circuit
101 Strobe detection circuit
102 Latch circuit
103 counter
104 Digital comparator
105 JK flip-flop
111 Conventional pulse width / digital conversion circuit
112 Gate circuit
113 counter

Claims (20)

An arithmetic circuit for calculating an accumulated value of arithmetic results obtained by parallel arithmetic processing,
A plurality of analog arithmetic circuits that perform arithmetic processing on information represented by analog signals;
A capacitor that accumulates as a charge amount a total value of calculation results by the plurality of analog calculation circuits;
A comparator that converts the amount of charge accumulated in the capacitor into a pulse signal having a corresponding pulse width;
A pulse width / digital conversion circuit for converting the pulse signal into a digital signal;
A digital arithmetic circuit that calculates an accumulated value based on the converted digital signal,
The pulse width / digital conversion circuit comprises:
A counter that counts the clock and outputs the count value as a digital signal;
An arithmetic circuit comprising: a plurality of termination latch circuits for latching a common count value output by the counter at the end of each pulse signal input thereto. The pulse width / digital conversion circuit comprises:
A start-end latch circuit that latches a count value output by the counter at the start end of the pulse signal;
A subtracting circuit that calculates and outputs a difference between a digital output value of the termination latch circuit and a digital output value of the start latch circuit, corresponding to each of the plurality of termination latch circuits, The arithmetic circuit according to claim 1.   The digital arithmetic circuit switches between the addition process and the subtraction process of the converted digital signal based on the information about the positive / negative of the calculation result by the analog arithmetic circuit, and calculates the accumulated value of the digital signal The arithmetic circuit according to claim 1.   The arithmetic circuit according to claim 1, wherein the plurality of analog arithmetic circuits are connected in parallel to the capacitor.   5. The arithmetic circuit according to claim 1, wherein a charge amount corresponding to a partial sum of the calculated accumulated values is stored in the capacitor based on an input analog signal.   6. The arithmetic circuit according to claim 1, wherein the digital arithmetic circuit executes processing every time arithmetic processing in the plurality of analog arithmetic circuits is completed.   The arithmetic circuit according to claim 1, wherein the analog arithmetic circuit multiplies the analog signal by a predetermined load value.   The arithmetic circuit according to claim 1, wherein the analog arithmetic circuit performs predetermined nonlinear conversion on the analog signal.   The arithmetic circuit according to claim 8, wherein the analog arithmetic circuit multiplies the output value of the nonlinear conversion by a predetermined load value.   10. The calculation according to claim 1, wherein the accumulated value calculated based on the analog signal is equivalent to an internal state value of a neuron constituting a neural network having the analog signal as an input value. circuit.   The arithmetic circuit according to claim 1, wherein the amount of charge stored in the capacitor is equivalent to a partial sum with respect to an internal state value of a neuron constituting a neural network having the analog signal as an input value.   The arithmetic circuit according to claim 1, wherein the analog signal is an image signal, and the analog arithmetic circuit performs arithmetic processing for each row of the image signal. A memory for holding digital data;
The digital arithmetic circuit adds the digital data held in the memory and the converted digital signal, and the memory holds the addition result to calculate the accumulated value. The arithmetic circuit according to claim 1. A memory for holding digital data;
When the calculation result by the analog calculation circuit is positive, the digital calculation circuit adds the digital data held in the memory and the converted digital signal, and the memory holds the addition result,
When the calculation result by the analog calculation circuit is negative, the digital calculation circuit subtracts the converted digital signal from the digital data held in the memory, and the memory holds the subtraction result, The arithmetic circuit according to claim 1, wherein the accumulated value is calculated.   The arithmetic circuit according to claim 3, wherein the digital arithmetic circuit alternately performs addition processing and subtraction processing. A second counter that counts the clock and outputs the count value as a digital signal;
Each input value input as a digital value from the outside is compared with the common count value output from the counter, and the time width from the predetermined time point to the time point when the input value and the count value match is determined. An output pulse signal or an output pulse signal having a time width from when the count value matches the value obtained by subtracting the input value from a predetermined maximum count value to the time when the count value reaches the maximum count value is generated. 16. The arithmetic circuit according to claim 1, further comprising a digital pulse width conversion circuit including a plurality of pulse generation means. Each of the plurality of pulse generating means includes
A pulse width register for latching the input value input from the outside;
A timing trigger generation circuit that compares each bit of the input value latched by the pulse width register with each bit of the count value output by the counter and generates a trigger when the two match completely;
An output pulse inversion circuit that inverts the truth value of the output pulse signal when the timing trigger generation circuit generates a trigger; and
The arithmetic circuit according to claim 16, further comprising: Each of the plurality of pulse generating means includes
A reference value register that latches a reference value that is a digital value indicating the rising timing of the output pulse;
An adder circuit that outputs an added value of the reference value and the input value that is a digital value input from the outside;
A pulse width register for latching the output value of the adder circuit;
A switching circuit that switches and outputs either the digital value latched by the reference value register or the digital value latched by the pulse width register;
A timing trigger generation circuit that compares each bit of the digital value output from the switching circuit with each bit of the count value output by the counter and generates a trigger when they completely match;
An output pulse inversion circuit that inverts the truth value of the output pulse signal when the timing trigger generation circuit generates a trigger;
The switching circuit outputs a digital value latched by the reference value register when the output pulse output from the output pulse inverting circuit is a false value, and when the output pulse output from the output pulse inverting circuit is a true value. 17. The arithmetic circuit according to claim 16, wherein switching is performed so as to output a digital value latched by the pulse width register. A current source circuit controlled by an output pulse signal from the digital pulse width conversion circuit;
The arithmetic circuit according to claim 16, further comprising a second capacitor. An operation control method for an arithmetic circuit that calculates an accumulated value of arithmetic results obtained by parallel arithmetic processing,
An analog calculation process for calculating information represented by analog signals by a plurality of analog calculation circuits;
An accumulation step of accumulating the total value of the calculation results by the analog calculation step in the capacitor as a charge amount;
A voltage pulse conversion step of converting the amount of charge accumulated in the capacitor into a pulse signal having a corresponding pulse width;
A pulse width / digital conversion step of converting the pulse signal into a digital signal;
An addition step of calculating an accumulated value based on the converted digital signal,
The pulse width / digital conversion step comprises:
A step of counting clocks by a counter and outputting the counted value as a digital signal;
And a step of latching a common count value output by the counter at the end of each pulse signal input thereto by a plurality of end latch circuits.

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