CN108428686B - 开关装置和设计开关装置的方法 - Google Patents
开关装置和设计开关装置的方法 Download PDFInfo
- Publication number
- CN108428686B CN108428686B CN201810145752.5A CN201810145752A CN108428686B CN 108428686 B CN108428686 B CN 108428686B CN 201810145752 A CN201810145752 A CN 201810145752A CN 108428686 B CN108428686 B CN 108428686B
- Authority
- CN
- China
- Prior art keywords
- pin
- package
- load terminal
- switching device
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
- G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
- G01R33/09—Magnetoresistive devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04034—Bonding areas specifically adapted for strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/40227—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
公开了一种包括在封装件内的开关的开关装置和用于设计开关装置的方法。在开关的负载端子和封装件的第一引脚之间设置有第一电连接,并且在开关的负载端子和封装件的第二引脚之间设置有至少部分地不同于第一电连接的第二电连接。第二引脚不同于第一引脚。
Description
技术领域
本申请涉及开关装置以及用于设计开关装置的方法。
背景技术
开关装置被用于切换电压或电流,例如用于选择性地将负载耦接至电压源和/或电流源,或用于切换电路内的信号。在一些应用中,期望测量流经开关装置的电流。也称为功率开关装置的一些开关装置可以使用晶体管作为开关并且可以被设计成切换诸如几安培或几十安培的高电流和/或诸如几百伏特的高电压。例如考虑到限制功耗,测量高电流可能是一个挑战。
已经采用了用于这种电流测量的各种方法。例如,诸如包括电流镜的电流测量电路可以与单个芯片管芯上的半导体功率开关集成在一起。在其他方法中,电流测量电路可以被设置在容纳半导体开关(例如,测量电阻器或测量变压器)的封装件的外部,或者可以被设置在封装件内但是在芯片管芯外部。在某些情况下,单片集成的方法可能不具备所要求的准确度和/或不能与负载电流进行电流隔离。封装件外部的方法需要相应的空间,在电阻器的情况下可能具有高损耗和相关的功耗,或者可能相对昂贵。
在用于电流测量的一种方法中,在封装件内设置磁场传感器装置以通过感测由负载电流产生的磁场来测量负载电流。磁场传感器装置可以被实现为桥式电路或者可以被实现为霍尔(Hall)传感器,其中形成桥式电路的元件中的至少一些是诸如各向异性磁阻(AMR)、巨磁阻(GMR)或隧穿磁阻(TMR)传感器元件的磁阻元件。
为了生成待被磁场传感器装置感测的足够大的磁场,测量电流的导体需要具有一定的电感。另一方面,这种电感可能会降低开关装置的切换速度,并且增大接通开关装置时的损耗。而且,切换速度也会取决于负载电流。
发明内容
根据一个实施方式,一种装置包括:封装件;设置在封装件中的开关,开关包括控制端子、第一负载端子和第二负载端子,其中,开关的第二负载端子经由第一电连接与封装件的第一引脚连接,第二负载端子经由第二电连接耦接至封装件的与第一引脚不同的第二引脚,并且第二电连接至少部分地不同于所述第一电连接。
根据另一实施方式,用于设计开关装置的方法包括:确定开关装置的所要求的接通性能,以及根据所要求的接通性能确定用于开关装置的负载端子与封装件的引脚之间的电连接的分接(tap)位置。
以上概要仅旨在给出对一些实现的简要概述,而不应被解释为限制。
附图说明
图1是示出根据一个实施方式的开关装置的框图;
图2是用于说明根据各实施方式的开关装置的特性的电路图;
图3示出了用于说明根据一些实施方式的开关装置的特性的仿真结果;
图4是根据一个实施方式的开关装置的局部透视图;
图5是沿着图4中的线A-A’所截取的示意性截面图;
图6是说明在类似于图4所示的实施方式中生成的磁场的图;以及
图7是示出根据一个实施方式的方法的流程图。
具体实施方式
在下文中,将参照附图详细描述各种实施方式。应该注意的是,这些实施方式仅仅是通过示例的方式给出的,不应该被解释为限制。例如,虽然实施方式可以被描述为包含许多特征或元素,但是在其他实施方式中,可以省略这些特征或元素中的一些,和/或可以由替代的特征或元素替换。此外,除了在附图中明确示出或在本文中描述的特征或元素之外,可以提供另外的特征或元素,例如在常规开关装置中使用的过电流保护、过电压保护或温度监控这样的特征或元素。
一些实施方式包括开关。通常可以将开关描述为包括控制端子和至少两个负载端子。基于提供至控制端子的信号,开关处于也称为接通状态的闭合状态或者处于也称为关断状态的打开状态。在闭合状态下,开关在其具有低欧姆电阻和/或低压降的负载端子之间电导通。在打开状态下,开关(除了可能存在不希望的漏电流之外)在其负载端子之间基本上不导通。
在一些实施方式中,开关可以被实现为晶体管。例如,在场效应晶体管如金属氧化物半导体场效应晶体管(MOSFET)的情况下,负载端子对应于源极端子和漏极端子,而控制端子对应于栅极端子。在双极结型晶体管(BJT)的情况下,负载端子对应于集电极端子和发射极端子,而控制端子对应于基极端子。在绝缘栅双极晶体管(IGBT)的情况下,负载端子对应于集电极端子和发射极端子,而控制端子对应于栅极端子。
在一些实施方式中,设置从晶体管的第二负载端子到封装件的第一引脚的第一电连接。设置从第二负载端子到封装件的第二引脚的第二电连接。下面参照附图进一步讨论这种配置的示例。可以例如通过磁场传感器装置在第一电连接上执行电流感测。第二电连接可以与切换晶体管结合使用,例如用于在第二负载端子是源极端子的情况下施加栅源电压。
本文使用的封装件是用于一个或更多个半导体芯片管芯的外壳。封装件通常包括一个或更多个引脚以提供电连接。芯片管芯经由诸如接合线或如连接夹(clip)的其他金属连接件之类的电连接而被连接至引脚。
如本文所使用的,引脚是指封装件的可用于将芯片连接至“外部世界”的任何电连接,包括例如“经典的”细长引脚以及例如在表面安装器件(SMD)元件中使用的电连接或用于大电流装置的螺丝端子。
图1示出了根据一个实施方式的装置。图1的装置包括设置在封装件10内的开关晶体管11。开关晶体管11可以包括任何上述类型的晶体管,并且包括第一负载端子T1、第二负载端子T2和控制端子C。封装件10包括至少四个引脚,在图1中示出了引脚13A至13D。可以设置另外的引脚以提供附加的电连接。
第一负载端子T1例如经由接合线或其他电连接而电耦接至引脚13A。
控制端子C耦接至引脚13B。第二负载端子经由第一电连接14耦接至引脚13C并经由第二电连接15耦接至引脚13D,第二电连接至少部分地不同于第一电连接。“至少部分地不同”在本文中是指在第一电连接14和第二电连接15“分支(branch apart)”之前可以是、但不一定是某个共同的电气路径。
虽然端子T1、C和T2分别示出为直接电耦接至引脚13A和13B,但是应当注意,可以在电连接中设置其他电路,例如用于保护开关晶体管11免受静电放电(ESD)事件的ESD保护电路。在图1的实施方式中,开关晶体管11可以经由引脚13B和13C被控制,引脚13C和第一电连接14提供例如用于当经由引脚13B向控制端子C施加控制电压以使控制端子C充电/放电时的电流流动的“返回路径”。通过处于接通状态的开关晶体管11从第一负载端子T1流向第二负载端子的负载电流将至少部分地经由第二电连接15流通。在一些实施方式中,第一电连接14可以具有比第二电连接15低的电感。在其他实施方式中,第一电连接15的电感可以高于或等于第二电连接15的电感。通过提供用于上述“返回路径”的具有相对低的电感的和/或至少部分地与承载负载电流的连接隔开的连接,可以在一些实施方式中实现具有相对小的损失的快速切换。
另一方面,在电连接15具有足够高的电感的实施方式中,例如大于10nH的量级的电感,例如10nH至30nH,当开关晶体管11闭合且电流经由负载端子T1、T2在引脚13A和13D之间流动时,生成足够高的磁场以实现通过如图1中的可选电流传感器12那样的基于磁场的电流传感器进行的准确感测。
应该注意的是,尽管图1的装置包括仅单个开关晶体管11,但是在其他实施方式中,开关晶体管11可以是也可以包括多个开关晶体管和/或其他电路部件的更大电路的一部分。
现在将参照图2和图3说明电感对开关晶体管的开关性能的影响。图2示出了用于仿真的简单电路,并且图3示出了相应的仿真结果。
在图2中,金属氧化物半导体场效应晶体管(MOSFET)20由栅极驱动器23经由栅极电阻器22控制。MOSFET 20的漏极端子耦接至出于仿真目的为400V的电压VH。在接通状态下由栅极驱动器23生成的栅极电压出于仿真目的可以是例如12V。栅极驱动器23被提供有正电源电压Vsupply。
在一些仿真中,如连接24所指示的,MOSFET 20的源极端子直接耦接至栅极驱动器23。对于其他仿真,如连接25所指示的,MOSFET 20的源极端子经由出于仿真目的设置为15nH的电感21耦接至栅极驱动器23。因此,当切换MOSFET 20时,用于一些仿真的栅源电流经由连接24而不经由电感21流动,并且用于其他仿真的栅源电流经由包括电感21的连接25流动。此外,出于仿真的目的,晶体管20的偏置电流被设定为5A。栅极电阻22被设定为3.3Ω的值,并且MOSFET 20被设定为60mΩ的导通电阻。当通过栅极驱动器23向MOSFET 20的栅极施加适当的信号从而将MOSFET 20从关断状态切换到接通状态时,负载电流将开始从MOSFET 20的漏极端子经由MOSFET 20和电感21向接地节点流动。当栅极驱动器23经由连接25耦接至MOSFET 20的源极端子时,负载电流和栅源电流共享电感21。当栅极驱动器23经由连接24耦接至MOSFET 20的源极端子时,负载电流流过的电感21被栅源电流旁路。应该注意的是,虽然用于仿真的值可以对应于一些装置的实际值,但是在其他装置实现中,这些值可以例如根据所使用的开关晶体管的目的(例如,待切换的电流、待切换的电压、电路环境等)显著变化。因此,这些值应被视为仅用于说明。
图3示出了当关闭MOSFET 20时随时间变化的仿真结果。曲线30和31示出了随时间变化的漏源电压Vds,其在关闭MOSFET 20时从电压VH=400V下降到几乎0,并且图3示出了漏极电流Id。曲线30、32示出了连接24(没有电感21)的性能,曲线31、33示出了连接25(包括电感21)的性能。
可以看出,对于包括电感21的连接25,切换相当慢(与曲线30相比,曲线31中的电压滞后下降,并且与曲线32相比,曲线33中的电流上升较慢)。此外,由于电感21,在连接25的情况下,MOSFET 20中的功耗(实质上是随时间积分的漏电流和漏源电压的乘积)相当高。在连接25的情况下,在接通MOSFET 20时负载电流33的变化引起电感21处的电压降,这降低了MOSFET 20处的有效栅源电压,从而减缓了MOSFET 20的接通。在连接24的情况下,栅极驱动器23限定了MOSFET 20处的有效栅源电压,这是因为栅极驱动器通过使用连接24将电感21旁路。连接24中的(图2中未示出的)可选的附加电感或寄生电感不重要,因为只有小的栅源电流而不是大的负载电流流过该可选的电感。
接下来,出于说明的目的,将参照图4和图5来讨论根据一个实施方式的装置实现。图4是根据一个实施方式的装置的局部透视图,以及图5是沿着图4中的线A-A’所截取的示意性截面图。图4和图5的装置包括部分示出的芯片封装件内的功率晶体管44芯片管芯。位于功率晶体管44的后侧处的功率晶体管44的漏极耦接至引脚40D,示出了引脚40D的引向封装件外的实际引脚的一部分。功率晶体管44的栅极端子接触区域45耦接至引脚40A,再次示出了引脚40A的引向封装件外的实际引脚的一部分。
功率晶体管44的被设置为大接触区域43的源极端子经由金属连接夹41耦接至引脚40G(仅部分地示出)。所示实施方式中的金属连接夹41具有U形部,其上设置有磁场传感器42,如在图5的截面图中可以明显看到的那样。在其他实施方式中,可以设置具有包括直线形状的另一形状的金属连接夹。磁场传感器42可以包括磁阻元件,其元件50A、50B在图5的截面图中示出。磁阻元件50A、50B可以与(图5中未示出的)另外的磁阻元件或者与(图5中未示出的)参考电阻一起耦接在桥电路中。通过将这样的U形连接夹41与桥式构造一起使用,可以提高对杂散磁场的容差,如将在下面参照图6进一步说明的。
如在图4中可以看到的,传感器42经由接合线耦接至同样仅部分示出的引脚40B、40C、40E和40F。图4的实施方式中的引脚40F用于向传感器42提供正电源电压,引脚40B用作接地连接,并且引脚40E和40C用作信号线以用于分接指示感测到的磁场和因此流动的电流的差分信号。在一些实施方式中,在漏极引脚40D的两侧上设置信号引脚40E、40C可以降低源极和漏极之间的负载部分对传感器信号的电容和电感耦合性能,并且因此最大限度地最小化共模干扰。由于引脚40E、40C上的信号是差分信号,因此,在实施方式中共模分量被抵消。在其他实施方式中,代替接合线,电连接可以以其他方式实现来取代接合线,并且可以例如包括例如通过在期望的接触区处具有开口的电介质上电镀沉积或钎焊金属而施加的接合线、接合带和/或金属棒来给出一些非限制性示例。
利用连接夹41上的构造以及具有经由引脚40C、40E的差分信号的分接的传感器元件50A、50B的桥式耦合,可以获得相比杂散磁场而言相对较高的鲁棒性。为了说明,图6示出了由流过金属连接夹41的电流产生的示例性磁场60根据沿第一水平方向x变化的横向位置而变化。点61指示磁场矢量在具有在图5的传感器元件50B处的传感器42的第一表面的平面中的分量,而点62说明了磁场矢量在具有在图5的传感器元件50A处的传感器42的第一表面的平面中的分量。可以看出,磁场在传感器50A、50B处分别具有相反的符号。相比之下,在与传感器元件50A、50B之间的距离对应的标尺上仅具有微小变化的杂散磁场通常将在传感器元件50A、50B处具有相同的符号。通过相应的桥式电路或通过由传感器元件50A感测到的场与由传感器元件50B感测到的场之间的差值,杂散磁场可以至少大部分被抵消,而只有由流过连接夹41的电流产生的磁场基本上有助于测量结果。
返回图4,连接夹41基于其长度和形状可以具有相对高的电感,例如大于10nH,例如在10nH和30nH之间,但不限于此。这可能导致较慢的切换性能,如上面参照图2和3所描述的。
因此,在图4的实施方式中,在功率晶体管44的源极端子43与引脚40B之间设置以接合线形式的附加电连接46。为了切换功率晶体管44,在引脚40A和40B之间施加栅源电压,使得当功率晶体管44的栅极端子充电或放电时流过的电流不经由连接夹41流动,而是经由接合线46流动。这种情况下,不从控制功率晶体管44的栅极驱动器的驱动电压中减去由连接夹41提供的电感两端的附加电压降,并且切换可以更快,如参照图2和图3所描述的。
应该注意的是,在其他实施方式中,可以在到功率晶体管44的漏极连接上设置传感器,而不是如图4所示的源极连接。然而,在一些实施方式中,在源极连接处设置传感器可以减少由传感器看到的电压侧翼(flank)。
应该注意的是,在图4中,引脚40B同时用作传感器42的以及经由用于控制功率晶体管44的接合线46至源极的连接的接地引脚。这在实施方式中节约了引脚。尽管如此,在其他实施方式中,可以设置单独的引脚。
在图4的实施方式中,经由接合线46设置(除了连接夹41以外的)附加的源极连接,这避免了如所描述的在功率晶体管44的切换期间由连接夹41提供的电感处的反馈电压。另一方面,在一些应用中,太快的切换可能是不期望的,或者可能导致由于寄生电路部件而引起的振荡,如图3的曲线30和32所示。在一些应用中,这种振荡也可能是不期望的。另一方面,通过仅使用连接夹41作为源极连接的太慢的切换也可能是不期望的。
为了根据应用来平衡这些需求,在其他实施方式中,可以不在功率晶体管44的源极连接区域43(例如,在源极连接区域43处起始(即具有端部)的接合线)上直接分接附加的源极连接(如接合线46),但可以在连接夹41上的任何位置处设置附加的源极连接。一些示例性位置由图4中的箭头和标签49A至49D标记。所提供的用于负载电流和栅源电流的公共路径长度从接合线46到位置49A到位置49B到位置49C直到位置49D(这些位置只是非限制性的示例)增加,这因此提供了针对切换负载电流对功率晶体管44的有效栅源电压及因而对切换速度的所描述的影响进行微调的可能性。
图7中示出了相应的方法。图7示出了用于设计功率装置的方法,例如图1所示的装置或者图4所示的装置。应该注意的是,图7仅示出与本文描述的附加的负载端子(例如源极)连接有关的总体设计过程的一部分,而完整设计过程可以包括许多附加的动作或事件,例如设计功率晶体管44、设计连接夹41的形式等。因此,除了图7所示的动作或事件之外,也可以在方法中使用其他动作或事件,特别是在常规设计过程中使用的动作或事件。
在图7中的70处,方法包括确定所要求的接通性能,例如所要求的接通速度或所要求的没有振荡。在71处,基于所要求的性能确定用于附加的负载端子连接的分接位置,例如直接在如开关晶体管的源极端子(例如图4中的接合线46)的负载端子处,或在连接夹上的、或负载端子与相应连接夹之间的其他电连接上的任何位置处(例如连接夹41上的位置49A至49D中的任何一个)。这样,可以将负载电流和栅极源电流(的对应于共享路径)的共享电感的任何值微调到期望的值,从而达到所要求的接通性能。
根据以下示例提供了一些非限制性实施方式:
示例1.一种装置,包括:
封装件;以及
设置在封装件中的开关,开关包括控制端子、第一负载端子和第二负载端子,
其中,开关的第二负载端子经由第一电连接与封装件的第一引脚连接,其中,第二负载端子经由第二电连接耦接至封装件的与第一引脚不同的第二引脚,其中,第二电连接至少部分地不同于第一电连接。
示例2.根据示例1的装置,其中,控制端子电耦接至封装件的第三引脚,并且第一负载端子电耦接至封装件的第四引脚。
示例3.根据示例2的装置,其中,第三引脚和第二引脚要被耦接至驱动器电路以驱动开关的切换。
示例4.根据示例2或3的装置,还包括驱动开关的切换的驱动器电路,其中,驱动器电路耦接至第二引脚和第三引脚。
示例5.根据示例1-4中的任一项的装置,还包括相邻于第一电连接布置的磁场传感器装置。
示例6.根据示例5的装置,其中,第一负载端子耦接至封装件的第四引脚,其中,磁场传感器装置包括耦接至封装件的第五引脚的第一信号输出端和耦接至封装件的第六引脚的第二信号输出端,其中,第五引脚和第六引脚设置在第四引脚的相对侧上。
示例7.根据示例5或6的装置,其中,磁场传感器装置包括第一电源端子和第二电源端子,其中,第一电源端子耦接至封装件的第七引脚,并且第二电源端子耦接至第二引脚。
示例8.根据示例1-7中的任一项的装置,其中,开关包括金属氧化物半导体场效应晶体管,其中,第二负载端子是源极端子。
示例9.根据示例1-8中的任一项的装置,其中,第一电连接包括起始于包括所述开关的半导体芯片管芯的第二负载端子接触区域处的金属连接夹。
示例10.根据示例9的装置,其中,第二电连接包括起始于第二负载端子接触区域处的接合线。
示例11.根据示例9或10的装置,其中,第二电连接包括起始于金属连接夹处的接合线。
示例12.一种装置,包括:
封装件;
设置在封装件内的功率开关芯片管芯,功率开关芯片管芯包括控制端子接触区域、第一负载端子接触区域和第二负载端子接触区域,其中,控制端子接触区域耦接至封装件的第一引脚,其中,第一负载端子接触区域耦接至封装件的不同于第一引脚的第二引脚;
金属连接夹,其将第二负载端子接触区域耦接至封装件的第三引脚,
设置在金属连接夹上的电流传感器装置;以及
电连接,其将第二负载端子接触区域耦接至封装件的不同于第三引脚的第四引脚。
示例13.根据示例12的装置,其中,电流传感器装置包括磁场传感器装置,其中,磁场传感器装置的电源端子耦接至第四引脚。
示例14.根据示例12或13的装置,其中,电连接的一端在第二负载端子接触区域处。
示例15.根据示例12-14中任一项的装置,其中,电连接的一端在金属连接夹处。
示例16.根据示例12-15中任一项的装置,其中,电流传感器装置包括耦接至封装件的第五引脚和第六引脚的第一信号端子和第二信号端子,第五引脚和第六引脚被设置在第二引脚的相对侧上。
示例17.根据示例12-16中任一项的装置,其中,金属连接夹包括U形部,其中,电流传感器装置设置在U形部上。
示例18.一种用于设计开关装置的方法,方法包括:
确定开关装置的所要求的接通性能;以及
根据所要求的接通性能确定用于在开关装置的负载端子与封装件的引脚之间的电连接的分接位置。
示例19.根据示例18的方法,其中,确定分接位置包括将分接位置确定为在包括功率开关的芯片管芯上、或在将负载端子耦接至封装件的另一引脚的金属连接夹上。
示例20.根据示例18或19的方法,还包括根据与所要求的接通性能相关联的电感来确定分接位置。
虽然上面已经描述了特定示例,但是这些仅仅是出于说明的目的,而不应被解释为限制。
Claims (20)
1.一种开关装置,包括:
封装件;
被布置在所述封装件中的开关,所述开关包括控制端子、第一负载端子和第二负载端子,其中,所述开关的所述第二负载端子经由第一电连接与所述封装件的第一引脚连接,其中,所述第二负载端子经由第二电连接耦接至所述封装件的与所述第一引脚不同的第二引脚,其中,所述第二电连接至少部分地不同于所述第一电连接;和
磁场传感器装置,其被布置成与所述第一电连接相邻,
其中,所述磁场传感器装置被连接到所述第二引脚,所述第二引脚用作接地连接。
2.根据权利要求1所述的开关装置,其中,所述控制端子电耦接至所述封装件的第三引脚,并且所述第一负载端子电耦接至所述封装件的第四引脚。
3.根据权利要求2所述的开关装置,其中,所述第三引脚和所述第二引脚被配置成耦接至驱动器电路以驱动所述开关的切换。
4.根据权利要求2所述的开关装置,还包括驱动所述开关的切换的驱动器电路,其中,所述驱动器电路耦接至所述第二引脚和所述第三引脚。
5.根据权利要求1所述的开关装置,其中,所述第一负载端子耦接至所述封装件的第四引脚,其中,所述磁场传感器装置包括耦接至所述封装件的第五引脚的第一信号输出端和耦接至所述封装件的第六引脚的第二信号输出端,其中,所述第五引脚和所述第六引脚被布置在所述第四引脚的相对侧上。
6.根据权利要求1所述的开关装置,其中,所述磁场传感器装置包括第一电源端子和第二电源端子,其中,所述第一电源端子耦接至所述封装件的第七引脚,并且所述第二电源端子耦接至所述第二引脚。
7.根据权利要求1所述的开关装置,其中,所述开关包括金属氧化物半导体场效应晶体管,其中,所述第二负载端子是源极端子。
8.一种开关装置,包括:
封装件;
被布置在所述封装件中的开关,所述开关包括控制端子、第一负载端子和第二负载端子;和
被设置在金属连接夹上的磁场传感器装置,
其中,所述开关的所述第二负载端子经由第一电连接与所述封装件的第一引脚连接,其中,所述第二负载端子经由第二电连接耦接至所述封装件的与所述第一引脚不同的第二引脚,其中,所述第二电连接至少部分地不同于所述第一电连接,以及
其中,所述第一电连接包括所述金属连接夹,所述金属连接夹起始于包括所述开关的半导体芯片管芯的第二负载端子接触区域处,以及
其中,所述磁场传感器装置被连接到所述第二引脚,所述第二引脚用作接地连接。
9.根据权利要求8所述的开关装置,其中,所述第二电连接包括起始于所述第二负载端子接触区域处的接合线。
10.根据权利要求8所述的开关装置,其中,所述第二电连接包括起始于所述金属连接夹处的接合线。
11.一种开关装置,包括:
封装件;
被布置在所述封装件内的功率开关芯片管芯,所述功率开关芯片管芯包括控制端子接触区域、第一负载端子接触区域和第二负载端子接触区域,其中,所述控制端子接触区域耦接至所述封装件的第一引脚,其中,所述第一负载端子接触区域耦接至所述封装件的不同于所述第一引脚的第二引脚;
金属连接夹,其将所述第二负载端子接触区域耦接至所述封装件的第三引脚,
被设置在所述金属连接夹上的电流传感器装置;以及
电连接,其将所述第二负载端子接触区域耦接至所述封装件的不同于所述第三引脚的第四引脚,
其中,所述电流传感器装置被连接到所述第四引脚,所述第四引脚用作接地连接。
12.根据权利要求11所述的开关装置,其中,所述电流传感器装置包括磁场传感器装置。
13.根据权利要求11所述的开关装置,其中,所述电连接的一端在所述第二负载端子接触区域处。
14.根据权利要求11所述的开关装置,其中,所述电连接的一端在所述金属连接夹处。
15.根据权利要求11所述的开关装置,其中,所述电流传感器装置包括耦接至所述封装件的第五引脚的第一信号端子和耦接至所述封装件的第六引脚的第二信号端子,所述第五引脚和所述第六引脚被布置在所述第二引脚的相对侧上。
16.根据权利要求11所述的开关装置,其中,所述金属连接夹包括U形部,其中,所述电流传感器装置被设置在所述U形部上。
17.一种用于制造开关装置的方法,所述方法包括:
将功率开关芯片管芯布置在封装件内,所述功率开关芯片管芯包括控制端子、第一负载端子和第二负载端子,所述功率开关芯片管芯包括控制端子接触区域、第一负载端子接触区域和第二负载端子接触区域;
将所述控制端子接触区域耦接至所述封装件的第一引脚;
将所述第一负载端子接触区域耦接至所述封装件的不同于所述第一引脚的第二引脚;
将金属连接夹耦接在所述第二负载端子接触区域与所述封装件的第三引脚之间;以及
将所述第二负载端子接触区域耦接至所述封装件的不同于所述第三引脚的第四引脚,
其中,附接在所述金属连接夹上的电流传感器装置被连接至所述第四引脚,所述第四引脚用作接地连接。
18.根据权利要求17所述的方法,其中,将所述第二负载端子接触区域耦接至所述第四引脚包括将所述第二负载端子接触区域耦接至所述第二负载端子接触区域与所述封装件的第三引脚之间的所述金属连接夹上的第一位置。
19.根据权利要求18所述的方法,其中,所述第一位置基于所述开关装置的所需接通性能和与所需接通性能相关联的感应率。
20.根据权利要求17所述的方法,其中,所述电流传感器装置包括磁场传感器装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/433,447 US10153766B2 (en) | 2017-02-15 | 2017-02-15 | Switch device |
US15/433,447 | 2017-02-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108428686A CN108428686A (zh) | 2018-08-21 |
CN108428686B true CN108428686B (zh) | 2021-12-07 |
Family
ID=62982595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810145752.5A Active CN108428686B (zh) | 2017-02-15 | 2018-02-12 | 开关装置和设计开关装置的方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10153766B2 (zh) |
CN (1) | CN108428686B (zh) |
DE (1) | DE102018103126A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019103030B4 (de) | 2018-04-04 | 2022-03-31 | Infineon Technologies Ag | Transistorvorrichtungen sowie Verfahren zur Herstellung und zum Betreiben von Transistorvorrichtungen |
US20210380060A1 (en) * | 2020-06-04 | 2021-12-09 | Veoneer Us, Inc. | Sensor communication discrete control considering emc compliance for restraint control module |
EP4213386A1 (en) * | 2022-01-13 | 2023-07-19 | Infineon Technologies AG | Semiconductor assembly with semiconductor switching device and current sense unit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1551342A (zh) * | 2003-05-14 | 2004-12-01 | ��ʽ���������Ƽ� | 半导体器件和电源系统 |
US20090073625A1 (en) * | 2007-09-14 | 2009-03-19 | Stmicroelectronics S.R.L. | Power integrated circuit with high insensitivity to parasitic inductances of wires for connection to a package and package for said integrated circuit |
CN106298757A (zh) * | 2015-06-23 | 2017-01-04 | 英飞凌科技股份有限公司 | 具有集成式磁场传感器的功率封装体 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006021774B4 (de) | 2005-06-23 | 2014-04-03 | Siemens Aktiengesellschaft | Stromsensor zur galvanisch getrennten Strommessung |
JP5755533B2 (ja) * | 2011-08-26 | 2015-07-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2017
- 2017-02-15 US US15/433,447 patent/US10153766B2/en active Active
-
2018
- 2018-02-12 CN CN201810145752.5A patent/CN108428686B/zh active Active
- 2018-02-13 DE DE102018103126.2A patent/DE102018103126A1/de active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1551342A (zh) * | 2003-05-14 | 2004-12-01 | ��ʽ���������Ƽ� | 半导体器件和电源系统 |
US20090073625A1 (en) * | 2007-09-14 | 2009-03-19 | Stmicroelectronics S.R.L. | Power integrated circuit with high insensitivity to parasitic inductances of wires for connection to a package and package for said integrated circuit |
CN106298757A (zh) * | 2015-06-23 | 2017-01-04 | 英飞凌科技股份有限公司 | 具有集成式磁场传感器的功率封装体 |
Also Published As
Publication number | Publication date |
---|---|
CN108428686A (zh) | 2018-08-21 |
US10153766B2 (en) | 2018-12-11 |
US20180234093A1 (en) | 2018-08-16 |
DE102018103126A1 (de) | 2018-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108428686B (zh) | 开关装置和设计开关装置的方法 | |
US11652478B2 (en) | Power modules having an integrated clamp circuit and process thereof | |
CN110178444B (zh) | 电路和用于操作电路的方法 | |
US11774523B2 (en) | Transistor devices and methods for producing transistor devices | |
US7864021B2 (en) | Integrated circuit device | |
CN107436407B (zh) | 开关器件中的测量 | |
KR101850906B1 (ko) | 전류 감지 코일을 갖는 집적 회로 | |
US20150346037A1 (en) | Integrated temperature sensor | |
US20160164279A1 (en) | Circuit and method for measuring a current | |
US10545199B2 (en) | Lateral transmission of signals across a galvanic isolation barrier | |
JP2017508287A (ja) | 2つの補助エミッタ導体経路を有する半導体モジュール | |
JP5796599B2 (ja) | 半導体モジュールおよびスイッチング素子の駆動装置 | |
US20130015889A1 (en) | Threshold voltage based power transistor operation | |
CN109756212A (zh) | 驱动控制电路和具有驱动控制电路和晶体管器件的电路 | |
CN109560690A (zh) | 基于iii/v族半导体的电路及运行该电路的方法 | |
US10823789B2 (en) | Fast-switching driver circuit for an inductive load | |
US11652473B2 (en) | Power modules having an integrated clamp circuit and process thereof | |
JP2004340917A (ja) | 電圧降下式電流計測装置 | |
CN111448760B (zh) | 半导体模块 | |
US10116303B2 (en) | Parallel devices having balanced switching current and power | |
Huang et al. | Printed Circuit Board Layout and Probing for GaN Power Switches | |
US11982693B2 (en) | Systems and methods to detect and measure the current mismatch among parallel semiconductor devices | |
CN108292918B (zh) | 用于开关的电子控制装置 | |
US20240003960A1 (en) | Semiconductor device | |
JP2023022558A (ja) | 入力容量測定回路および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |