CN108400128B - Interconnect structure and method of making the same - Google Patents

Interconnect structure and method of making the same Download PDF

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Publication number
CN108400128B
CN108400128B CN201710066478.8A CN201710066478A CN108400128B CN 108400128 B CN108400128 B CN 108400128B CN 201710066478 A CN201710066478 A CN 201710066478A CN 108400128 B CN108400128 B CN 108400128B
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conductive pattern
layer
substrate
etching process
interconnect structure
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CN108400128A (en
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李鸿志
黄旻暄
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An interconnection structure includes a substrate and a conductive pattern. The conductive pattern includes a bottom. The bottom of the conductive pattern is disposed on the substrate. The conductive pattern has notches on both sidewalls of the bottom.

Description

Interconnect structure and method of making the same
Technical Field
The present invention relates to a conductive structure and a method for fabricating the same, and more particularly, to an interconnect structure and a method for fabricating the same.
Background
As the semiconductor industry advances, multilayer interconnect designs are becoming a necessary design for many integrated circuits as the degree of integration of the integrated circuits increases and the surface of the chip does not provide enough area to fabricate the desired interconnect.
As semiconductor devices are gradually scaled down, an overlap margin (overlay window) between an upper conductive element and a lower conductive element therebelow in a multilayer interconnect structure is also reduced, and thus alignment deviation is likely to occur. When the alignment deviation occurs between the upper layer conductive element and the lower layer conductive element in the multi-layer interconnection structure, the upper layer conductive element exposes the lower layer conductive element. As a result, the adjacent two upper conductive elements generate a bridging path (bridging path) through the exposed lower conductive element, thereby generating a circuit bridging defect.
Disclosure of Invention
The invention provides an interconnection structure and a manufacturing method thereof, which can effectively prevent the defect of circuit bridging.
The invention provides an interconnection structure, which comprises a substrate and a conductive pattern. The conductive pattern includes a bottom. The bottom of the conductive pattern is disposed on the substrate. The conductive pattern has notches on both sidewalls of the bottom.
According to an embodiment of the invention, in the interconnect structure, the position of the minimum width of the conductive pattern is, for example, at the gap.
According to an embodiment of the present invention, in the interconnect structure, the conductive pattern further includes a middle portion and a top portion. The middle portion is located between the top portion and the bottom portion. The position of the maximum width of the conductive pattern is, for example, at the middle portion.
In the interconnect structure, the position of the maximum width of the conductive pattern is, for example, a transition position of a positive slope and a negative slope.
According to an embodiment of the present invention, the interconnect structure further includes a first barrier layer. The first barrier layer is arranged between the conductive pattern and the substrate. The width of the first barrier layer may be greater than the minimum width of the conductive pattern.
According to an embodiment of the present invention, the interconnect structure further includes a first barrier layer. The first barrier layer is arranged between the conductive pattern and the substrate. The gap can be located at the interface of the conductive pattern and the first barrier layer.
According to an embodiment of the present invention, the interconnect structure further includes a dielectric layer. The dielectric layer is arranged on the substrate at two sides of the conductive pattern. The gap may be between the dielectric layer and the conductive pattern.
The invention provides a manufacturing method of an interconnection structure, which comprises the following steps. A substrate is provided. A conductive pattern is formed on a substrate. The conductive pattern includes a bottom. The conductive pattern has notches on both sidewalls of the bottom.
According to an embodiment of the present invention, in the method for manufacturing an interconnect structure, the method for manufacturing a conductive pattern includes the following steps. A conductive pattern material layer is formed on a substrate. A patterned mask layer is formed on the conductive pattern material layer. The patterned mask layer is used as a mask to perform a first etching process on the conductive pattern material layer. The first etching gas used in the first etching process comprises chlorine (Cl)2) With boron trichloride (BCl)3). The flow rate of boron trichloride in the first etching process is less than or equal to the flow rate of chlorine. After the first etching process, the patterned mask layer is used as a mask to perform a second etching process on the conductive pattern material layer. The second etching gas used in the second etching process includes chlorine and boron trichloride. The flow rate of boron trichloride in the second etching process is greater than that of chlorine.
According to an embodiment of the present invention, in the method for manufacturing an interconnect structure, a dielectric layer is formed on the substrate on both sides of the conductive pattern. The gap may be between the dielectric layer and the conductive pattern.
In view of the above, in the interconnect structure and the method for manufacturing the same provided by the present invention, since the conductive pattern has the notches on the two sidewalls of the bottom, a Critical Dimension (CD) of the bottom of the conductive pattern can be reduced to increase an overlap margin between the conductive pattern and the conductive element therebelow, thereby preventing a defect of circuit bridging. In addition, since the other part of the conductive pattern except the bottom has a larger width, and a larger cross-sectional area can be maintained, a low resistance value and a low RC delay (RC delay) can be maintained.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1E are cross-sectional views illustrating a manufacturing process of an interconnect structure according to an embodiment of the invention.
Description of reference numerals:
100: substrate
102. 106: barrier material layer
102a, 106 a: barrier layer
104: layer of conductive pattern material
104 a: conductive pattern
108: patterned mask layer
110. 112, 112: gap
114: dielectric layer
116: hole(s)
BP: bottom part
EF: etch front
MP: intermediate section
TP: top part
W1: minimum width
W2: maximum width
W3, W4: width of
Detailed Description
Fig. 1A to fig. 1E are cross-sectional views illustrating a manufacturing process of an interconnect structure according to an embodiment of the invention.
First, referring to fig. 1A, a substrate 100 is provided. The substrate 100 may be a single-layer substrate or a multi-layer substrate, and may have other layers (not shown), conductive elements (not shown) or semiconductor elements (not shown) formed thereon.
Next, a barrier material layer 102 may be optionally formed on the substrate 100. The material of the barrier material layer 102 is, for example, Ti, TiN, Ta, TaN, or a combination thereof. The barrier material layer 102 is formed by a physical vapor deposition method or a chemical vapor deposition method.
Then, a conductive pattern material layer 104 is formed on the barrier material layer 102. The material of the conductive pattern material layer 104 is, for example, AlCu, Al, or W. The conductive pattern material layer 104 is formed by, for example, physical vapor deposition or chemical vapor deposition.
Next, a barrier material layer 106 may be optionally formed on the conductive pattern material layer 104. The material of the barrier material layer 106 is, for example, Ti, TiN, Ta, TaN, or a combination thereof. The barrier material layer 106 is formed by a physical vapor deposition method or a chemical vapor deposition method.
Thereafter, a patterned mask layer 108 is formed on the barrier material layer 106. The material of the patterned mask layer 108 is, for example, a patterned photoresist layer or a patterned hard mask layer. The material of the patterned photoresist layer is, for example, a positive photoresist material or a negative photoresist material. The material of the patterned hard mask layer is, for example, amorphous carbon (amorphous carbon), silicon nitride or silicon oxide.
Referring to fig. 1B, a portion of the barrier material layer 106 is removed by using the patterned mask layer 108 as a mask, and a barrier layer 106a is formed on the conductive pattern material layer 104. The barrier material layer 106 is partially removed by, for example, performing an etching process (e.g., a dry etching process) on the barrier material layer 106 using the patterned mask layer 108 as a mask.
Subsequently, a first etching process is performed on the conductive pattern material layer 104 by using the patterned mask layer 108 as a mask. After the first etching process, the shape of the etch front (etch front) EF in the conductive pattern material layer 104 may be similar to a U-shape (U-shape). The first etching process is, for example, a dry etching process.
The first etching gas used in the first etching process includes chlorine and boron trichloride. The flow rate of boron trichloride in the first etching process is less than or equal to the flow rate of chlorine. The ratio of the flow rates of boron trichloride and chlorine in the first etching process is 0.3 to 1. In one embodiment, the flow rates of boron trichloride and chlorine in the first etching process may be 0.5 to 1.
In addition, the first etching gas further includes a shielding gas. The protective gas is, for example, methane, nitrogen, tetrafluoromethane, trifluoromethane, or a combination thereof. In the first etching process, the flow rate of methane is, for example, 5sccm to 20sccm, the flow rate of nitrogen is, for example, 5sccm to 20sccm, the flow rate of tetrafluoromethane is, for example, 0sccm to 15sccm, and the flow rate of trifluoromethane is, for example, 0sccm to 15 sccm.
In addition, during the first etching process, the process pressure is, for example, 2mTorr to 35mTorr, the RF power is, for example, 100W to 1500W, and the RF bias power is, for example, 15W to 500W. In one embodiment, the first etch process is performed at a process pressure of, for example, 4mTorr to 20mTorr, a RF power source of, for example, 400W to 1200W, and a RF bias power of, for example, 50W to 200W.
Next, referring to fig. 1C, after the first etching process is performed, a second etching process is performed on the conductive pattern material layer 104 by using the patterned mask layer 108 as a mask, so as to form a conductive pattern 104a on the barrier material layer 102. The second etching process may be an etch front modified etch process. That is, after the second etching process is performed, the shape of the etching front edge EF in the conductive pattern material layer 104 may be adjusted from the U-shape to a shape having an undercut (undercut). As such, the overall shape of the conductive pattern 104a may be similar to a bottle shape (bottle shape). The second etching process is, for example, a dry etching process. In addition, when the second etching process is performed, a portion of the barrier material layer 102 may be selectively removed.
The second etching gas used in the second etching process includes chlorine and boron trichloride. The flow rate of boron trichloride in the second etching process is greater than that of chlorine. The ratio of the flow rates of boron trichloride and chlorine gas in the second etching process is 1.3 to 5. In one embodiment, the flow rates of boron trichloride and chlorine in the second etching process may be 1.5 to 2.5.
In addition, the second etching gas further includes a shielding gas. The protective gas is, for example, methane, nitrogen, tetrafluoromethane, trifluoromethane, or a combination thereof. In the second etching process, the flow rate of methane is, for example, 0sccm to 5sccm, the flow rate of nitrogen is, for example, 5sccm to 20sccm, the flow rate of tetrafluoromethane is, for example, 0sccm to 5sccm, and the flow rate of trifluoromethane is, for example, 0sccm to 5 sccm.
In addition, during the second etching process, the process pressure is, for example, 2mTorr to 30mTorr, the RF power is, for example, 100W to 1500W, and the RF bias power is, for example, 15W to 200W. In one embodiment, the second etch process is performed at a process pressure of, for example, 2mTorr to 15mTorr, a RF power of, for example, 500W to 1200W, and a RF bias power of, for example, 50W to 200W.
The conductive pattern 104a includes a bottom BP. The conductive pattern 104a has notches 110 on both sidewalls of the bottom BP. The critical dimension of the bottom BP of the conductive pattern 104a can be reduced by the gap 110, so as to increase the overlapping margin between the conductive pattern 104a and the conductive element therebelow, thereby preventing the generation of the defect of circuit bridging. The minimum width W1 of the conductive pattern 104a is located at the notch 110, for example.
The conductive pattern 104a further includes a middle portion MP and a top portion TP. The middle portion MP is located between the top portion TP and the bottom portion BP. The conductive pattern 104a may also have a gap 112 on each of two sidewalls of the top portion TP, but the invention is not limited thereto. In another embodiment, the conductive pattern 104a may not have the gap 112 on both sidewalls of the top portion TP.
Further, the maximum width W2 of the conductive pattern 104a is located at the middle portion MP, for example. The position of the maximum width W2 of the conductive pattern 104a is, for example, a transition position of a positive slope and a negative slope. The width W3 at the top TP may be between the minimum width W1 and the maximum width W2. In this embodiment, the bottom portion BP and the middle portion MP may be approximately separated by a minimum width W1, and the top portion TP and the middle portion MP may be approximately separated by a width W3, but the invention is not limited thereto.
Next, referring to fig. 1D, a portion of the barrier material layer 102 is removed by using the patterned mask layer 108 as a mask, so as to form a barrier layer 102a between the conductive pattern 104a and the substrate 100. The barrier material layer 102 is partially removed by, for example, performing an etching process (e.g., a dry etching process) on the barrier material layer 102 using the patterned mask layer 108 as a mask. The width W4 of the barrier layer 102a may be greater than the minimum width W1 of the conductive pattern 104 a.
In addition, the gap 110 may be adjacent to the interface between the conductive pattern 104a and the barrier layer 102 a. For example, the gap 110 can be located at the interface between the conductive pattern 104a and the barrier layer 102 a. In another embodiment, when the interconnect structure does not have the barrier layer 102a, the gap 110 may be adjacent to the interface between the conductive pattern 104a and the substrate 100. For example, the gap 110 may be located at the interface between the conductive pattern 104a and the substrate 100.
The patterned mask layer 108 may then be removed. The patterned mask layer 108 is removed by, for example, dry removal or wet removal. For example, the patterned mask layer 108 may be removed by ashing (ash) the patterned mask layer 108 with oxygen plasma and then removing the ashed residues by wet cleaning. In another embodiment, when the patterned mask layer 108 is a patterned hard mask layer of silicon nitride or silicon oxide, for example, the patterned mask layer 108 may not be removed.
Although the method for manufacturing the conductive pattern 104a of the present embodiment is described by taking the above-mentioned manufacturing method as an example, the method for manufacturing the conductive pattern 104a of the present invention is not limited thereto.
Next, referring to fig. 1E, a dielectric layer 114 is formed on the substrate 100 at two sides of the conductive pattern 104 a. The gap 110 may be located between the dielectric layer 114 and the conductive pattern 104 a. In addition, the dielectric layer 114 can also fill part of the gap 110. In addition, the gap 112 may be located between the dielectric layer 114 and the conductive pattern 104a, and the dielectric layer 114 may also fill a portion of the gap 112. On the other hand, depending on the quality of the hole-filling capability, a hole 116 may be formed in the dielectric layer 114 between two adjacent conductive patterns 104 a. The material of the dielectric layer 114 is, for example, silicon oxide. The dielectric layer 114 is formed by, for example, chemical vapor deposition.
Based on the above embodiments, since the conductive pattern 104a has the notches 110 on the two sidewalls of the bottom BP, the critical dimension of the bottom BP of the conductive pattern 104a can be reduced, so as to increase the overlapping margin between the conductive pattern 104a and the conductive element therebelow, thereby preventing the defect of circuit bridging. In addition, since the conductive pattern 104a has a larger width at the other portion except the bottom BP, a larger cross-sectional area can be maintained, so that a low resistance value and a low rc delay can be maintained.
The interconnect structure of the present embodiment is described below with reference to fig. 1E. Although the method for manufacturing the interconnect structure of the present embodiment is described by taking the above-described manufacturing method as an example, the method for manufacturing the interconnect structure of the present invention is not limited thereto.
Referring to fig. 1E, the interconnect structure includes a substrate 100 and a conductive pattern 104 a. The conductive pattern 104a includes a bottom BP. The bottom BP of the conductive pattern 104a is disposed on the substrate 100. The conductive pattern 104a has notches 110 on both sidewalls of the bottom BP. The conductive pattern 104a further includes a middle portion MP and a top portion TP. The middle portion MP is located between the top portion TP and the bottom portion BP. The conductive pattern 104a may optionally have a gap 112 on both sidewalls of the top portion TP. In addition, the interconnect structure may further optionally include at least one of the barrier layer 102a, the barrier layer 106a and the dielectric layer 114. The barrier layer 102a is disposed between the conductive pattern 104a and the substrate 100. The barrier layer 106a is disposed on the conductive pattern 104 a. The dielectric layer 114 is disposed on the substrate 100 at two sides of the conductive pattern 104 a. A hole 116 may be optionally formed in the dielectric layer 114 between two adjacent conductive patterns 104 a. In addition, the materials, arrangement, formation methods and effects of the components in the interconnect structure are described in detail in the manufacturing method of fig. 1A to 1E, and thus are not described herein again.
In summary, in the interconnect structure and the method for fabricating the same according to the above embodiments, since the conductive pattern has the notches on the two sidewalls of the bottom, the critical dimension of the bottom of the conductive pattern can be reduced to increase the overlapping margin between the conductive pattern and the conductive element therebelow, thereby preventing the occurrence of the defect of circuit bridging. In addition, the conductive pattern has a larger width at the other part except the bottom part, so that a larger cross section area can be kept, and low resistance capacitance delay can be maintained.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (9)

1. An interconnect structure, comprising:
a substrate;
a conductive pattern including a bottom and a top, wherein the bottom of the conductive pattern is disposed on the substrate, and the conductive pattern has a bottom gap on two sidewalls of the bottom, and a top gap on two sidewalls of the top; and
a first barrier layer disposed between the conductive pattern and the substrate, wherein the bottom gap is located at an interface between the conductive pattern and the first barrier layer.
2. The interconnect structure of claim 1 wherein a location of a minimum width of the conductive pattern is located at the bottom gap.
3. The interconnect structure of claim 2, wherein the conductive pattern further comprises a middle portion, the middle portion being located between the top portion and the bottom portion, and a location of a maximum width of the conductive pattern being located at the middle portion.
4. The interconnect structure of claim 3, wherein the location of the maximum width of the conductive pattern is a transition location of a positive slope and a negative slope.
5. The interconnect structure of claim 2, wherein the width of the first barrier layer is greater than the minimum width of the conductive pattern.
6. The interconnect structure of claim 1, further comprising a dielectric layer disposed on the substrate on both sides of the conductive pattern, wherein the bottom gap and the top gap are located between the dielectric layer and the conductive pattern.
7. A method of fabricating an interconnect structure, comprising:
providing a substrate; and
forming a conductive pattern on the substrate, wherein the conductive pattern comprises a bottom and a top, the conductive pattern has a bottom gap on two side walls of the bottom, and the conductive pattern also has a top gap on two side walls of the top; and
providing a first barrier layer disposed between the conductive pattern and the substrate, wherein the bottom gap is located at an interface between the conductive pattern and the first barrier layer.
8. The method of claim 7, wherein the method of manufacturing the conductive pattern comprises:
forming a conductive pattern material layer on the substrate;
forming a patterned mask layer on the conductive pattern material layer;
performing a first etching process on the conductive pattern material layer by using the patterned mask layer as a mask, wherein a first etching gas used in the first etching process comprises chlorine and boron trichloride, and the flow of the boron trichloride in the first etching process is less than or equal to that of the chlorine; and
after the first etching process, a second etching process is performed on the conductive pattern material layer by using the patterned mask layer as a mask, wherein a second etching gas used in the second etching process includes the chlorine gas and the boron trichloride, and the flow rate of the boron trichloride in the second etching process is greater than that of the chlorine gas.
9. The method as claimed in claim 7, further comprising forming a dielectric layer on the substrate on both sides of the conductive pattern, wherein the bottom gap and the top gap are located between the dielectric layer and the conductive pattern.
CN201710066478.8A 2017-02-07 2017-02-07 Interconnect structure and method of making the same Active CN108400128B (en)

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CN111900167B (en) * 2020-06-28 2024-04-05 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof

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CN1381880A (en) * 2001-04-13 2002-11-27 华邦电子股份有限公司 Outline-control method for etching metal layer
CN1471136A (en) * 2002-07-01 2004-01-28 株式会社半导体能源研究所 Method for manufacturing semiconductor device
CN1630042A (en) * 2003-12-18 2005-06-22 上海华虹Nec电子有限公司 Multistep dry process etching method for metal wiring
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