CN1630042A - Multistep dry process etching method for metal wiring - Google Patents
Multistep dry process etching method for metal wiring Download PDFInfo
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- CN1630042A CN1630042A CN 200310109600 CN200310109600A CN1630042A CN 1630042 A CN1630042 A CN 1630042A CN 200310109600 CN200310109600 CN 200310109600 CN 200310109600 A CN200310109600 A CN 200310109600A CN 1630042 A CN1630042 A CN 1630042A
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Abstract
A multistage dry etching method for metal wiring in microelectronic manufacturing field contains adding buffer stage in conversion of different technological conditions to reduce the wire width difference change, end point detecting respectively to anti-inversion film and metal layer by imitating the plasma lighting wavelength change to control accurately the etching time in said stage. By said method the stable shape and resistance metal wiring can be obtained.
Description
Technical field
The relevant microelectronics manufacture of the present invention field, the multistep dry process etching method of especially relevant a kind of metal wiring.
Background technology
Along with the development of semiconductor fabrication, live width and its spacing of metal wiring also constantly dwindle.During less than 0.32um,, improve the very little method Cp﹠amp that produces in batches in metal wiring live width and spacing in order to obtain stable photolithographic exposure size; Cpk, need be on metal the anti-transmitting film ARC of deposit one deck (Anti-Reflect Coating).Therefore in the dry etching process, want the multiple membrane structure of etching successively: the oxide-film of ARC (its composition is silicon oxynitride/silica)/titanium nitride/titanium/metal/titanium nitride/titanium/down.As shown in Figure 1: the skin of metal wiring has sandwich construction, comprises two-layer titanium nitride/titanium layer, and its top is coated with silicon oxynitride/silicon oxide layer, and the bottom coats has ground oxide-film down.Existing carry out etching with 3 steps or 4 steps usually, it can satisfy general etching requirement, yet rate of finished products can not guarantee, easily the problem of appearance as shown in Fig. 2 (A)-Fig. 2 _ (D).Defective as shown in Fig. 2 (A) reduces the cross-sectional area of metal, increases the metal wire impedance.Owing to reduced the TiN area on metal wire and top, the very big influence of meeting contacts with upper strata Via's, influences interconnection impedance.Defective shown in Fig. 2 (B) reduces the cross-sectional area of metal, increases the metal wire impedance.And, produce cavity (void) in the time of can influencing interlayer film (HDP) deposit because metal wire caves inward.Produce broken string (open fault) when the defective shown in Fig. 2 (C) is serious, the cross-sectional area of metal is reduced, increase the metal wire impedance.Equally, the defective shown in Fig. 2 (D) reduces the cross-sectional area of metal, increases the metal wire impedance.
Therefore, should design a kind of multistep lithographic method of new metal wiring, accurately control the etching precision of metal wiring.
Summary of the invention
For a change the defective in the prior art the objective of the invention is: a kind of multistep dry process etching method that can effectively control the metal wiring etching precision is provided.
In order to realize goal of the invention of the present invention, the multistep dry process etching method of a kind of metal wiring of the present invention, the section of this metal wiring has sandwich construction, comprise two-layer titanium nitride/titanium layer, the top of its titanium nitride/titanium layer is coated with silicon oxynitride/silicon oxide layer, the bottom is coated with down the ground oxide-film, and its processing step is:
Silicon oxynitride/silica main etching at certain pressure, source power, bias power and reacting gas, comprises chlorine and fluoroform, carries out the end point determination of etching in the etching process by the variation of emission wavelength of simulation element;
Silicon oxynitride/silica over etching, it determines etch period according to the inhomogeneity of CVD (chemical vapor deposition) thickness and the internal homogeneity of etch rate, prevents to have behind this EOS silicon oxynitride or silica residual;
Metal wire top titanium nitride/titanium etching, the numerical value of the source power that reduces to provide in the etching process also increases bias power numerical value to reduce plasma density, reduce chloride ion content, thereby and add boron trichloride gas to increase reaction product protection metal sidewall;
Buffering step increases source power and pressure, reduces bias power simultaneously, increases chlorine and chloroform content, makes titanium and metal cross surface place's deposit reaction product, protects metal sidewall;
The master metal etching further increases chlorine content, and carries out the etching terminal detection by the emission wavelength of simulation aluminium chloride, and terminal point switches to the full over etching step of etch rate immediately once detecting;
The metal over etching reduces chlorine content, thereby reduces etch rate, reduces the ratio of source power and bias power simultaneously, can be with the complete etching of metal remained;
The titanium nitride/titanium etching of metal wire bottom further strengthens bias power, to reduce the difference in size between the two membranes;
The oxide-film etching is controlled etch period down, has both avoided titanium nitride residual, avoids down the etch amount of ground oxide-film dark excessively again, and influencing next step interlayer film can not complete filling.
Owing to adopt technique scheme, during different technology conditions etching multi-layer film structure in the multistep dry process etching method of the present invention, when process conditions are rotated, increase to cushion to go on foot and reduce linewidth difference, thereby make that the precision of etching is higher, can access resistance-stable metal wiring.
Description of drawings
Fig. 1 is the structural representation after the metal wiring etching under the normal condition;
Fig. 2 be the prior art lithographic method the schematic diagram of the technological deficiency that occurs easily;
The cutaway view of the multi-layer film structure that Fig. 3 is on the metal wiring to be had;
Fig. 4 is the process chart of metal wiring multistep dry etching of the present invention;
Wherein:
ARC is anti-emission rete, and its composition is silicon oxynitride/silica, and Al is an aluminium lamination, and TiN/Ti is the titanium nitride/titanium layer.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
See also shown in Figure 3ly, have the membrane structure of multilayer on the metallic aluminium distribution, comprise two-layer titanium nitride/titanium layer, the top of its titanium nitride/titanium layer is coated with anti-transmitting film (ARC, Anti-Reflect Coating, its composition are silicon oxynitride/silica) layer, the bottom is coated with down the ground oxide-film.In order to obtain accurate live width, when above-mentioned each tunic of etching, accurately control the process conditions in the etching process.In the present embodiment, the thickness of metal aluminum steel is 4500 , and two-layer titanium nitride/titanium layer thickness is 500 , and silica/silicon oxide layer thickness that the top of its titanium nitride/titanium layer coats is 600 , so the gross thickness of film is 6100 .The bottom is coated with down ground oxide thickness 800A.
See also Fig. 3 and shown in Figure 4, in etching process, will have certain pressure, source power, bias power and gas.At first carry out the ARC main etching, its pressure is 8mTorr, and source power is 1200W, and bias power is 30W, the chlorine of 80sccm unit and the fluoroform of 6sccm unit.In etching process, the end point determination of etching is carried out in the variation of the emission wavelength by simulation F element.Then carry out the over etching of ARC, its process conditions are: pressure 8mTorr, and source power is 1200W, and bias power is 30W, and the fluoroform of the chlorine of 80 units and 6 units is identical with the process conditions of previous step.Consider the internal homogeneity of inhomogeneity and section's erosion speed of CVD (chemical vapor deposition) thickness, add over etching, can prevent to have after this from not finishing silicon oxynitride or silica residual.Can accurately control the etch period of ARC by above-mentioned two steps.Then carry out the titanium nitride/titanium at aluminum steel top, its process conditions are: pressure 8M Torr, and source power is 800W, bias power is 130W, the boron chloride of the chlorine of 15sccm unit, the fluoroform of 2sccm unit and 70sccm unit.Because from then on the step beginning is excessively to metal etch; reduce the density that source power can reduce plasma; can reduce chemical etching speed (in metal etch; chemical etching is the principal element that influences etch rate); in gas, increase boron chloride; increase the physics corrasion on the one hand; on the other hand since boron chloride in course of reaction; be easy to produce more reaction product; this product is not volatile; be deposited on the aluminum steel sidewall, protective side wall effectively, thus reach the size of metal wire after the accurate control etching.
If after carrying out the titanium nitride etching, directly carry out the aluminium etching, can be because under identical etching condition, the etch rate of metallic aluminium is faster than the etch rate of Titanium, when etching during excessively to metallic aluminium, is easy to generate linewidth difference from Titanium.Similarly, because the etch rate of aluminium is fast, can make the aluminium lateral etching more, will dwindle than titanium, form a step from the size of aluminium in shape than titanium at horizontal direction.Therefore carving the adding buffering step between aluminium and the titanium nitride, its process conditions are the compromise of two steps, are specially: pressure 10mTorr, and source power is 1000W, bias power is 100W, the boron chloride of the chlorine of 50sccm unit, the fluoroform of 10sccm unit and 40 sccm units.Add the fluoroform of big flow,, can protect the aluminium sidewall not by too much etching at cross surface place deposit one deck reaction product of titanium and aluminium, and excessively arrive the main etching of aluminium because this gas has the effect of very strong deposit reaction product.
Carry out the main etching of aluminium below, in this process, carry out etching terminal by the emission wavelength of simulating AlCl and detect, and in order to prevent the appearance of aluminium bottom notch shape, the mode of taking etching to detect makes terminal point switch to the slow over etching step of etch rate immediately once detecting.Its concrete process conditions are: pressure 10mTorr, and source power is 1000W, bias power is 100W, the boron chloride of the chlorine of 60sccm unit, the fluoroform of 5sccm unit and 35 sccm units.Consider equipment capacity, under the prerequisite that does not influence the aluminium shape, the flow that strengthens chlorine can increase etch rate, and the shape in order to guarantee that aluminium is vertical again will reduce the flow of fluoroform.The over etching of aluminium is considered the deposit thickness of aluminium and the inhomogeneity of etch rate, adds over etching, can residual aluminium etching is clean.Its process conditions are: pressure 10mTorr, source power is 600W, bias power is 120W, the boron chloride of the chlorine of 40sccm unit, the fluoroform of 5sccm unit and 35 sccm units, reduce source power, can reduce the density that produces plasma in the reaction chamber, and then reduce the same tropism of etching, prevent that the aluminium bottom from by lateral etching, producing the bad shape that caves inward.Reduce the ratio of source power and bias power, can reduce the chemical reaction ratio, increase the physics reaction ratio, thereby reduce because of the different micro loading effects that produce of aluminum steel bar density.Reducing the flow of chlorine, also is in order to reduce etch rate, prevents the generation of the bad shape that caves inward.
Then carry out the titanium nitride/titanium etching of aluminum steel bottom, and be the etching of aluminium and the transition step of following ground oxide-film, poor in order to the very little method (CD) that reduces between the film, avoid titanium nitride residual.Its process conditions are: pressure 10mTorr, and source power is 600W, bias power is 150W, the boron chloride of the chlorine of 30sccm unit, the fluoroform of 9sccm unit and 30 sccm units.Because the chemical etching speed ratio aluminium of titanium is slow, so strengthen bias power, can strengthen the proportion of physical shock (reaction) in this step, can reduce the difference in size between the two membranes.
Will descend the etching of ground oxide-film at last, its process conditions are: pressure 10mTorr, and source power is 600W, bias power is 150W, the boron chloride of the chlorine of 30sccm unit, the fluoroform of 5sccm unit and 30 sccm units.In etching process, to control etch period, both avoid the nitride metal titanium residual, avoid down the etch amount of ground oxide-film dark excessively again, can not complete filling (cavity occurring) when influencing next step interlayer film deposit.Can reduce the flow of fluoroform in right amount to the etching of oxide-film down.
In like manner, the present invention also can be used for the dry etching of other metal wiring.
In sum, the goal of the invention that can finish the inventor of the present invention provides and can accurately control etching precision, prevents the various deficiencies of prior art, and high-quality metal wiring is provided when integrated circuit is made.
Claims (3)
1, a kind of multistep dry process etching method of metal wiring, the section of this metal wiring has multi-layer film structure, comprises two-layer titanium nitride/titanium layer, and the top of its titanium nitride/titanium layer is coated with silicon oxynitride/silicon oxide layer, the bottom is coated with down the ground oxide-film, and its processing step is:
Silicon oxynitride/silica main etching, under certain pressure, source power, bias power and reacting gas condition, carry out, wherein gas comprises chlorine and fluoroform, carries out the end point determination of etching in the etching process by the variation of emission wavelength of simulation element;
Silicon oxynitride/silica over etching, it determines etch period according to the thick inhomogeneity of chemical vapor deposition film and the internal homogeneity of etch rate, prevents to have behind this EOS silicon oxynitride or silica residual;
Metal wire top titanium nitride/titanium etching, the numerical value of the source power that reduces to provide in the etching process also increases bias power numerical value to reduce plasma density, reduce chloride ion content, thereby and add boron trichloride gas to increase reaction product protection metal sidewall;
Buffering step increases source power and pressure, reduces bias power simultaneously, increases chlorine and chloroform content, makes titanium and metal cross surface place's deposit reaction product, protects metal sidewall;
The master metal etching further increases chlorine content, and carries out the etching terminal detection by the emission wavelength of simulation aluminium chloride, and terminal point switches to the slow over etching step of etch rate immediately once detecting;
The metal over etching reduces chlorine content, thereby reduces etch rate, reduces the ratio of source power and bias power simultaneously, can be with the complete etching of metal remained;
The titanium nitride/titanium etching of metal wire bottom further strengthens bias power, to reduce the difference in size between the two membranes;
The oxide-film etching is controlled etch period down, has both avoided titanium nitride residual, avoids down the etch amount of ground oxide-film dark excessively again, and influencing next step interlayer film can not complete filling.
2, the multistep dry process etching method of metal wiring as claimed in claim 1 is characterized in that: described metal can be aluminium.
3, the multistep dry process etching method of metal wiring as claimed in claim 1 or 2 is characterized in that: at the simulation element described in silicon oxynitride/silica main etching step is the F element.
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| CNB2003101096003A CN1328767C (en) | 2003-12-18 | 2003-12-18 | Multistep dry process etching method for metal wiring |
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| CNB2003101096003A CN1328767C (en) | 2003-12-18 | 2003-12-18 | Multistep dry process etching method for metal wiring |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7713831B2 (en) | 2006-09-29 | 2010-05-11 | Hynix Semiconductor Inc. | Method for fabricating capacitor in semiconductor device |
| CN101452846B (en) * | 2007-11-30 | 2010-05-26 | 上海华虹Nec电子有限公司 | Thick aluminum film forming process |
| CN101346807B (en) * | 2006-07-28 | 2010-12-08 | 住友精密工业株式会社 | End point detectable plasma etching method and plasma etching apparatus |
| CN101162693B (en) * | 2006-10-09 | 2011-02-16 | 西安能讯微电子有限公司 | Gallium nitride surface low damnification etching |
| CN102024669B (en) * | 2009-09-09 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing reflection power in plasma etching |
| CN108400128A (en) * | 2017-02-07 | 2018-08-14 | 旺宏电子股份有限公司 | Interconnection structure and its manufacturing method |
| CN109860043A (en) * | 2018-12-13 | 2019-06-07 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate preparation method |
| CN112530802A (en) * | 2020-11-30 | 2021-03-19 | 北京北方华创微电子装备有限公司 | Etching control method |
| JP2022505863A (en) * | 2018-10-30 | 2022-01-14 | アプライド マテリアルズ インコーポレイテッド | Methods for Etching Structures for Semiconductor Applications |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101740469B (en) * | 2008-11-17 | 2012-05-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing aluminum wiring |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08274099A (en) * | 1995-03-29 | 1996-10-18 | Yamaha Corp | Wiring forming method |
| JPH09289212A (en) * | 1996-04-19 | 1997-11-04 | Ricoh Co Ltd | Laminated wiring of semiconductor device and its fabrication method |
| JP2985858B2 (en) * | 1997-12-19 | 1999-12-06 | 日本電気株式会社 | Etching method |
| JP2002134475A (en) * | 2000-10-24 | 2002-05-10 | Sony Corp | Etching method |
| CN1379454A (en) * | 2001-04-09 | 2002-11-13 | 华邦电子股份有限公司 | Method for preventing generation of metal wire phenomenon |
| JP2003109948A (en) * | 2001-10-02 | 2003-04-11 | Matsushita Electric Ind Co Ltd | Formation method of wiring |
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| CN101346807B (en) * | 2006-07-28 | 2010-12-08 | 住友精密工业株式会社 | End point detectable plasma etching method and plasma etching apparatus |
| US7713831B2 (en) | 2006-09-29 | 2010-05-11 | Hynix Semiconductor Inc. | Method for fabricating capacitor in semiconductor device |
| CN101162693B (en) * | 2006-10-09 | 2011-02-16 | 西安能讯微电子有限公司 | Gallium nitride surface low damnification etching |
| CN101452846B (en) * | 2007-11-30 | 2010-05-26 | 上海华虹Nec电子有限公司 | Thick aluminum film forming process |
| CN102024669B (en) * | 2009-09-09 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing reflection power in plasma etching |
| CN108400128A (en) * | 2017-02-07 | 2018-08-14 | 旺宏电子股份有限公司 | Interconnection structure and its manufacturing method |
| CN108400128B (en) * | 2017-02-07 | 2020-10-16 | 旺宏电子股份有限公司 | Interconnect structure and method of making the same |
| JP2022505863A (en) * | 2018-10-30 | 2022-01-14 | アプライド マテリアルズ インコーポレイテッド | Methods for Etching Structures for Semiconductor Applications |
| JP7179172B6 (en) | 2018-10-30 | 2022-12-16 | アプライド マテリアルズ インコーポレイテッド | Method for etching structures for semiconductor applications |
| JP7179172B2 (en) | 2018-10-30 | 2022-11-28 | アプライド マテリアルズ インコーポレイテッド | Method for etching structures for semiconductor applications |
| CN109860043A (en) * | 2018-12-13 | 2019-06-07 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate preparation method |
| CN109860043B (en) * | 2018-12-13 | 2021-03-16 | 深圳市华星光电半导体显示技术有限公司 | Array substrate preparation method |
| CN112530802A (en) * | 2020-11-30 | 2021-03-19 | 北京北方华创微电子装备有限公司 | Etching control method |
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Effective date of registration: 20171213 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Granted publication date: 20070725 Termination date: 20181218 |