CN108400128A - Interconnection structure and its manufacturing method - Google Patents
Interconnection structure and its manufacturing method Download PDFInfo
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- CN108400128A CN108400128A CN201710066478.8A CN201710066478A CN108400128A CN 108400128 A CN108400128 A CN 108400128A CN 201710066478 A CN201710066478 A CN 201710066478A CN 108400128 A CN108400128 A CN 108400128A
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- conductive pattern
- interconnection structure
- layer
- substrate
- etch process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Abstract
A kind of interconnection structure, including substrate and conductive pattern.Conductive pattern includes bottom.The bottom of conductive pattern is set in substrate.Conductive pattern respectively has notch on the two side of bottom.
Description
Technical field
The invention relates to a kind of conductive structure and its manufacturing methods, and in particular to a kind of interconnection structure and its
Manufacturing method.
Background technology
With the development of semiconductor industry, when the integrated level of integrated circuit increases, the surface of chip can not provide enough
Area is come when making required interconnection structure, the interconnection structure design of multilayer, which just gradually becomes many integrated circuits, to adopt
Design method.
As semiconductor element is gradually reduced, the Upper conductive element in multilayer interconnection structure and underlying conductive below
The overlapping nargin (overlay window) of element can also become smaller, therefore be easy to happen deviation of the alignment.When in multilayer interconnection structure
Upper conductive element with below underlying conductive element occur deviation of the alignment when, Upper conductive element can expose below
Underlying conductive element.Thus, two adjacent Upper conductive elements can by the underlying conductive element exposed and
Generate bridge path (bridging path), and then the defect of generation circuit bridge joint (circuit bridging).
Invention content
A kind of interconnection structure of present invention offer and its manufacturing method, can be effectively prevented the defect of generation circuit bridge joint.
The present invention proposes a kind of interconnection structure, including substrate and conductive pattern.Conductive pattern includes bottom.Conductive pattern
Bottom is set in substrate.Conductive pattern respectively has notch on the two side of bottom.
Described in one embodiment of the invention, in above-mentioned interconnection structure, the position example of the minimum widith of conductive pattern
It is located at indentation, there in this way.
Described in one embodiment of the invention, in above-mentioned interconnection structure, conductive pattern further includes middle part and top.
Middle part is between top and bottom.The position of the maximum width of conductive pattern is, for example, to be located at middle part.
Described in one embodiment of the invention, in above-mentioned interconnection structure, the position example of the maximum width of conductive pattern
The transition position of positive slope and negative slope in this way.
Further include the first barrier layer in above-mentioned interconnection structure described in one embodiment of the invention.First barrier layer
It is set between conductive pattern and substrate.The width of first barrier layer can be more than the minimum widith of conductive pattern.
Further include the first barrier layer in above-mentioned interconnection structure described in one embodiment of the invention.First barrier layer
It is set between conductive pattern and substrate.Notch can be located at the interface of conductive pattern and the first barrier layer.
Further include dielectric layer in above-mentioned interconnection structure described in one embodiment of the invention.Dielectric layer, which is set to, leads
In the substrate of electrical pattern both sides.Notch can be between dielectric layer and conductive pattern.
The present invention proposes a kind of manufacturing method of interconnection structure, includes the following steps.Substrate is provided.It is formed and is led in substrate
Electrical pattern.Conductive pattern includes bottom.Conductive pattern respectively has notch on the two side of bottom.
Described in one embodiment of the invention, in the manufacturing method of above-mentioned interconnection structure, the manufacturer of conductive pattern
Method includes the following steps.Conductive pattern material layer is formed in substrate.Patterning cover curtain layer is formed in conductive pattern material layer.
To pattern cover curtain layer as mask, the first etch process is carried out to conductive pattern material layer.Used in first etch process
One etching gas includes chlorine (Cl2) and boron chloride (BCl3).The flow of boron chloride in first etch process is less than or waits
In the flow of chlorine.After carrying out the first etch process, to pattern cover curtain layer as mask, conductive pattern material layer is carried out
Second etch process.Second etching gas used in second etch process includes chlorine and boron chloride.Second etch process
In boron chloride flow be more than chlorine flow.
Further include in conductive pattern in the manufacturing method of above-mentioned interconnection structure described in one embodiment of the invention
Dielectric layer is formed in the substrate of both sides.Notch can be between dielectric layer and conductive pattern.
Based on above-mentioned, in interconnection structure and its manufacturing method proposed by the invention, since conductive pattern is in bottom
Respectively there is notch on two side, therefore the critical size (critical dimension, CD) of the bottom of conductive pattern can be reduced,
To improve overlapping nargin of the conductive pattern with conducting element below, and then it can prevent the defect of circuit bridge.In addition,
Since other parts of the conductive pattern other than bottom have larger width, and then larger sectional area can be possessed, therefore energy
Enough maintain low resistance and low resistance capacitance delays (RC delay).
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Description of the drawings
Figure 1A to Fig. 1 E is the manufacturing process sectional view of the interconnection structure of one embodiment of the invention.
Reference sign：
100：Substrate
102、106：Barrier material layer
102a、106a：Barrier layer
104：Conductive pattern material layer
104a：Conductive pattern
108：Pattern cover curtain layer
110、112：Notch
114：Dielectric layer
116：Hole
BP：Bottom
EF：Etch leading edge
MP：Middle part
TP：Top
W1：Minimum widith
W2：Maximum width
W3、W4：Width
Specific implementation mode
Figure 1A to Fig. 1 E is the manufacturing process sectional view of the interconnection structure of one embodiment of the invention.
First, Figure 1A is please referred to, substrate 100 is provided.Substrate 100 can be single layer substrates or multi-layer substrate, and can be formed with
Other film layers (not being painted), conducting element (not being painted) or semiconductor element (not being painted) are thereon.
Then, barrier material layer 102 is optionally formed in substrate 100.The material of barrier material layer 102 is, for example,
Ti, TiN, Ta, TaN or combinations thereof.The forming method of barrier material layer 102 is, for example, physical vaporous deposition or chemical vapor deposition
Area method.
Then, conductive pattern material layer 104 is formed on barrier material layer 102.The material example of conductive pattern material layer 104
AlCu, Al or W in this way.The forming method of conductive pattern material layer 104 is, for example, physical vaporous deposition or chemical vapor deposition
Method.
Next, optionally forming barrier material layer 106 in conductive pattern material layer 104.Barrier material layer 106
Material be, for example, Ti, TiN, Ta, TaN or combinations thereof.The forming method of barrier material layer 106 is, for example, physical vaporous deposition
Or chemical vapour deposition technique.
Later, patterning cover curtain layer 108 is formed on barrier material layer 106.Patterning cover curtain layer 108 material be, for example,
Pattern photoresist layer or patterning curtain layer of hard hood.The material for patterning photoresist layer is, for example, positive photoresist or negative photoresist.
The material for patterning curtain layer of hard hood is, for example, amorphous carbon (amorphous carbon), silicon nitride or silica.
Furthermore Figure 1B is please referred to, to pattern cover curtain layer 108 as mask, removes part barrier material layer 106, and is being led
Barrier layer 106a is formed in electrical pattern material layer 104.The removing method of part barrier material layer 106 is, for example, to pattern mask
Layer 108 is mask, and processing procedure (e.g., dry etch process) is etched to barrier material layer 106.
Then, to pattern cover curtain layer 108 as mask, the first etch process is carried out to conductive pattern material layer 104.Into
After the first etch process of row, the shape of etching leading edge (etch front) EF in conductive pattern material layer 104 can be similar
In U-shaped (U-shape).First etch process is, for example, dry etch process.
First etching gas used in first etch process includes chlorine and boron chloride.Three in first etch process
The flow of boron chloride is less than or equal to the flow of chlorine.The flow proportional of boron chloride and chlorine in first etch process is in this way
0.3 to 1.In one embodiment, the flow of the boron chloride in the first etch process and chlorine can be 0.5 to 1.
In addition, the first etching gas further includes protective gas.Protective gas is, for example, methane, nitrogen, tetrafluoromethane, trifluoro
Methane or combinations thereof.In the first etch process, the flow of methane is, for example, 5sccm to 20sccm, and the flow of nitrogen is, for example,
5sccm to 20sccm, the flow of tetrafluoromethane are, for example, 0sccm to 15sccm, the flow of fluoroform be, for example, 0sccm extremely
15sccm。
In addition, when carrying out the first etch process, process pressure is, for example, 2mTorr to 35mTorr, radio-frequency power supply power
E.g. 100W to 1500W, and RF bias power is, for example, 15W to 500W.In one embodiment, the first etching system is being carried out
Cheng Shi, process pressure are, for example, 4mTorr to 20mTorr, and radio-frequency power supply power is, for example, 400W to 1200W, and rf bias work(
Rate is, for example, 50W to 200W.
Followed by, Fig. 1 C are please referred to, after carrying out the first etch process, to pattern cover curtain layer 108 for mask, to conduction
Pattern material layer 104 carries out the second etch process, and conductive pattern 104a can be formed on barrier material layer 102.Second etching
Processing procedure can be that etching leading edge adjusts etch process (etch front modified etch process).Also that is, carrying out the
After two etch process, the shape of the etching leading edge EF in conductive pattern material layer 104 can be adjusted to have undercutting from U-shaped
(undercutting) shape.Thus, which the global shape of conductive pattern 104a can be similar to ampuliform (bottle
shape).Second etch process is, for example, dry etch process.In addition, when carrying out the second etch process, optionally move
Except part barrier material layer 102.
Second etching gas used in second etch process includes chlorine and boron chloride.Three in second etch process
The flow of boron chloride is more than the flow of chlorine.The flow proportional in this way 1.3 of boron chloride and chlorine in second etch process to
5.In one embodiment, the flow of the boron chloride in the second etch process and chlorine can be 1.5 to 2.5.
In addition, the second etching gas further includes protective gas.Protective gas is, for example, methane, nitrogen, tetrafluoromethane, trifluoro
Methane or combinations thereof.In the second etch process, the flow of methane is, for example, 0sccm to 5sccm, and the flow of nitrogen is, for example,
5sccm to 20sccm, the flow of tetrafluoromethane are, for example, 0sccm to 5sccm, the flow of fluoroform be, for example, 0sccm extremely
5sccm。
In addition, when carrying out the second etch process, process pressure is, for example, 2mTorr to 30mTorr, radio-frequency power supply power
E.g. 100W to 1500W, and RF bias power is, for example, 15W to 200W.In one embodiment, the second etching system is being carried out
Cheng Shi, process pressure are, for example, 2mTorr to 15mTorr, and radio-frequency power supply power is, for example, 500W to 1200W, and rf bias work(
Rate is, for example, 50W to 200W.
Conductive pattern 104a includes bottom BP.Conductive pattern 104a respectively has notch 110 on the two side of bottom BP.It borrows
The critical size that the bottom BP of conductive pattern 104a can be reduced by notch 110, to improve conductive pattern 104a and leading below
The overlapping nargin of electric device, and then can prevent the defect of circuit bridge.The position of the minimum widith W1 of conductive pattern 104a
E.g. it is located at notch 110.
Conductive pattern 104a further includes middle part MP and top TP.Middle part MP is between top TP and bottom BP.It leads
Electrical pattern 104a also optionally respectively has notch 112 on the two side of top TP, but the present invention is not limited thereto.
In another embodiment, conductive pattern 104a also can not jagged 112 on the two side of top TP.
In addition, the position of the maximum width W2 of conductive pattern 104a is, for example, to be located at middle part MP.Conductive pattern 104a's
The position of maximum width W2 is, for example, the transition position of positive slope and negative slope.Width W3 positioned at top TP can be between minimum wide
It spends between W1 and maximum width W2.In this embodiment, bottom BP and middle part MP can the rough position with minimum widith W1 do
For boundary, top TP and middle part MP can the rough position with width W3 as boundary, but the present invention is not limited thereto.
Next, please refer to Fig. 1 D, to pattern cover curtain layer 108 as mask, part barrier material layer 102 is removed, and
Barrier layer 102a is formed between conductive pattern 104a and substrate 100.The removing method of part barrier material layer 102 is, for example, to scheme
Case cover curtain layer 108 is mask, and processing procedure (e.g., dry etch process) is etched to barrier material layer 102.Barrier layer 102a's
Width W4 can be more than the minimum widith W1 of conductive pattern 104a.
In addition, notch 110 can be adjacent to the interface of conductive pattern 104a and barrier layer 102a.For example, notch 110 can
Positioned at the interface of conductive pattern 104a and barrier layer 102a.In another embodiment, when interconnection structure does not have barrier layer 102a
When, notch 110 can be adjacent to the interface of conductive pattern 104a and substrate 100.For example, notch 110 can be located at conductive pattern
The interface of 104a and substrate 100.
Then, patterning cover curtain layer 108 can be removed.The removing method of patterning cover curtain layer 108 is, for example, that dry type removes method
Or wet type removes method.For example, the removing method of patterning cover curtain layer 108 first can use oxygen plasma-based to patterning testis curtain layer 108
It is ashed (ash), then is removed the residue after ashing with wet-cleaning method.In another embodiment, when patterning mask
When layer 108 is, for example, the patterning curtain layer of hard hood of silicon nitride or silica, patterning cover curtain layer 108 can not be removed.
Although the manufacturing method of the conductive pattern 104a of the present embodiment is illustrated by taking above-mentioned manufacturing method as an example, this
The manufacturing method of the conductive pattern 104a of invention is not limited thereto.
Then, Fig. 1 E are please referred to, form dielectric layer 114 in the substrate 100 of the both sides conductive pattern 104a.Notch 110 can
Between dielectric layer 114 and conductive pattern 104a.In addition, dielectric layer 114 can also be inserted in partial notch 110.In addition, notch
112 can be between dielectric layer 114 and conductive pattern 104a, and dielectric layer 114 can also be inserted in partial notch 112.Another party
The good and bad situation for filling out hole ability is depended in face, and hole may be formed in the dielectric layer 114 between two neighboring conductive pattern 104a
Hole 116.The material of dielectric layer 114 is, for example, silica.The forming method of dielectric layer 114 is, for example, chemical vapour deposition technique.
Based on above-described embodiment it is found that since conductive pattern 104a respectively has notch 110 on the two side of bottom BP, because
This can reduce the critical size of the bottom BP of conductive pattern 104a, conductive pattern 104a and conducting element below can be improved
Overlapping nargin, and then can prevent the defect of circuit bridge.Further, since its other than the BP of bottom of conductive pattern 104a
He partly has larger width, and then can possess larger sectional area, therefore is able to maintain that low resistance is prolonged with low resistance capacitance
Late.
Hereinafter, illustrating the interconnection structure of the present embodiment by Fig. 1 E.In addition, the manufacturer of the interconnection structure of the present embodiment
Although method is to be illustrated by taking above-mentioned manufacturing method as an example, but the manufacturing method of the interconnection structure of the present invention is not limited thereto.
Fig. 1 E are please referred to, interconnection structure includes substrate 100 and conductive pattern 104a.Conductive pattern 104a includes bottom BP.
The bottom BP of conductive pattern 104a is set in substrate 100.Conductive pattern 104a respectively has notch on the two side of bottom BP
110.Conductive pattern 104a further includes middle part MP and top TP.Middle part MP is between top TP and bottom BP.Conductive pattern
Case 104a optionally respectively has notch 112 on the two side of top TP.In addition, interconnection structure is also optionally included with
At least one of barrier layer 102a, barrier layer 106a and dielectric layer 114.Barrier layer 102a is set to conductive pattern 104a and base
Between bottom 100.Barrier layer 106a is set on conductive pattern 104a.Dielectric layer 114 is set to the base of the both sides conductive pattern 104a
On bottom 100.Optionally there is hole 116 in dielectric layer 114 between two neighboring conductive pattern 104a.In addition, mutually
Material, set-up mode, forming method and effect of each component in connection structure are in the manufacturing method of above-mentioned Figure 1A to Fig. 1 E
At large illustrated, therefore is repeated no more in this.
In conclusion in the interconnection structure and its manufacturing method that are proposed in above-described embodiment, since conductive pattern is the bottom of at
Respectively there is notch on the two side in portion, therefore the critical size of the bottom of conductive pattern can be reduced, to improve conductive pattern and its
The overlapping nargin of the conducting element of lower section, and then can prevent the defect of circuit bridge.Further, since conductive pattern is in bottom
Other parts in addition have larger width, and then can possess larger sectional area, therefore are able to maintain that low resistance and low electricity
Hinder capacitance delays.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any people in the art
Member, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention is when regarding
Subject to the defining of claim.
Claims (10)
1. a kind of interconnection structure, which is characterized in that including：
One substrate；And
The bottom of one conductive pattern, including a bottom, the wherein conductive pattern is set in the substrate, and the conductive pattern exists
Respectively there is a notch on the two side of the bottom.
2. the position of interconnection structure according to claim 1, wherein a minimum widith of the conductive pattern is located at the notch
Place.
3. interconnection structure according to claim 2, the wherein conductive pattern further include a middle part and a top, among this
Portion is located between the top and the bottom, and the position of a maximum width of the conductive pattern is located at the middle part.
4. interconnection structure according to claim 3, the wherein position of the maximum width of the conductive pattern be positive slope with
The transition position of negative slope.
5. interconnection structure according to claim 2 further includes one first barrier layer, is set to the conductive pattern and the substrate
Between, wherein the width of first barrier layer is more than the minimum widith of the conductive pattern.
6. interconnection structure according to claim 1 further includes one first barrier layer, is set to the conductive pattern and the substrate
Between, wherein the notch is located at the interface of the conductive pattern and first barrier layer.
7. interconnection structure according to claim 1 further includes a dielectric layer, it is set to the substrate of the conductive pattern both sides
On, wherein the notch is located between the dielectric layer and the conductive pattern.
8. a kind of manufacturing method of interconnection structure, which is characterized in that including：
One substrate is provided；And
A conductive pattern is formed on this substrate, and wherein the conductive pattern includes a bottom, and the conductive pattern is in the bottom
Respectively there is a notch on two side.
9. the manufacturing method of the manufacturing method of interconnection structure according to claim 8, the wherein conductive pattern includes：
A conductive pattern material layer is formed on this substrate；
A patterning cover curtain layer is formed in the conductive pattern material layer；
Using the patterning cover curtain layer as mask, one first etch process is carried out to the conductive pattern material layer, wherein first erosion
It scribes one first etching gas used in journey and includes a chlorine and a boron chloride, and the trichlorine in first etch process
The flow for changing boron is less than or equal to the flow of the chlorine；And
After carrying out first etch process, using the patterning cover curtain layer as mask, one is carried out to the conductive pattern material layer
Second etch process, wherein one second etching gas used in second etch process include the chlorine and the boron chloride,
And the flow of the boron chloride in second etch process is more than the flow of the chlorine.
10. the manufacturing method of interconnection structure according to claim 8 further includes in the substrate of the conductive pattern both sides
A dielectric layer is formed, wherein the notch is located between the dielectric layer and the conductive pattern.
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| CN201710066478.8A CN108400128B (en) | 2017-02-07 | 2017-02-07 | Interconnect structure and method of making the same |
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| CN111900167A (en) * | 2020-06-28 | 2020-11-06 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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| CN108400128B (en) | 2020-10-16 |
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