TWI686912B - Interconnect structure and fabricating method thereof - Google Patents

Abstract

An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

Description

Interconnection structure and manufacturing method thereof

The invention relates to a conductive structure and a manufacturing method thereof, and particularly relates to an interconnect structure and a manufacturing method thereof.

With the development of the semiconductor industry, when the accumulation degree of integrated circuits increases and the surface of the chip cannot provide enough area to make the required interconnects, the multilayer interconnect design gradually becomes a number of integrated circuits. The design method that must be adopted.

As the semiconductor element gradually shrinks, the overlap window (overlay window) of the upper conductive element and the lower conductive element in the multilayer interconnection structure will also become smaller, so alignment deviations are likely to occur. When the alignment deviation between the upper conductive element and the lower conductive element under the multilayer interconnection structure, the upper conductive element will expose the lower conductive element under it. In this way, the two adjacent upper-layer conductive elements will generate a bridging path through the exposed lower-layer conductive elements, thereby generating defects in circuit bridging.

The invention provides an interconnection structure and a manufacturing method thereof, which can effectively prevent the defects of the circuit bridge.

The present invention provides an interconnect structure including a substrate, a dielectric layer, a first conductive pattern and a second conductive pattern. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern, and exposes the exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

According to an embodiment of the invention, in the above interconnect structure, the material of the first conductive pattern is, for example, W, Ti, TiN, Ta or TaN.

According to an embodiment of the invention, in the above interconnect structure, the material of the second conductive pattern is, for example, AlCu, Al or W.

According to an embodiment of the invention, in the above interconnect structure, the width of the second conductive pattern may be smaller than the width of the first conductive pattern, and the exposed portion of the first conductive pattern may be located on one side of the second conductive pattern Or both sides.

According to an embodiment of the invention, in the above interconnect structure, the notch may expose part of the side wall of the opening.

The invention provides a method for manufacturing an interconnect structure, which includes the following steps. A dielectric layer is formed on the substrate, wherein the dielectric layer has an opening. A first conductive pattern is formed in the opening. A second conductive pattern is formed on the first conductive pattern. The second conductive pattern exposes the exposed portion of the first conductive pattern. A notch is formed in the exposed portion of the first conductive pattern.

According to an embodiment of the present invention, in the above method for manufacturing an interconnect structure, the formation method of the notch, for example, uses the second conductive pattern as a mask, and performs an etching process on the exposed portion of the first conductive pattern to partially The exposed portion of the first conductive pattern.

According to an embodiment of the present invention, in the above method for manufacturing an interconnect structure, the etching gas used in the etching process includes chlorine gas and shielding gas. Based on the total amount of chlorine gas and protective gas, the content of chlorine gas is, for example, 50% by volume to 96% by volume.

According to an embodiment of the present invention, in the manufacturing method of the interconnection structure, the protective gas is, for example, nitrogen (N ₂ ), boron trichloride (BCl ₃ ), trifluoromethane (CHF ₃ ), methane ( CH ₄ ) or a combination thereof.

According to an embodiment of the invention, in the above method for manufacturing an interconnect structure, the etching gas further includes an inert gas.

Based on the above, in the interconnect structure and the manufacturing method thereof proposed by the present invention, since the exposed portion of the first conductive pattern exposed by the second conductive pattern has a gap, the adjacent two second conductive patterns can be cut off Bridging path between. In this way, the interconnect structure and the manufacturing method thereof proposed by the present invention can prevent the defects of the circuit bridge, and can effectively increase the overlapping margin of the second conductive pattern and the first conductive pattern.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

1A to 1D are cross-sectional views of the manufacturing process of the interconnect structure according to an embodiment of the invention.

First, referring to FIG. 1A, a dielectric layer 102 is formed on a substrate 100, wherein the dielectric layer 102 has an opening 104. The substrate 100 may be a single-layer substrate or a multi-layer substrate, and other film layers (not shown) or semiconductor devices (not shown) may be formed thereon. The material of the dielectric layer 102 is, for example, silicon oxide. The method of forming the dielectric layer 102 is, for example, a chemical vapor deposition method. The opening 104 is, for example, a contact hole, a via hole, or a trench. The method for forming the opening 104 is, for example, a patterning process on the dielectric layer 102.

Next, referring to FIG. 1B, a barrier layer 106 can be selectively formed on the surface of the opening 104. The material of the barrier layer 106 is, for example, Ti, TiN, Ta, TaN, or a combination thereof.

Then, a conductive pattern 108 is formed on the barrier layer 106 in the opening 104. The barrier layer 106 can be used to increase the adhesion between the conductive pattern 108 and other film layers. The conductive pattern 108 is, for example, a plug or a wire, wherein the plug may be a contact window plug or a via window plug. The material of the conductive pattern 108 is, for example, W, Ti, TiN, Ta, or TaN.

The method of forming the barrier layer 106 and the conductive pattern 108 is exemplified as follows, but the invention is not limited thereto. First, a barrier material layer (not shown) is conformally formed on the dielectric layer 102. The method for forming the barrier material layer is, for example, a physical vapor deposition method or a chemical vapor deposition method. Next, a conductive pattern material layer (not shown) filling the opening 104 is formed on the barrier material layer. The method for forming the conductive pattern material layer is, for example, a physical vapor deposition method or a chemical vapor deposition method. Then, the conductive pattern material layer and the barrier material layer other than the opening 104 are removed. The method for removing the conductive pattern material layer and the barrier material layer other than the opening 104 is, for example, a chemical mechanical polishing method or an etch-back method.

Next, referring to FIG. 1C, a barrier layer 110 may be selectively formed on the conductive pattern 108. The material of the barrier layer 110 is, for example, Ti, TiN, Ta, TaN, or a combination thereof.

After that, a conductive pattern 112 is formed on the barrier layer 110. The conductive pattern 112 exposes the exposed portion EP of the conductive pattern 108. The barrier layer 110 can be used to increase the adhesion between the conductive pattern 112 and other film layers. In this embodiment, the exposed portion EP of the conductive pattern 108 may be located on one side of the conductive pattern 112. The width of the conductive pattern 112 may be greater than, equal to or less than the width of the conductive pattern 108. The conductive pattern 112 is, for example, a wire or a plug, where the plug may be a contact window plug or a via window plug. The material of the conductive pattern 112 is, for example, AlCu, Al, or W.

Furthermore, a barrier layer 114 can be selectively formed on the conductive pattern 112. The material of the barrier layer 114 is, for example, Ti, TiN, Ta, TaN, or a combination thereof. The barrier layer 114 can be used to increase the adhesion between the film layer formed thereon and the conductive pattern 112.

The formation methods of the barrier layer 114, the conductive pattern 112 and the barrier layer 110 are exemplified as follows, but the invention is not limited thereto. First, a stacked structure of a barrier material layer (not shown), a conductive pattern material layer (not shown) and a barrier material layer (not shown) is sequentially formed on the dielectric layer 102. The method for forming the barrier material layer and the conductive pattern material layer is, for example, a physical vapor deposition method or a chemical vapor deposition method. Next, a patterning process is performed on the stacked structure of the barrier material layer, the conductive pattern material layer, and the barrier material layer.

Next, referring to FIG. 1D, a notch 116 is formed in the exposed portion EP of the conductive pattern 108. Since the notch 116 can cut off the bridge path between the two adjacent conductive patterns 112, the defect of the circuit bridge can be prevented, and the overlapping margin of the conductive pattern 112 and the conductive pattern 108 can be effectively increased. The notch 116 may expose part of the side wall of the opening 104. The exposed portion EP of the conductive pattern 108 exposed by the notch 116 may have a slope.

The formation method of the notch 116 is, for example, using the conductive pattern 112 as a mask, and performing an etching process on the exposed portion EP of the conductive pattern 108 to partially remove the exposed portion EP of the conductive pattern 108. The exposed portion EP of the conductive pattern 108 can be removed by in-situ etching. During the etching process of the exposed portion EP of the conductive pattern 108, a part of the barrier layer 106 on the sidewall of the opening 104 may be simultaneously removed. In addition, in the above etching process, the etching rate of the barrier layer 106 is, for example, greater than the etching rate of the exposed portion EP of the conductive pattern 108.

The etching gas used in the etching process includes chlorine gas and shielding gas. Based on the total amount of chlorine gas and protective gas, the content of chlorine gas is, for example, 50% by volume to 96% by volume. The protective gas is, for example, nitrogen, boron trichloride, trifluoromethane, methane, or a combination thereof. In addition, the etching gas further includes an inert gas. The inert gas is, for example, argon gas or helium gas.

In one embodiment, in the etching gas used in the etching process, the flow rate of chlorine gas may be 15 sccm to 500 sccm, the flow rate of nitrogen gas may be 5 sccm to 20 sccm, and the flow rate of boron trichloride may be 0 sccm to 100 The flow rate of trifluoromethane can be 0 sccm to 20 sccm, the flow rate of methane can be 0 sccm to 15 sccm, and the flow rate of inert gas (eg, argon or helium) can be 0 sccm to 200 sccm. In another embodiment, in the etching gas used in the etching process, the flow rate of chlorine gas may be 30 sccm to 100 sccm, the flow rate of nitrogen gas may be 10 sccm to 20 sccm, and the flow rate of boron trichloride may be 0 sccm to 5 sccm, the flow rate of trifluoromethane can be 0 sccm to 3 sccm, the flow rate of methane can be 0 sccm to 3 sccm, and the flow rate of inert gas can be 50 sccm to 200 sccm.

In addition, in an embodiment, during the etching process, the process pressure may be 2 mTorr to 30 mTorr, the RF power supply may be 30 W to 1500 W, and the RF bias power may be 15 W to 850 W. In another embodiment, during the etching process, the process pressure may be 2 mTorr to 8 mTorr, the RF power supply may be 300 W to 1000 W, and the RF bias power may be 100 W to 250 W.

Based on the above, in the manufacturing method of the interconnection structure of the above embodiment, since the exposed portion EP of the conductive pattern 108 exposed by the conductive pattern 112 has a notch 116, it is possible to cut between two adjacent conductive patterns 112 Bridge path. In this way, the manufacturing method of the interconnection structure of the above embodiment can prevent the defects of the circuit bridge and can effectively increase the overlapping margin of the conductive pattern 112 and the conductive pattern 108.

The interconnection structure of this embodiment will be described below with reference to FIG. 1D. In addition, although the manufacturing method of the interconnect structure of the present embodiment is described as an example of the above manufacturing method, the manufacturing method of the interconnect structure of the present invention is not limited thereto.

Referring to FIG. 1D, the interconnect structure includes a substrate 100, a dielectric layer 102, a conductive pattern 108, and a conductive pattern 112. The dielectric layer 102 is disposed on the substrate 100 and has an opening 104. The conductive pattern 108 is disposed in the opening 104. The conductive pattern 112 is disposed on the conductive pattern 108 and exposes the exposed portion EP of the conductive pattern 108. The exposed portion EP of the conductive pattern 108 has a notch 116. In this embodiment, the exposed portion EP of the conductive pattern 108 may be located on one side of the conductive pattern 112. In addition, the interconnect structure may optionally include at least one of the barrier layer 106, the barrier layer 110, and the barrier layer 114. The barrier layer 106 is disposed between the conductive pattern 108 and the dielectric layer 102, and may be further disposed between the conductive pattern 108 and the substrate 100. The barrier layer 110 is disposed between the conductive pattern 112 and the conductive pattern 108 and between the conductive pattern 112 and the dielectric layer 102. The barrier layer 114 is disposed on the conductive pattern 112. In addition, the materials, arrangement methods, forming methods, and effects of the components in the interconnect structure have been described in detail in the above-described manufacturing methods of FIGS. 1A to 1D, so they will not be repeated here.

Based on the above, in the interconnect structure of the above embodiment, since the exposed portion EP of the conductive pattern 108 exposed by the conductive pattern 112 has the notch 116, the bridge path between two adjacent conductive patterns 112 can be cut off . In this way, the interconnection structure of the above embodiments can prevent the defects of the circuit bridge and can effectively increase the overlapping margin of the conductive pattern 112 and the conductive pattern 108.

2 is a cross-sectional view of an interconnect structure according to another embodiment of the invention.

Please refer to FIG. 1D and FIG. 2 at the same time. The difference between the interconnect structure of FIG. 1D and the interconnect structure of FIG. 2 is as follows. In the interconnect structure of FIG. 2, due to process variations, the width of the conductive pattern 108a is greater than the width of the conductive pattern 108, so that the width of the conductive pattern 112 is smaller than the width of the conductive pattern 108a, and the exposed portion of the conductive pattern 108a EP is located on both sides of the conductive pattern 112. In addition, the exposed portions EP of the conductive pattern 108a may have notches 116 on both sides of the conductive pattern 112, respectively. In addition, the formation method and function of the interconnect structure of FIG. 2 and the interconnect structure of FIG. 1D are similar, and the same components are denoted by the same reference numerals, so they will not be repeated here.

In summary, in the interconnect structure and the manufacturing method of the above embodiment, since the exposed portion of the lower conductive pattern exposed by the upper conductive pattern has a gap, it can be cut between two adjacent upper conductive patterns Bridge path. In this way, the interconnection structure and the manufacturing method thereof in the above embodiments can prevent the defects of the circuit bridge, and can effectively increase the overlapping margin of the upper conductive pattern and the lower conductive pattern.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧Substrate 102‧‧‧ Dielectric layer 104‧‧‧ Opening 106, 110, 114‧‧‧ Barrier layer 108, 112‧‧‧ Conductive pattern 116‧‧‧ Notch EP‧‧‧ Exposed part

1A to 1D are cross-sectional views of the manufacturing process of the interconnect structure according to an embodiment of the invention. 2 is a cross-sectional view of an interconnect structure according to another embodiment of the invention.

100‧‧‧ base

102‧‧‧dielectric layer

104‧‧‧ opening

106, 110, 114 ‧‧‧ barrier layer

108, 112‧‧‧ conductive pattern

116‧‧‧Notch

EP‧‧‧ exposed part

Claims (11)

An interconnect structure includes: a substrate; a dielectric layer disposed on the substrate and having an opening, wherein the entire bottom of the opening exposes the substrate; a first conductive pattern is disposed in the opening; And a second conductive pattern disposed on the first conductive pattern and exposing an exposed portion of the first conductive pattern, wherein the exposed portion of the first conductive pattern has a gap and the bottom of the first conductive pattern Is equal to the width of the first conductive pattern at the height of the bottom of the notch, the width of the second conductive pattern is smaller than the width of the first conductive pattern, and the exposed portion of the first conductive pattern is located in the second conductive pattern On both sides. The interconnect structure as described in item 1 of the patent application range, wherein the material of the first conductive pattern includes W, Ti, TiN, Ta, or TaN. The interconnect structure as described in item 1 of the patent application, wherein the material of the second conductive pattern includes AlCu, Al or W. The interconnect structure as described in item 1 of the patent application scope, wherein the notch exposes part of the side wall of the opening. The interconnect structure as described in item 1 of the patent application, wherein the height of the first conductive pattern located on the side wall of the opening is lower than the height of the first conductive pattern located below the second conductive pattern. A method for manufacturing an interconnecting structure includes: Forming a dielectric layer on a substrate, wherein the dielectric layer has an opening; forming a first conductive pattern in the opening; forming a second conductive pattern on the first conductive pattern, wherein the second conductive pattern An exposed portion of the first conductive pattern is exposed, the width of the second conductive pattern is smaller than the width of the first conductive pattern, and the exposed portion of the first conductive pattern is located on both sides of the second conductive pattern; and A notch is formed in the exposed portion of the first conductive pattern and the width of the bottom of the first conductive pattern is equal to the width of the first conductive pattern at the height position of the bottom of the notch. The method for manufacturing an interconnect structure as described in item 6 of the patent application scope, wherein the method for forming the notch includes: using the second conductive pattern as a mask, and performing an etching process on the exposed portion of the first conductive pattern To partially remove the exposed portion of the first conductive pattern. The method for manufacturing an interconnect structure as described in item 7 of the patent application scope, wherein an etching gas used in the etching process includes a chlorine gas and a protective gas, and the total amount of the chlorine gas and the protective gas is calculated based on The content of chlorine gas is 50% to 96% by volume. The method for manufacturing an interconnect structure as described in item 8 of the patent application range, wherein the protective gas includes nitrogen, boron trichloride, trifluoromethane, methane, or a combination thereof. The method for manufacturing an interconnect structure as described in item 8 of the patent application scope, wherein the etching gas further includes an inert gas. An internal connection structure, including: A substrate; a dielectric layer disposed on the substrate and having an opening, wherein the entire bottom of the opening exposes the substrate; a first conductive pattern disposed in the opening; and a second conductive pattern disposed On the first conductive pattern, and an exposed portion of the first conductive pattern is exposed, wherein the exposed portion of the first conductive pattern has a gap, and the width of the second conductive pattern is smaller than the width of the first conductive pattern And the width of the bottom of the second conductive pattern is equal to the width of the top of the second conductive pattern, and the exposed portion of the first conductive pattern is located on both sides of the second conductive pattern.

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