CN101587859B - Method for forming semiconductor interconnected structure - Google Patents
Method for forming semiconductor interconnected structure Download PDFInfo
- Publication number
- CN101587859B CN101587859B CN200810112509XA CN200810112509A CN101587859B CN 101587859 B CN101587859 B CN 101587859B CN 200810112509X A CN200810112509X A CN 200810112509XA CN 200810112509 A CN200810112509 A CN 200810112509A CN 101587859 B CN101587859 B CN 101587859B
- Authority
- CN
- China
- Prior art keywords
- etching
- inner metal
- metal layer
- layer
- seconds
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides a method for forming a semiconductor interconnected structure, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with an inner metal layer which is provided with a dielectric layer; etching a through hole on the dielectric layer until the inner metal layer is exposed in the atmosphere of oxidation; processing the inner metal layer by a reduction plasma; and filling a conducting material in the through hole. By performing the in-situ reduction of the oxidized inner metal layer in the semiconductor metal interconnected structure, the method prevents the acid atmosphere of the subsequent process procedures from corroding the inner metal layer, improves the reliability of the manufactured semiconductor devices, reduces the time delay and improves the clock frequency.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to the method that forms semiconductor interconnected structure.
Background technology
The metal interconnection structure is a kind of common structure that semiconductor device comprises.This structure as shown in Figure 1, Semiconductor substrate 101 surface coverage have dielectric layer 102, dielectric layer 102 surfaces form the inner metal layer 103 with graphics shape, be coated with interlevel dielectric layer 104 on dielectric layer 102 and the inner metal layer 103, offer the groove that is used to hold outer metal level 105 on the interlevel dielectric layer 104.
Traditional semiconductor technology is mainly to adopt aluminium as the metal interconnection material, is restricted on signal lag.And process for copper is incorporated the integrated level that integrated circuit fabrication process can improve chip, and improve device density, improve clock frequency and reduce the energy that consumes.Reaching such requirement just need be to making corresponding adjustment on the technology.In new technological level, especially on 90 nanometers or following technology node, main signal lag is from the part of interconnection circuit.The smaller metal material of resistivity is as interconnecting material and to select the smaller dielectric material of dielectric constant for use be two main directions that reduce signal lag, improve clock frequency.Discover that because resistivity is little, electromigration failures is low, and process for copper adopted Damascus (Damascene) technology, reduced the number of plies of metal interconnection, thereby reduced cost, so copper is satisfactory preferable selection.
It is the Chinese invention patent of ZL02160505.X that the applicant of this patent had once obtained the patent No..This patent disclosure the method for making of copper damascene structure in a kind of porous dielectric, comprise step: on the surface of Semiconductor substrate, form the ground floor dielectric substance; Make interior metal wire in the ground floor dielectric substance, interior metal wire is surrounded by the ground floor dielectric substance; Optionally remove and be trapped among interior metal wire dielectric substance on every side, form the groove in the dielectric substance, make metal wire exposure in the part; Metal connects material outside forming on the interior metal wire that exposes in groove.
In the said method, form this step of groove in the dielectric substance, often use the method for plasma etching to come the etching dielectric substance, to obtain groove shape preferably.And owing to comprised oxygen in the employed etching gas of plasma etching dielectric substance, formed the oxidation atmosphere, when interior metal wire is exposed in this oxidation atmosphere, metal wire can partly form metal oxide, this can cause electron transfer, and reliability reduces and finally time-delay increase, the clock frequency of the semiconductor device of formation reduce.And when subsequent technique was acid condition, metal oxide was corroded than metal is easier.
Summary of the invention
At the deficiencies in the prior art, technical problem to be solved by this invention provides a kind of method of making the semiconductor interconnected structure of high reliability, low delay and high clock frequency.
For solving the problems of the technologies described above, the invention provides a kind of method that forms semiconductor interconnected structure, comprise step: Semiconductor substrate is provided, has inner metal layer on the described Semiconductor substrate, have dielectric layer on the inner metal layer; Under the oxidation atmosphere, on dielectric layer, etch through hole until exposing inner metal layer; With the described inner metal layer of reproducibility plasma treatment; Filled conductive material in through hole.
Alternatively, described reproducibility plasma is the plasma that contains hydrogen.
Alternatively, the described process conditions that contain the described inner metal layer of plasma treatment of the hydrogen flow 180sccm to 220sccm that is hydrogen; Pressure is 15mTorr to 25mTorr; Power is 600W to 1000W; Time is 15 seconds to 25 seconds.
Alternatively, described in etching through hole under the oxidation atmosphere on the dielectric layer after exposing the inner metal layer step, also comprise the step of repairing described through hole.
Alternatively, describedly be trimmed to employing with the mist of oxygen and the argon gas plasma etching as etching gas, wherein the flow of oxygen is 25sccm to 35sccm, and the flow of argon gas is 270sccm to 330sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; Etch period is 5 seconds to 15 seconds.
Alternatively, the material of described inner metal layer comprises the metal of copper or cupric.
Alternatively, etching is for adopting with the mist of carbon tetrafluoride, argon gas and the oxygen plasma etching as etching gas under the described oxidation atmosphere, wherein the flow of carbon tetrafluoride is 40sccm to 60sccm, the flow of argon gas is 135sccm to 165sccm, and the flow of oxygen is 20sccm to 30sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; The time of etching is 35 seconds to 45 seconds.
In the technique scheme, increased step with the described inner metal layer of reproducibility plasma treatment, make before in etching through hole under the oxidation atmosphere on the dielectric layer in the step that exposes inner metal layer, etching agent and inner metal layer with oxidizability react the metal oxide of generation by in-situ reducing, thereby improved semiconductor device reliability, reduced time-delay and increased clock frequency, and prevented when subsequent technique be when under acid condition, carrying out, the problem that the metal oxide on the inner metal layer is easy to be corroded.
In addition, the processing using plasma that among embodiment inner metal layer is reduced is handled, and can finish in-situ reducing reparation to inner metal layer in same plasma-reaction-chamber with aforementioned plasma etching industrial, can simplified reduction technology.
In addition, increased the step of repairing described through hole among another embodiment, avoided residual material in the through hole on the dielectric to influence the reliability of semiconductor device and increase the time-delay of semiconductor device.
Description of drawings
Fig. 1 is the schematic diagram of the semiconductor alloy interconnect architecture of prior art manufacturing;
Fig. 2 forms the method flow diagram of semiconductor interconnected structure for one embodiment of the invention;
Fig. 3 is step 1 provided among Fig. 2 Semiconductor substrate structural representation;
Fig. 4 is that Semiconductor substrate shown in Figure 3 adopts dry etching structural representation before;
Fig. 5 is for etching the structural representation behind the dielectric layer connecting hole on Fig. 4 medium layer;
Fig. 6 is the schematic diagram that mask layer adopts sandwich construction among Fig. 5.
Embodiment
Present embodiment is by reducing to inner metal layer oxidized in the semiconductor alloy interconnect architecture, prevent acid atmosphere in the subsequent process steps to the corrosion of inner metal layer, so improve the semiconductor device that produces reliability, reduce time-delay and increase clock frequency.
For this reason, present embodiment provides a kind of method that forms semiconductor interconnected structure, comprises step: Semiconductor substrate is provided, has inner metal layer on the described Semiconductor substrate, have dielectric layer on the inner metal layer; Under the oxidation atmosphere, on dielectric layer, etch through hole until exposing inner metal layer; With the described inner metal layer of reproducibility plasma treatment; Filled conductive material in through hole.Alternatively, described reproducibility plasma is the plasma that contains hydrogen.Alternatively, the described process conditions that contain the described inner metal layer of plasma treatment of the hydrogen flow 180sccm to 220sccm that is hydrogen; Pressure is 15mTorr to 25mTorr; Power is 600W to 1000W; Time is 15 seconds to 25 seconds.Alternatively, described in etching through hole under the oxidation atmosphere on the dielectric layer after exposing the inner metal layer step, also comprise the step of repairing described through hole.Alternatively, describedly be trimmed to employing with the mist of oxygen and the argon gas plasma etching as etching gas, wherein the flow of oxygen is 25sccm to 35sccm, and the flow of argon gas is 270sccm to 330sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; Etch period is 5 seconds to 15 seconds.Alternatively, the material of described inner metal layer comprises the metal of copper or cupric.Alternatively, etching is for adopting with the mist of carbon tetrafluoride, argon gas and the oxygen plasma etching as etching gas under the described oxidation atmosphere, wherein the flow of carbon tetrafluoride is 40sccm to 60sccm, the flow of argon gas is 135sccm to 165sccm, and the flow of oxygen is 20sccm to 30sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; The time of etching is 35 seconds to 45 seconds.
Be specifically described below in conjunction with accompanying drawing.
As shown in Figure 2, the method for the formation semiconductor interconnected structure of present embodiment comprises step:
S101 provides Semiconductor substrate, has inner metal layer on the described Semiconductor substrate, has dielectric layer on the inner metal layer;
S102, under the oxidation atmosphere on dielectric layer etching dielectric contact hole until exposing inner metal layer;
S103 is with the described inner metal layer of reproducibility plasma treatment;
S104 fills metal in contact hole.
Describe the concrete steps of said method below with reference to the accompanying drawings in detail.
At first execution in step S101 as shown in Figure 3, provides Semiconductor substrate 201, has inner metal layer 203 on the Semiconductor substrate 201, is used to form the metal interconnection connecting line in the semiconductor device.The thickness of inner metal layer 203 be 375nm to 415nm, for example thickness is 395nm.As what describe in the background technology, because resistivity is little, the reliability height of electron transfer, and process for copper has adopted Damascus (Damascene) technology, reduced the number of plies of metal interconnection, thereby reduced cost, the material of therefore making inner metal layer 203 can comprise the metal of copper or cupric.The method of making inner metal layer 203 can be the method for the manufacturing inner metal layer mentioned in the background technology.
Between inner metal layer 203 and the Semiconductor substrate 201 insulating barrier 202 can also be arranged, be used for forming electricity and isolate with Semiconductor substrate 201.The material of insulating barrier 202 can be the nitrogen-doped carbon thing, thickness be 40nm to 50nm, for example thickness is 45nm.The method that forms insulating barrier 202 on inner metal layer 203 can be that field of semiconductor manufacture forms common chemical vapour deposition (CVD) or the physical vaporous deposition of dielectric layer.
Be coated with etching stop layer 204 on the inner metal layer 203.Etching stop layer 204 can deposit on inner metal layer 203 and form with chemical vapour deposition (CVD) or physical vaporous deposition.The material of etching stop layer 204 can be the nitrogen-doped carbon thing, the carborundum that concrete example such as nitrogen mix.The thickness of etching stop layer 204 is 40nm to 50nm.
Follow execution in step S102, etching etching stop layer 204 forms the dielectric contact hole until exposing inner metal layer under the oxidation atmosphere.In the present embodiment, groove 211 and contact hole 212 form the structure of singly inlaying, but the through hole of other forms of exposure inner metal layer also is applicable to the present invention.Described etching can be that dry etching also can be a wet etching.When adopting dry etching, as shown in Figure 4, can also cover dielectric layer 205 on the etching stop layer 204 with groove 211 and contact hole 212 structures, be used to form the mask of dry etching etching stop layer 204.Described dry etching is to be mask with dielectric layer 205, etching stop layer 204 is adopted with the mist of carbon tetrafluoride, argon gas and the oxygen plasma etching as etching gas, wherein the flow of carbon tetrafluoride is 40 to 60sccm, concrete example such as 40sccm, 45sccm, 50sccm, 55sccm, 60sccm; The flow of argon gas is 135 to 165sccm, concrete example such as 135sccm, 140sccm, 145sccm, 150sccm, 155sccm, 160sccm, 165sccm; The flow of oxygen is 20 to 30sccm, concrete example such as 20sccm, 22sccm, 25sccm, 27sccm, 30sccm.The pressure of etching is 25 to 35mTorr, concrete example such as 25mTorr, 27mTorr, 30mTorr, 32mTorr, 35mTorr.Described 1mTorr equals 0.1333Pa.The power that adopts during etching is 100 to 300W, concrete example such as 100W, 150W, 200W, 250W, 300W.The time of etching is 35 to 45 seconds, and concrete example was as 35 seconds, 37 seconds, 40 seconds, 42 seconds, 45 seconds.Form structure as shown in Figure 5 at last.In above-mentioned steps, use oxygen containing plasma etching etching stop layer 204, but other plasmas with oxidizing property still can be used for etching etching stop layer 204.
After step S102, can also comprise the step that the dielectric contact hole on the etching stop layer 204 is repaired, be used to the time-delay of avoiding the interior residual material of dielectric contact hole to influence the reliability of semiconductor device and increasing semiconductor device.Described finishing is to adopt with the mist of oxygen and the argon gas plasma etching as etching gas, and wherein the flow of oxygen is 25 to 35sccm, and for example flow is 30sccm, and the flow of argon gas is 270 to 330sccm, and for example flow is 300sccm.The pressure of etching is 25 to 35mTorr, and for example pressure is 30mTorr.The power that adopts during etching is between 100 to 300W, and for example power is 200W.The time of etching is 5 to 15 seconds, and for example etch period is 10 seconds.Through after the pre-shaping step, the dielectric contact hole on the etching stop layer 204 forms form preferably, helps improving the performance of the semiconductor device of making.
Step S102 and follow-uply optionally the dielectric contact hole on the etching stop layer 204 is carried out in the pre-shaping step, inner metal layer 203 can with the plasma reaction of employed oxygen in the above-mentioned steps, generate metal oxide.The existence of metal oxide can reduce semiconductor device reliability, increase time-delay and reduce clock frequency, and when subsequent technique be when under acid condition, carrying out, metal oxide is easy to be corroded, and then causes semiconductor device defective to occur.Thereby need reduce processing to the inner metal layer after the oxidation, to overcome the aforementioned problem that causes performance of semiconductor device to reduce or occur defective.
Described reduction can be the position that does not change Semiconductor substrate, carries out in-situ reducing in the plasma etching chamber.
In the present embodiment inner metal layer 203 being reduced the step of handling is execution in step S103, with the described inner metal layer 203 of reproducibility plasma treatment.The reproducibility plasma can be that hydrogen etc. has the gas of reproducibility or have a mist of reproducibility resulting through plasma.Described processing is a plasma treatment, with hydrogen is example, described processing is to adopt the plasma treatment of hydrogen as plasma source, and the flow of hydrogen is 180 to 220sccm, concrete example such as 180sccm, 190sccm, 200sccm, 210sccm, 220sccm.The pressure of handling is 15 to 25mTorr, concrete example such as 15mTorr, 17mTorr, 20mTorr, 22mTorr, 25mTorr.The power that adopts during processing is 600 to 1000W, concrete example such as 600W, 700W, 800W, 900W, 1000W.The time of handling is 15 to 25 seconds, and concrete example was as 15 seconds, 17 seconds, 20 seconds, 22 seconds, 25 seconds.
After step S103, metal oxide on the inner metal layer 203 is reduced, overcome of the oxidation of the plasma of oxygen in step S102 and the follow-up step of optionally the dielectric contact hole on the etching stop layer 204 being repaired, and then overcome the problem that causes performance of semiconductor device to reduce or occur defective inner metal layer 203.
In the present embodiment, the dielectric layer 205 that is covered on the etching stop layer 204 can be single coating, also can be the multilayered coating structure.As shown in Figure 6, when dielectric layer 205 is the multilayered coating structure, from from the nearest one deck of etching stop layer 204, can be black diamond layer 2051 (BlackDiamond), high-temperature oxide layer 2052, bottom anti-reflection layer 2053 and low temperature oxide layer 2054 successively.Wherein, black diamond layer 2051 is a kind of low k organic silicate glass insulating barriers, and thickness is 390nm to 400nm, concrete example such as 395nm.Black diamond layer 2051 can be deposited on the etching stop layer 204 by the method for chemical vapour deposition (CVD).High-temperature oxide layer 2052 is a kind of high-k dielectric layers, and its material can be a compact silicon dioxide, and thickness is 100nm to 140nm, and concrete example such as 120nm can be deposited on by the method for chemical vapour deposition (CVD) on the black diamond layer 2051.The effect of high-temperature oxide layer 2052 is to the infringement of black diamond layer 2051 when preventing plasma etching.Can also form bottom anti-reflection layer 2053 by the method for spin coating on high-temperature oxide layer 2052, its material can be a silicon nitride, and thickness is 300nm to 400nm, concrete example such as 360nm.Can also form low temperature oxide layer 2054 by the method for chemical vapour deposition (CVD) or physical vapour deposition (PVD) on the bottom anti-reflection layer 2053.Low temperature oxide layer 2054 is a kind of low K dielectrics layers, and thickness is 100nm to 140nm, concrete example such as 120nm.
As shown in Figure 6, the groove 211 on the dielectric layer 205 is positioned at black diamond layer 2051 with the boundary of contact hole 212, and the degree of depth of groove 211 in black diamond layer 2051 accounts for 60% to 70% of black diamond layer 2051 thickness, and concrete example is as 65%.
The concrete steps of above-mentioned formation groove 211 and contact hole 212 are:
On low temperature oxide layer 2054, form first photoresist layer with spin-coating method,, on first photoresist layer, form contact hole pattern through exposure imaging technology;
As mask, etching low temperature oxide layer 2054, bottom anti-reflection layer 2053, high-temperature oxide layer 2052 and black diamond layer 2051 until exposing etching stop layer 204, and are removed first photoresist layer with ashing method with first photoresist layer;
Deposition of sacrificial layer on low temperature oxide layer 2054, and sacrifice layer filled up contact hole, and make sacrificial layer surface flatten smooth after, on sacrifice layer, forms second photoresist layer with spin-coating method, pass through exposure imaging technology, on second photoresist layer, form channel patterns;
With second photoresist layer as etching mask, along channel patterns etching low temperature oxide layer 2054, bottom anti-reflection layer 2053, high-temperature oxide layer 2052 and black diamond layer 2051, account for 65% of black diamond layer 2051 thickness until the etching depth in black diamond layer 2051, and remove second photoresist layer 116 and sacrifice layer 114 with organic stripper.
Directly execution in step S102 and step S103 after the above-mentioned steps, in order to oxidized inner metal layer 203 is reduced, prevent acid atmosphere in the subsequent process steps to the corrosion of inner metal layer 203, and improve the semiconductor device that produces reliability, reduce time-delay and increase clock frequency.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (5)
1. a method that forms semiconductor interconnected structure is characterized in that, comprises step:
Semiconductor substrate is provided, has inner metal layer on the described Semiconductor substrate, have dielectric layer on the inner metal layer;
Under the oxidation atmosphere, on dielectric layer, etch through hole until exposing inner metal layer;
With the described inner metal layer of reproducibility plasma treatment that contains hydrogen, and the described process conditions that contain the described inner metal layer of plasma treatment of the hydrogen flow 180sccm to 220sccm that is hydrogen; Pressure is 15mTorr to 25mTorr; Power is 600W to 1000W; Time is 15 seconds to 25 seconds;
In through hole, fill metal material.
2. the method for formation semiconductor interconnected structure as claimed in claim 1 is characterized in that: described in etching through hole under the oxidation atmosphere on the dielectric layer after exposing the inner metal layer step, also comprise the step of repairing described through hole.
3. the method for formation semiconductor interconnected structure as claimed in claim 2, it is characterized in that: describedly be trimmed to employing with the mist of oxygen and argon gas plasma etching as etching gas, wherein the flow of oxygen is 25sccm to 35sccm, and the flow of argon gas is 270sccm to 330sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; Etch period is 5 seconds to 15 seconds.
4. the method for formation semiconductor interconnected structure as claimed in claim 1 is characterized in that: the material of described inner metal layer comprises the metal of copper or cupric.
5. the method for formation semiconductor interconnected structure as claimed in claim 1, it is characterized in that: etching is for adopting with the mist of carbon tetrafluoride, argon gas and the oxygen plasma etching as etching gas under the described oxidation atmosphere, wherein the flow of carbon tetrafluoride is 40sccm to 60sccm, the flow of argon gas is 135sccm to 165sccm, and the flow of oxygen is 20sccm to 30sccm; The pressure of etching is 25mTorr to 35mTorr; Etching power is 100W to 300W; The time of etching is 35 seconds to 45 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810112509XA CN101587859B (en) | 2008-05-23 | 2008-05-23 | Method for forming semiconductor interconnected structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810112509XA CN101587859B (en) | 2008-05-23 | 2008-05-23 | Method for forming semiconductor interconnected structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101587859A CN101587859A (en) | 2009-11-25 |
| CN101587859B true CN101587859B (en) | 2011-03-23 |
Family
ID=41372022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810112509XA Active CN101587859B (en) | 2008-05-23 | 2008-05-23 | Method for forming semiconductor interconnected structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101587859B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9318026B2 (en) | 2008-08-21 | 2016-04-19 | Lincoln Global, Inc. | Systems and methods providing an enhanced user experience in a real-time simulated virtual reality welding environment |
| US9280913B2 (en) | 2009-07-10 | 2016-03-08 | Lincoln Global, Inc. | Systems and methods providing enhanced education and training in a virtual reality environment |
| CN105336565A (en) * | 2014-06-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Immersed type method for cleaning watermark after explosion |
| CN105336585B (en) * | 2014-06-13 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Etching method and forming method of interconnection structure |
| CN105448749B (en) * | 2014-08-20 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of lead wire welding mat structure |
| CN108183108A (en) * | 2017-12-28 | 2018-06-19 | 信利（惠州）智能显示有限公司 | The production method and array substrate and display device of a kind of array substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875465A (en) * | 2003-10-27 | 2006-12-06 | 住友电气工业株式会社 | Gallium nitride semiconductor substrate and process for producing the same |
-
2008
- 2008-05-23 CN CN200810112509XA patent/CN101587859B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875465A (en) * | 2003-10-27 | 2006-12-06 | 住友电气工业株式会社 | Gallium nitride semiconductor substrate and process for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101587859A (en) | 2009-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101587859B (en) | Method for forming semiconductor interconnected structure | |
| CN101355047B (en) | Method for forming through hole in low dielectric coefficient medium layer | |
| TW201011861A (en) | Method for fabricating integrated circuit | |
| CN100561729C (en) | Double mosaic structure manufacture method | |
| CN101192533A (en) | Etch stop layer and its forming method | |
| KR100790452B1 (en) | Method for forming multi layer metal wiring of semiconductor device using damascene process | |
| CN101364565A (en) | Method for manufacturing semiconductor device | |
| CN100561706C (en) | The formation method of dual-damascene structure | |
| CN105977149A (en) | Passivation layer etching method, manufacture method of pad and manufacture method of semiconductor device | |
| CN101055421A (en) | Method for forming double inserted structure | |
| TW200302550A (en) | Method for forming multi-layer metal line of semiconductor device | |
| JP5930416B2 (en) | Wiring structure, semiconductor device provided with wiring structure, and method of manufacturing the semiconductor device | |
| CN101625992A (en) | Method for manufacturing dual-damascene structure | |
| JP2009004633A (en) | Multilayer interconnection structure and method of manufacturing the same | |
| US11688604B2 (en) | Method for using ultra thin ruthenium metal hard mask for etching profile control | |
| CN103165515B (en) | Manufacture method of semiconductor device | |
| CN101740474B (en) | Method for manufacturing semiconductor device and dual-damascene structure | |
| JP2008010824A (en) | Method for manufacturing semiconductor memory element | |
| CN1243378C (en) | Process for preparing metallic interconnection wire | |
| KR100791688B1 (en) | Method for forming dual damascene pattern in semiconductor manufacturing process | |
| KR100453956B1 (en) | Method for manufacturing metal line of semiconductor device | |
| CN101625993B (en) | Dual-damascene structure and manufacturing method thereof | |
| KR101181271B1 (en) | Method for Forming Metal Line of Semiconductor Device | |
| CN101996933B (en) | Method for manufacturing top copper interconnection layer | |
| TWI233661B (en) | Method for forming multi-layer metal line of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |