CN118073307A - Semiconductor structure, semiconductor device, electronic apparatus, and wafer bonding method - Google Patents
Semiconductor structure, semiconductor device, electronic apparatus, and wafer bonding method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- Manufacturing & Machinery (AREA)
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- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
The embodiment of the application provides a semiconductor structure, a semiconductor device, electronic equipment and a wafer bonding method, wherein the wafer bonding method comprises the following steps: providing two wafers to be bonded, wherein each wafer comprises a substrate, and a device functional layer is arranged on a first side of at least one of the two substrates; forming metal bonding layers on the two wafers respectively, wherein the metal bonding layers are arranged on the first side of the substrate; forming an original auxiliary bonding layer covering the metal bonding layer on at least one of the two wafers with the metal bonding layer to obtain two processed wafers; wherein the original auxiliary bonding layer is an insulating compound; and attaching the two wafers after treatment so that the metal bonding layers on the two wafers are arranged oppositely, and performing heat treatment so that the original auxiliary bonding layers clamped between the corresponding metal bonding layers in the two wafers are reduced to conductive layers. The wafer bonding method has simple process and strong universality, and can conveniently realize high-strength bonding between two wafers with any metal bonding layers.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure, a semiconductor device, electronic equipment and a wafer bonding method.
Background
Wafer bonding technology is a key technology in the semiconductor manufacturing process, and can bond two wafers with different functions together, and based on the stacking thought, a semiconductor device with higher integration level, more functions and smaller size can be obtained. The types of conventional wafer bonding technologies generally include metal-metal direct bonding technologies (such as Cu-Cu bonding, au-Sn bonding, etc.), silicon-silicon direct bonding technologies, etc., which have high requirements on the types of bonding materials, the flatness of bonding surfaces, etc., otherwise, poor bonding quality and even bonding failure are easily caused, which limits the application of the wafer bonding technology in heterogeneous integration. Therefore, it is necessary to provide a wafer bonding method that is highly versatile, has low bonding difficulty, and has high bonding strength.
Disclosure of Invention
In view of the above, an embodiment of the present application provides a wafer bonding method, which can achieve convenient and high-strength bonding between two wafers having any metal bonding layer, and also provides a semiconductor structure and a semiconductor device based on the method.
Specifically, a first aspect of an embodiment of the present application provides a semiconductor structure, including:
The semiconductor device comprises a first substrate and a plurality of first metal bonding layers, wherein the plurality of first metal bonding layers are arranged on one side of the first substrate at intervals, and a first insulating bonding layer is arranged between two adjacent first metal bonding layers;
The first device functional layer and the plurality of second metal bonding layers are arranged on one side, facing the first substrate, of the first device functional layer, the plurality of first metal bonding layers are arranged in a one-to-one opposite mode, and a second insulating bonding layer is arranged between two adjacent second metal bonding layers; a conductive layer is further arranged between each first metal bonding layer and the second metal bonding layer opposite to the first metal bonding layer, an auxiliary bonding layer is arranged between the adjacent conductive layers, and the auxiliary bonding layers are made of insulating compounds; the conductive layer contains the same element as the normal valence element in the auxiliary bonding layer, and the reducibility of the material of the first metal bonding layer and/or the second metal bonding layer close to the conductive layer is higher than that of the material of the conductive layer.
In the semiconductor structure provided by the embodiment of the application, the conductive layer is obtained by reducing the same material as the auxiliary bonding layer through the first metal bonding layer and/or the second metal bonding layer. The conductive layers and the insulating bonding layers separating the conductive layers can establish bonding bridges between structures on the upper side and the lower side of the conductive layers, high-strength bonding between the upper metal bonding layer and the lower metal bonding layer and between the upper insulating bonding layer and the lower insulating bonding layer is realized, the overall structural stability of the semiconductor structure is ensured, the longitudinal conductive connection between the first metal bonding layer and the second metal bonding layer which are correspondingly arranged is not influenced, and the transverse electric insulation between the adjacent first metal bonding layers/between the adjacent second metal bonding layers in the thickness direction vertical to the first substrate is ensured.
In the embodiment of the application, the surface of the conductive layer, which is contacted with the first metal bonding layer or the second metal bonding layer, is flat and has no damage. The conductive layer with the characteristics can better play a role of firmly and electrically connecting the first metal bonding layer and the second metal bonding layer, and high structural stability of the semiconductor structure is ensured.
In an embodiment of the present application, the first metal bonding layer and/or an interface of the first metal bonding layer near the conductive layer contains the same element as the negative valence element in the auxiliary bonding layer. This may reflect to some extent that the conductive layer is reduced by the first metal bonding layer and/or the second metal bonding layer from the same material as the auxiliary bonding layer, covalent bonding may exist between the interface of the conductive layer and the upper and lower metal bonding layers, and the bonding strength is higher.
In an embodiment of the present application, the auxiliary bonding layer includes one or more of a metal oxide, a metal nitride, a silicon oxide containing a doping element, a silicon nitride containing a doping element, and a silicon oxynitride containing a doping element; the material of the conductive layer comprises a simple substance of silicon containing doping elements or a simple substance corresponding to the metal elements in the metal oxide or the metal nitride. The auxiliary bonding layer materials have good hydrophilicity and insulativity, stable bonding between the upper auxiliary bonding layer and the lower auxiliary bonding layer in the semiconductor structure can be ensured by the auxiliary bonding layer materials, and the conductivity of a reduction product-conductive layer of the material which is the same as the auxiliary bonding layer materials is good, so that good electric connection between the corresponding layers of the semiconductor structure is realized.
In an embodiment of the present application, the metal element in the metal oxide and the metal nitride includes one or more of aluminum, tantalum, hafnium, and zirconium. At this time, the conductive layer containing these elements has good conductivity, the auxiliary bonding layer is easier to prepare, and can be reduced by the usual metal bonding layer at a lower temperature.
In the embodiment of the application, the auxiliary bonding layer is one layer or two layers; the number of layers of the conductive layer is the same as that of the auxiliary bonding layer.
In some embodiments of the present application, the conductive layer and the auxiliary bonding layer are each one layer, and the thicknesses of the conductive layer and the auxiliary bonding layer are each in the range of 0.5nm to 10 nm. The thinner conductive layer and the auxiliary bonding layer can still ensure the stable joint between the first metal bonding layer and the second metal bonding layer and the stable joint between the first auxiliary bonding layer and the second auxiliary bonding layer under the thinner condition.
In still other embodiments of the present application, the auxiliary bonding layer comprises a first auxiliary bonding layer and a second auxiliary bonding layer disposed in a stacked arrangement, and the first auxiliary bonding layer is adjacent to the first insulating bonding layer; the conductive layer comprises a first conductive layer and a second conductive layer which are stacked, and the first conductive layer is close to the first metal bonding layer; the first conductive layer is obtained by reducing the first metal bonding layer, and the second conductive layer is obtained by reducing the second metal bonding layer, wherein the material of the first conductive layer is the same as that of the first auxiliary bonding layer. The auxiliary bonding layers of the two-layer structure can better ensure that bonding interfaces of different areas are similar materials when the semiconductor structure is prepared, can better realize high-strength covalent bonding, ensures higher proceeding degree of reduction reaction, ensures that the surface state of each conductive layer is good, has no gap with adjacent metal bonding layers and the like, and ensures higher structural stability of the semiconductor structure.
In the embodiment of the application, the surface of the first insulating bonding layer, which faces away from the first substrate, is flush with the surface of the first metal bonding layer, which faces away from the first substrate; the surface of the second insulating bonding layer facing the first substrate is flush with the surface of the second metal bonding layer facing the first substrate. Thus, the surface of the conducting layer or the auxiliary bonding layer facing away from or towards the first substrate is smooth, and smooth preparation of the semiconductor structure and good stability maintenance are guaranteed.
In some embodiments of the present application, the first device functional layer includes a plurality of first device functional sub-layers disposed at intervals, and one side of each of the second metal bonding layers facing away from the first substrate is provided with one of the second device functional sub-layers.
In some embodiments of the present application, the semiconductor structure further includes: and the second device functional layers are positioned between the first substrate and the first metal bonding layer, and the second device functional layers are arranged in one-to-one correspondence with the second device functional layers. In this way, the semiconductor structure can integrate the device function layers with two different functions, and has higher integration level and more functions.
A second aspect of the embodiment of the present application provides a semiconductor device, including the semiconductor structure according to the first aspect of the embodiment of the present application. The semiconductor device has high structural stability and can stably perform its function.
In an embodiment of the present application, the semiconductor device may include one of an optoelectronic device, a power device, and a radio frequency device.
A third aspect of the embodiment of the present application provides an electronic device, including the semiconductor device according to the second aspect of the embodiment of the present application. The electronic equipment with the semiconductor device can stably operate, and has outstanding market competitiveness.
The embodiment of the application also provides a wafer bonding method, which comprises the following steps:
Providing two wafers to be bonded, wherein each wafer comprises a substrate, and a device functional layer is arranged on a first side of at least one of the two substrates;
forming metal bonding layers on the two wafers respectively, wherein the metal bonding layers are arranged on the first side of the substrate;
Forming an original auxiliary bonding layer covering the metal bonding layer on at least one of the two wafers with the metal bonding layer to obtain two processed wafers; wherein the original auxiliary bonding layer is an insulating compound;
and attaching the two wafers after the treatment so that the metal bonding layers on the two wafers are oppositely arranged, and performing heat treatment on the two wafers after the attachment so that the original auxiliary bonding layers clamped between the metal bonding layers correspondingly arranged in the two wafers are reduced to be conductive layers.
According to the wafer bonding method, the original auxiliary bonding layer is introduced on the metal bonding layer of at least one of the two wafers, the original auxiliary bonding layer can be used for realizing the primary stable bonding of the two wafers after bonding, the high-strength covalent bonding between bonding interfaces is realized by means of heat treatment, and the reduction of the metal bonding layer of the two wafers to the auxiliary bonding layer clamped in the middle is realized, so that the conductive connection of the two wafers is realized. The wafer bonding method has simple process and strong universality, and can conveniently realize high-strength bonding between any two wafers with metal bonding layers.
In this embodiment, after the bonding, the reducibility of the material on the side where the metal bonding layer contacts the original auxiliary bonding layer is higher than the reducibility of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer. Thus, the original auxiliary bonding layer in the specific area can be ensured to be successfully restored.
In an embodiment of the present application, the original auxiliary bonding layer includes one of a metal oxide, a metal nitride, a silicon oxide containing a doping element, a silicon nitride containing a doping element, and a silicon oxynitride containing a doping element. The original auxiliary bonding layer materials are easy to prepare, have good hydrophilicity and insulativity, can ensure the close fit of two wafers after being contacted, can be reduced by a common metal bonding layer at a lower temperature, and the reduction products of the original auxiliary bonding layer materials are conductive.
In an embodiment of the present application, the thickness of the original auxiliary bonding layer is in the range of 0.5-10 nm. The original auxiliary bonding layer does not have adverse effect on the roughness of the surface to be bonded of the wafer under the condition of thinness, and is beneficial to reducing the duration of subsequent heat treatment and reducing the damage to the functions of the wafer.
In an embodiment of the present application, the temperature of the heat treatment is 100-200 ℃. The lower heat treatment temperature can ensure that the reduction of the original auxiliary bonding layer can be smoothly carried out, and simultaneously, the damage to the device functional layer on the wafer is reduced, so that the bonded structure can normally play a role.
In some embodiments of the application, the metal bonding layer is spaced apart from the first side of the substrate; and before forming the original auxiliary bonding layer, the wafer bonding method further comprises: an insulating bonding layer is further formed between the adjacent metal bonding layers on the two wafers, and the original auxiliary bonding layer also covers the insulating bonding layer; the surface of the insulating bonding layer, which is away from the substrate, is flush with the surface of the metal bonding layer, which is away from the substrate.
When two wafers with the metal bonding layer and the insulating bonding layer are bonded in a mixed mode, an original auxiliary bonding layer capable of covering the metal bonding layer and the insulating bonding layer is introduced into at least one of the two wafers, so that preliminary low-temperature bonding after bonding of the two wafers can be conveniently realized by means of the original auxiliary bonding layer, high-strength covalent bonding between bonding interfaces is realized by means of heat treatment, and the upper metal bonding layer and the lower metal bonding layer of the two wafers only restore the original auxiliary bonding layer clamped in the middle, so that longitudinal conductive connection between the corresponding metal bonding layers in the two wafers and transverse insulating separation between adjacent metal bonding layers in the same wafer are ensured. In addition, the surface of one side of the insulating bonding layer, which is away from the substrate, is flush with the surface of one side of the metal bonding layer, which is away from the substrate, so that an auxiliary bonding layer with a flat surface can be formed later, and the wafer bonding power can be improved.
Drawings
Fig. 1 is a flow chart of a wafer bonding method according to an embodiment of the present application.
Fig. 2 is a schematic diagram illustrating a specific process of a wafer bonding method according to an embodiment of the application.
Fig. 3 is a schematic diagram illustrating a modification of the wafer bonding method shown in fig. 2.
Fig. 4 is a schematic diagram illustrating another modification of the wafer bonding method shown in fig. 2.
Fig. 5 is a schematic diagram illustrating a specific process of a wafer bonding method according to another embodiment of the present application.
Fig. 6 is a schematic diagram illustrating a modification of the wafer bonding method shown in fig. 5.
Fig. 7 is a schematic diagram of another process of bonding and heat treating the two wafers in fig. 5.
Fig. 8 is a schematic diagram of another process of bonding and heat treating the two wafers in fig. 6.
Fig. 9 is a schematic diagram illustrating another modification of the wafer bonding method shown in fig. 5.
Fig. 10 is a schematic diagram illustrating a process of a wafer bonding method according to another embodiment of the present application.
Fig. 11 is a schematic diagram illustrating a modification of the wafer bonding method shown in fig. 10.
Fig. 12 is a schematic diagram illustrating another variation of the wafer bonding method shown in fig. 10.
Fig. 13A to 13H are schematic structural views of a semiconductor structure according to an embodiment of the present application.
The main reference numerals illustrate: 100-semiconductor structure, 1 a-first wafer, 1 b-second wafer, 10 a-first substrate, 10 b-second substrate, 20 a-second device functional layer, 20 b-first device functional layer, 30 a-first metal bonding layer, 30 b-second metal bonding layer, 31 a-first insulating bonding layer, 31 b-first insulating bonding layer, 40 a-first original auxiliary bonding layer, 40 b-second original auxiliary bonding layer, 402 a-first conductive layer, 402 b-second conductive layer, 401 a-first auxiliary bonding layer; 401 b-a second auxiliary bonding layer, 401-an auxiliary bonding layer, 402-a conductive layer.
Detailed Description
The technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
The embodiment of the application provides a wafer bonding method, please refer to the flow chart of fig. 1, the detailed process diagrams of fig. 2-3, the wafer bonding method comprises the following steps S01-S04.
S01, providing two wafers to be bonded, each wafer comprising a substrate, with a device functional layer disposed on a first side of at least one of the two substrates.
The substrate may be a sapphire substrate, a glass substrate, a silicon carbide substrate, a silicon substrate, a germanium substrate, a silicon-on-insulator substrate (SOI substrate), a germanium-on-insulator substrate, or a group III-V compound substrate (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or the like). The crystal orientation of the silicon substrate is not limited, and may be, for example, a silicon substrate with a (111) crystal plane index, or a silicon substrate with other crystal plane indexes; in particular, the silicon substrate in the wafer used to fabricate the optoelectronic device may be a silicon substrate of (111) crystal plane index. Each device functional layer may be a single layer or a plurality of layers (a plurality of layers means two or more layers), and the number of layers or the material of each layer may be selected according to the function of the semiconductor device formed by wafer bonding. In some embodiments, the device functional layer includes an epitaxial stacked structure formed based on a iii-v semiconductor material (e.g., gaN, gaAs, alN, alGaN, inN, etc.), for example, including a buffer layer, an n-doped layer, an active layer, and a p-doped layer in a stacked arrangement, with the buffer layer adjacent to the substrate. The device functional layer comprising the epitaxial stacked structure is particularly suitable for preparing photoelectric devices.
Regarding the two wafers to be bonded, in some embodiments, both wafers may include a substrate and a device functional layer disposed on the substrate, and as shown in fig. 2-3, the two wafers may be referred to as a first wafer 1a and a second wafer 1b, respectively, the first wafer 1a includes a first substrate 10a and a second device functional layer 20a disposed on a first side 101a of the first substrate 10a, and the second wafer 1b includes a second substrate 10b and a first device functional layer 20b disposed on a first side 101b of the second substrate 10 b. In fig. 2-3, in both wafers with device functional layers, each device functional layer is fully covering the entire surface area of the first side of the substrate. In other embodiments, the two wafers to be bonded may also be one wafer including a substrate and the other wafer including a substrate and a device functional layer disposed on the substrate (this will be described below with reference to fig. 4).
And S02, forming metal bonding layers on the two wafers respectively, wherein the metal bonding layers are arranged on the first side of the substrate.
Wherein the metal bonding layer on each substrate can be a single-layer metal or a multi-layer metal stack; each layer of metal can be a metal simple substance, or a metal alloy, or a composite layer formed by the metal alloy and the metal simple substance. In an embodiment of the present application, the metal bonding layer is not elemental copper. Thus, the reduction of the metal bonding layer to the original auxiliary bonding layer below can be ensured more smoothly. Wherein, the material of the metal bonding layer comprises Ti, cr, ni, ta, au, in, sn, ag, al, W and one or more of alloy of at least two elements, tiN and TaN. For example, the metal bonding layer may be a Ti layer, a Ta layer, a Cr layer, a Ni layer, a TiCr alloy layer, niCrTi alloy layer, a stack of Ti layer and Ni layer, or the like. The metal bonding layer may be prepared by electroplating, physical vapor deposition (such as sputtering, electron beam evaporation, thermal evaporation), or the like, but is not limited thereto. In the present application, the thickness of the metal bonding layer may be between several nanometers and several tens of micrometers, such as in the range of 10nm to 10 μm, and specifically may be 20nm, 30nm, 50nm, 60nm, 80nm, 100nm, 150nm, 200nm, 500nm, 800nm, 1 μm, 5 μm, 8 μm, or the like.
As shown in fig. 2-3, after the processing in step S02, the first wafer 1a further includes a first metal bonding layer 30a stacked on a side of the second device functional layer 20a facing away from the first substrate 10a, and the first metal bonding layer 30a is also located on the first side 101a of the first wafer 1a. Similarly, the second wafer 1b further comprises a second metal bonding layer 30b laminated on the side of the first device functional layer 20b facing away from the second substrate 10b, the second metal bonding layer 30b also being located on the first side 101b of the second wafer 1b. More specifically, in fig. 2, the first metal bonding layer 30a entirely covers a side surface of the second device functional layer 20a facing away from the first substrate 10a, and in fig. 3, the second metal bonding layer 30b entirely covers a side surface of the first device functional layer 20b facing away from the second substrate 10 b.
S03, forming an original auxiliary bonding layer covering the metal bonding layer on at least one of the two wafers with the metal bonding layer to obtain two processed wafers; wherein the original auxiliary bonding layer is an insulating compound.
In step S03, the original auxiliary bonding layer may be prepared on both wafers (as shown in fig. 2), or the original auxiliary bonding layer may be prepared on only one of the wafers (as shown in fig. 3). Accordingly, after the two wafers are bonded in step S04 described below, the total number of primary auxiliary bonding layers in the bonded structure may be one or two. In fig. 2, in the first wafer 1a, a first original auxiliary bonding layer 40a is formed on a surface of the first metal bonding layer 30a facing away from the first substrate 10a, and covers the first metal bonding layer 30a, and since the first metal bonding layer 30a covers the first substrate 10a entirely, the first original auxiliary bonding layer 40a also correspondingly covers the first substrate 10a entirely; similarly, in the second wafer 1b, a side of the second metal bonding layer 30b facing away from the second substrate 10b is formed with a second original auxiliary bonding layer 40b. In fig. 3, only the second substrate 10b has the original auxiliary bonding layer 40 formed thereon, which may cover the second metal bonding layer 30 b.
In an embodiment of the present application, the thickness of each of the original auxiliary bonding layers is less than the thickness of the metal bonding layer, for example, the thickness of the original auxiliary bonding layer is 0.1% -10% of the thickness of the metal bonding layer. For example, referring to fig. 2, specifically, the thickness of the first original auxiliary bonding layer 40a is smaller than the thickness of the first metal bonding layer 30a, and the thickness of the second original auxiliary bonding layer 40b is smaller than the thickness of the second metal bonding layer 30 b. In the embodiment of the present application, the thicknesses of the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b may be in the range of 0.5nm to 100nm, respectively; in some embodiments, the thickness may be in the range of 0.5nm-10nm, such as 0.6nm, 0.8nm, 1nm, 1.5nm, 2nm, 3nm, 5nm, 8nm, 9.5nm, 10nm, and the like. The thinner original auxiliary bonding layer does not have adverse effect on the roughness of the bonding surface of the metal bonding layer on the wafer, and is beneficial to reducing the duration of the subsequent heat treatment and reducing the damage to the wafer. In some embodiments, the thickness of the original auxiliary bonding layer may be greater than or equal to one molecular layer and less than 5 molecular layers, and may be specifically 0.5nm to 3nm. Wherein "one molecular layer" refers to the thickness of a monolayer of molecules of the constituent material of the original auxiliary bonding layer.
In an embodiment of the present application, the material of each of the original auxiliary bonding layers independently includes one or more of metal oxide, metal nitride, silicon oxide containing a doping element, silicon nitride containing a doping element, and silicon oxynitride containing a doping element. That is, the materials of the original auxiliary bonding layers may be the same or different. Wherein the metal elements in the metal oxide and the metal nitride comprise one or more of aluminum Al, tantalum Ta, hafnium Hf and zirconium Zr. The doping elements include n-type doping elements (e.g., arsenic As, phosphorus P) and/or P-type doping elements (e.g., boron B). The doping element ensures that the product of the reduction of the silicon oxide, nitride or oxynitride containing the doping element, in particular the elemental silicon containing the doping element, is electrically conductive. The original auxiliary bonding layer can be formed by a low-pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, atomic layer deposition, a physical vapor deposition process, a laser pulse deposition process or the like.
The original auxiliary bonding layer is made of the insulating material and generally has good hydrophilicity, the surface is always provided with hydroxyl suspension bonds, or after the surface is treated by water or aqueous solution or hydrophilic organic solvent or plasma bombardment, the surface can be provided with enough hydrophilic hydroxyl groups, which is beneficial to realizing hydrogen bonding with sufficient bonding strength between two wafers by the original auxiliary bonding layer at low temperature (which can comprise normal temperature, which is the temperature compared with the subsequent heat treatment), and further is beneficial to converting bonding interfaces into covalent bonding with higher strength in the subsequent heat treatment. In addition, the original auxiliary bonding layer material can be formed on various metal bonding layers, the requirements on the type, the surface condition and the like of the metal layers to be bonded are not high, the original auxiliary bonding layer has low requirements on the thickness, a few nm is enough to bond two wafers together initially, the forming of a thinner original auxiliary bonding layer can not adversely affect the roughness of the bonding surface, the duration of heat treatment after the following bonding of the two wafers is short, the temperature is low, and the damage to the wafer structure is reduced.
The material of the original auxiliary bonding layer can be selected based on the metal bonding layer, and the principle that the reducibility of the material at the contact side of the metal bonding layer and the original auxiliary bonding layer in the structure obtained by bonding the two wafers through S04 is higher than that of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer is taken as the principle. That is, the application does not require that the reducibility of the material of the whole metal bonding layer is higher than that of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer, and only the part of the material of the metal bonding layer contacted with the original auxiliary bonding layer is required to be satisfied, so that the application range of the wafer bonding method is widened, and particularly when the metal bonding layer is a multi-layer metal lamination, the original auxiliary bonding layer can be arranged on a wafer with any metal bonding layer, so that the convenient bonding of two wafers is realized.
When the original auxiliary bonding layer is metal oxide or metal nitride, the simple substance corresponding to the normal valence element in the original auxiliary bonding layer refers to the simple substance corresponding to the metal element in the metal oxide or the metal nitride. When the original auxiliary bonding layer is silicon oxide, silicon nitride or silicon oxynitride containing doped elements, the normal valence element is specifically a simple substance corresponding to the silicon element. In some embodiments, the primary auxiliary bonding layer is an oxide or nitride of Al, and in this case, the metal material of the side of the metal bonding layer adjacent to the primary auxiliary bonding layer may include at least one of Ti, cr, and Ni. In other embodiments, the primary auxiliary bonding layer is an oxide or nitride of tantalum Ta, hafnium Hf, zirconium Zr, and the metallic material on the side of the metallic bonding layer adjacent to the primary auxiliary bonding layer includes at least one of Al, ti, cr, ni.
And S04, bonding the two wafers processed in the step S03 to enable the metal bonding layers on the two wafers to be arranged oppositely, and performing heat treatment on the two bonded wafers to enable the original auxiliary bonding layers clamped between the metal bonding layers arranged correspondingly on the two wafers to be reduced into conductive layers.
Bonding refers to the contact of the surfaces of two wafers to be bonded. For fig. 2, in which the original auxiliary bonding layers are on both wafers, the bonding means that the first original auxiliary bonding layer 40a is in contact with the second original auxiliary bonding layer 40 b; for fig. 3, where only one of the wafers has an original auxiliary bonding layer, the attachment means that the original auxiliary bonding layer 40 on the second wafer 1b is in contact with the first metal bonding layer 30a on the first wafer 1a. After bonding, the upper and lower metal bonding layers on the two wafers are oppositely arranged and aligned. It should be noted that the "alignment" herein is not limited to "perfect alignment" (perfect alignment refers to that the sidewalls of the upper and lower metal bonding layers disposed in any opposite direction are flush along the thickness direction of the substrate), and may be allowed to have a certain offset, and the present application will be described below in terms of offset alignment. When there are several metal bonding layers on two wafers, the "alignment" specifically means that any one metal bonding layer on one wafer corresponds to one metal bonding layer on another wafer one by one, and the orthographic projections of each pair of the upper and lower metal bonding layers disposed oppositely on the original auxiliary bonding layer have a certain overlapping area.
In some embodiments of the present application, before the bonding of the two wafers after the processing, the method further includes: and carrying out hydrophilic treatment on the surfaces to be bonded of the two wafers. The surface to be bonded of the wafers is subjected to hydrophilic treatment, so that a certain number of hydrogen bonds can be formed between the bonded surfaces of the two wafers after the two wafers are bonded, the strength of the bonded two wafers is improved, and the reduction reaction during subsequent heat treatment is facilitated. As described in the foregoing description of the present application, after the original auxiliary bonding layer is subjected to hydrophilic treatment, the number of hydroxyl suspensions on the surface of the auxiliary bonding layer can be increased; the hydrophilic treatment of the metal bonding layer is also beneficial to forming a certain hydrophilic group (such as-OH) on the surface of the metal bonding layer so as to ensure the close fit between the metal bonding layer and the original auxiliary bonding layer. The hydrophilic treatment may include plasma bombardment (such as oxygen plasma bombardment), or chemical mechanical Polishing (CHEMICAL MECHANICAL Polishing, CMP), or spraying, soaking, immersing, etc. with water or hydrophilic agent, or a combination of the foregoing. The hydrophilic agent may be an aqueous solution such as an ammonia solution or a weak acid, or a hydrophilic organic solvent containing a hydroxyl group. In the case of hydrophilic treatment with water, spraying or immersing with deionized water, immersing with water vapor, or the like may be specifically included.
In the application, the two bonded wafers are subjected to heat treatment, the bonding interface of the two wafers can be gradually changed from hydrogen bonding to covalent bonding, and meanwhile, the original auxiliary bonding layer clamped between the two oppositely arranged metal bonding layers is reduced to be a conductive layer, in particular to be reduced by the metal bonding layer contacted with the original auxiliary bonding layer, and the two wafers are electrically connected by virtue of the metal bonding layer and the conductive layer between the metal bonding layers. It can be understood that in the structure obtained after the bonding of the two wafers, the reducibility of the material on the side, which is in contact with the original auxiliary bonding layer, of the metal bonding layer is higher than that of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer. If the original auxiliary bonding layer is formed on only one wafer, the metal bonding layer on at least one of the two wafers may meet the requirement of reducibility after bonding.
In fig. 2, the reducibility of the material of the first metal bonding layer 30a near the first original auxiliary bonding layer 40a is higher than the reducibility of the simple substance corresponding to the normal valence element in the first original auxiliary bonding layer 40a, and the reducibility of the material of the second metal bonding layer 30b near the second original auxiliary bonding layer 40b is higher than the reducibility of the simple substance corresponding to the normal valence element in the second original auxiliary bonding layer 40b, so that the first original auxiliary bonding layer 40a is reduced to the first conductive layer 402a by the first metal bonding layer 30a and the second original auxiliary bonding layer 40b is reduced to the second conductive layer 402b by the second metal bonding layer 30 b. In fig. 3, the material of the first metal bonding layer 30a and/or the second metal bonding layer 30b near the side of the original auxiliary bonding layer 40 should have a higher reducibility than the simple substance corresponding to the normal valence element in the original auxiliary bonding layer 40. This also ensures that after the two wafers of fig. 3 are bonded, the original auxiliary bonding layer 40 can be reduced by the metal bonding layer on the side or sides that are in contact with it. In addition, when the primary auxiliary bonding layers are prepared on both wafers as in fig. 2, the materials of the first primary auxiliary bonding layer 40a and the second primary auxiliary bonding layer 40b may be the same or different, and preferably the same. When the two are made of the same material, the bonding strength between the first conductive layer 402a and the second conductive layer 402b can be improved by ensuring stronger covalent bonding force at the bonding interface during bonding and heat treatment of the two wafers.
In the embodiment of the application, the heat treatment can be performed at the temperature of 100-1000 ℃ for 1min-10h. In some embodiments, the heat treatment is performed at a temperature of 100 to 600 ℃, for example, specifically 100 ℃, 150 ℃, 200 ℃, 220 ℃, 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, 550 ℃, 580 ℃, or the like, and the heat treatment may be further performed at a temperature in the range of 100 to 200 ℃. The lower heat treatment temperature can ensure that the reduction of the original auxiliary bonding layer can be smoothly carried out, and simultaneously, the damage to the device functional layer on the wafer is reduced, so that the bonded structure can normally play a role. The heat treatment may be performed for a period of time of, in particular, 5min, 10min, 15min, 20min, 30min, 40min, 1h, 2h, 3h, 5h, 8h, etc. The specific temperature and time of the heat treatment can be regulated and controlled according to the material or thickness of the original auxiliary bonding layer.
In step S04, the "bonding" may be performed under a pressurized condition, for example, by applying pressure to one or both of the first substrate and the second substrate. The bonding and the heat treatment may be performed simultaneously, for example, in a bonding machine having a heating function, or may be performed in a bonding machine, or may be performed after the "heat treatment" is performed in other heating equipment (e.g., a tube furnace, a rapid annealing furnace, etc.).
Bonding between two wafers directly provided with a metal bonding layer is carried out based on the prior art, strict and complex requirements on the type of the metal bonding layer, the flatness, the compactness and the like of bonding surfaces are met, but the embodiment of the application comprises the wafer bonding method of the steps S01-S04. Therefore, the wafer bonding method has the advantages of simple process, strong universality and low bonding difficulty, can realize the convenience and high-strength bonding between any two wafers with the metal bonding layer, and reduces the excessive dependence on substrate materials, bonding processes and the like in the conventional wafer bonding method.
When the original auxiliary bonding layers are introduced on the metal bonding layers of the two wafers, bonding surfaces of the two wafers can be respectively covered by the same materials, bonding difficulty is reduced, the two wafers can be conveniently and rapidly subjected to primary hydrogen bonding after being attached, the distance between the adjacent wafers is better pulled, reduction reaction is facilitated during heat treatment, good surface state (such as no hole) of the obtained conductive layer is ensured, no gap exists between the conductive layer and the metal bonding layer, and the like. In addition, when the thickness of the original auxiliary bonding layer is lower, two wafers can be stably bonded together, and the deposited thinner film layer can not adversely affect the roughness of the surface to be bonded of the wafers to affect bonding, so that planarization treatment of the surface to be bonded can be omitted, the complexity of the bonding process is reduced, and damage to the structure/function of the wafers in the heat treatment process can be reduced.
In some embodiments of the present application, after the step S04, the method further includes step S05: one of the two substrates is removed to yield semiconductor structure 100. As exemplified in fig. 2 or 3 by removal of the second substrate 10 b. The substrate removal can be realized by mechanical grinding, CMP, wet etching, dry etching and other methods, and the wafer substrate on one side is reserved so as to carry out the subsequent wafer device processing flow.
If only one of the two wafers used in step S01 has the device functional layer on the first side of the substrate, the substrate of the wafer having the device functional layer is generally removed when the operation of removing one of the substrates is performed, and the subsequent process is generally performed on the exposed device functional layer. Specifically, referring to fig. 4, fig. 4 is a schematic diagram illustrating another modification of the wafer bonding method shown in fig. 2. Fig. 4 differs from fig. 2 in that: before the formation of the metal bonding layer, the first wafer 1a comprises only the first substrate 10a, whereas the first side 101a of the first substrate 10a is free of the second device functional layer 20a, and the second wafer 1b comprises also the second substrate 10b and the first device functional layer 20b provided on the first side 101b thereof. Accordingly, the first metal bonding layer 30a is in direct contact with the first side surface of the first substrate 10a, and the second metal bonding layer 30b is disposed on the side of the first device functional layer 20b facing away from the second substrate 10b. After the bonding process and the heat treatment, the second substrate 10b on the second wafer 1b is removed.
Fig. 5 is a schematic diagram illustrating a specific process of a wafer bonding method according to another embodiment of the present application. The main differences between the method shown in fig. 5 and fig. 2 are that: the metal bonding layers are formed on the substrate at intervals, and an insulating bonding layer is introduced between the metal bonding layers. Specifically, the wafer bonding method shown in fig. 5 includes:
S501, as shown in fig. 5 (a), two wafers to be bonded, a first wafer 1a and a second wafer 1b are provided, the first wafer 1a including a first substrate 10a and a second device functional layer 20a provided on a first side 101a of the first substrate 10a, and the second wafer 1b including a second substrate 10b and a first device functional layer 20b provided on a first side 101b of the second substrate 10 b. Wherein the second device functional layer 20a entirely covers the first side 101a of the first substrate 10a and the first device functional layer 20b entirely covers the first side 101b of the second substrate 10 b.
S502, a plurality of metal bonding layers are formed on two wafers at intervals respectively, the metal bonding layers are located on the first side of the substrate, an insulating bonding layer is further formed between two adjacent metal bonding layers, and the surface of the insulating bonding layer, deviating from the substrate, is flush with the surface of the metal bonding layer, deviating from the substrate.
As shown in fig. 5 (B), a plurality of first metal bonding layers 30a are formed on a side surface of the second device functional layer 20a facing away from the first substrate 10a, a first insulating bonding layer 31a is sandwiched between two adjacent first metal bonding layers 30a, a plurality of second metal bonding layers 30B are formed on a side surface of the first device functional layer 20B facing away from the second substrate 10B, and a second insulating bonding layer 31B is sandwiched between two adjacent second metal bonding layers 30B. Wherein the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a, and the surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with the surface of the second metal bonding layer 30b facing away from the second substrate 10 b. That is, the first insulating bonding layer 31a has the same thickness as the first metal bonding layer 30a, and the second insulating bonding layer 31b has the same thickness as the second metal bonding layer 30 b. Referring to the foregoing description of the thickness of the metal bonding layer according to the present application, it is understood that the thickness of the first and second insulating bonding layers 31a and 31b may be between several nanometers and several tens of micrometers, respectively, for example, in the range of 10nm-10 μm. In addition, the material of each insulating bonding layer may be the same as or different from the original auxiliary bonding layer below, and each insulating bonding layer includes, but is not limited to, various dielectric materials such as silicon oxide, silicon nitride, titanium oxide, aluminum oxide, and the like.
Since the metal bonding layer and the insulating bonding layer exist in different regions of the same wafer at the same time, that is, two different bonding materials exist in different bonding regions, bonding of two wafers can be called as 'hybrid bonding'. In the prior art, the metal bonding layers are directly bonded and the insulating bonding layers are directly bonded, but the surface treatment and bonding conditions of different bonding materials have strict requirements, so that the difficulty and failure rate of the hybrid bonding are increased. The following primary auxiliary bonding layer and related processes are therefore introduced in the embodiments of the present application.
S503, forming an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of two wafers with the metal bonding layer and the insulating bonding layer; wherein the original auxiliary bonding layer is an insulating compound.
As shown in fig. 5 (C), a first original auxiliary bonding layer 40a covering one entire surface of the first metal bonding layer 30a and the first insulating bonding layer 31a is formed on the first side 101a of the first wafer, and a second original auxiliary bonding layer 40b covering one entire surface of the second metal bonding layer 30b and the second insulating bonding layer 31b is formed on the first side 101b of the second wafer. The thickness, material, function, etc. of each original auxiliary bonding layer can be selected according to the previous description of the present application.
When the mixed bonding of the two wafers is carried out, the original auxiliary bonding layer is introduced, so that bonding materials in different areas of the wafers with the original auxiliary bonding layer are covered by the same material, and the bonding difficulty of the two wafers is reduced. When the original auxiliary bonding layers are introduced on the substrates of the two wafers, bonding materials in different areas of the two wafers can be covered by the same material, and the hybrid bonding of the two wafers becomes bonding of dielectric materials, so that the requirements on the materials of the metal bonding layer and the insulating bonding layer, surface treatment and the like are reduced, and the high-quality hybrid bonding can be conveniently realized under the simple bonding condition.
In an embodiment of the present application, a surface of the original auxiliary bonding layer facing away from the wafer substrate is flat. For fig. 5 (C), the surface of the first primary auxiliary bonding layer 40a facing away from the first substrate 10a is planar, and the surface of the second primary auxiliary bonding layer 40b facing away from the second substrate 10b is planar. Thus, the bonding of two wafers can be more conveniently completed, and the bonding power is higher.
And S504, bonding the two wafers subjected to the treatment so that the metal bonding layers on the two wafers are arranged oppositely one by one and correspondingly the insulating bonding layers are also arranged oppositely one by one, and performing heat treatment on the two bonded wafers so that the original auxiliary bonding layers clamped between the two metal bonding layers (namely, the two metal bonding layers oppositely arranged along the thickness direction of the substrate) which are correspondingly arranged in the two wafers are reduced into conductive layers, particularly the parts of the original auxiliary bonding layers which are contacted with the metal bonding layers are reduced, and the original auxiliary bonding layers in other areas remain unchanged.
As shown in fig. 5 (D), after the two wafers are bonded, the first original auxiliary bonding layer 40a is in contact with the second original auxiliary bonding layer 40b, wherein the two wafers can be bonded with hydroxyl groups by means of hydroxyl dangling bonds on the surface of the material of the original auxiliary bonding layer. And, each of the first metal bonding layers 30a has a second metal bonding layer 30b disposed opposite thereto, and each of the first insulating bonding layers 31a is disposed opposite to a second insulating bonding layer 31 b. After the bonded two wafers are subjected to heat treatment, as shown in (E) of fig. 5, the bonding interface of the two wafers is converted into covalent bonding with higher bonding strength, and the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b are reduced, specifically, the first original auxiliary bonding layer 40a is reduced to the first conductive layer 402a by the first metal bonding layer 30a in contact therewith, and the second original auxiliary bonding layer 40b is reduced to the second conductive layer 402b by the second metal bonding layer 30b in contact therewith; while the portions of the first and second original auxiliary bonding layers sandwiched between the first and second insulating bonding layers 31a and 31b remain unchanged, and are denoted by reference numerals 401a and 401b, respectively, for convenience of distinction. It will be appreciated that, along the thickness direction perpendicular to the first substrate 10a, a first auxiliary bonding layer 401a is provided between adjacent first conductive layers 402a, and a second auxiliary bonding layer 401b is provided between adjacent second conductive layers 402 b.
In addition, as described in the foregoing description of the present application, the surface to be bonded may be subjected to hydrophilic treatment before the bonding of the wafer; the process conditions of the hydrophilic treatment, the fitting, the heat treatment, etc. can be seen from the foregoing description. After the heat treatment of step S504, a step of "removing one of the two substrates" is further included.
For the hybrid bonding between two wafers with a conductive metal bonding layer and a non-conductive insulating bonding layer, the above wafer bonding method of the embodiment of the present application including steps S501-S504, by introducing the original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of the two wafers, the original low-temperature bonding after bonding the two wafers can be conveniently realized by means of the original auxiliary bonding layer, and the high-strength covalent bonding between bonding interfaces can be realized by means of heat treatment, and the upper and lower metal bonding layers of the two wafers only reduce the original auxiliary bonding layer sandwiched between them in situ, so that the longitudinal conductive connection between the corresponding metal bonding layers in the two wafers is ensured, and the current insulation separation between the adjacent metal bonding layers in the same wafer is ensured by means of the non-conductive auxiliary bonding layer kept in original state between the upper and lower insulating bonding layers.
Fig. 6 is a schematic diagram illustrating a modification of the wafer bonding method shown in fig. 5. The main differences between the method shown in fig. 6 and fig. 5 are that: in fig. 6, the original auxiliary bonding layer 40 is formed only on the second wafer 1 b. The advantageous effects of the method of fig. 6 are similar to those of fig. 5 and are not described in detail here.
In fig. 6, after the two wafers are bonded, the material of the second metal bonding layer 30b and/or the first metal bonding layer 30a near the side of the original auxiliary bonding layer 40 should have a higher reducibility than that of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer 40. Thus, during the heat treatment, the portion of the original auxiliary bonding layer 40 sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b may be reduced to the conductive layer 402, where the original auxiliary bonding layer 40 may be specifically reduced by the first metal bonding layer 30a, or reduced by the second metal bonding layer 30b, or reduced by the first metal bonding layer 30a and the second metal bonding layer 30b together, and the specific reduction may be determined according to the specific materials of the three materials.
It should be noted that fig. 5 and 6 illustrate the case where the metal bonding layers on the two wafers are completely aligned during bonding, but it is understood that the alignment of the metal bonding layers on the two wafers may also allow for a certain offset, and particularly, refer to fig. 7 and 8.
Fig. 7 is a schematic diagram of another process of bonding and heat treating the two wafers in fig. 5. In fig. 7, after the two wafers are bonded, the first metal bonding layer 30a and the second metal bonding layer 30b are disposed in a one-to-one opposite manner, but are not fully aligned, and a certain offset occurs, and accordingly, the first insulating bonding layer 31a and the second insulating bonding layer 31b are disposed in a one-to-one opposite manner, but are not fully aligned. Upon heat treatment, the first original auxiliary bonding layer 40a in contact with the first metal bonding layer 30a is reduced by the first metal bonding layer 30a to the first conductive layer 402a, and the second original auxiliary bonding layer 40b in contact with the second metal bonding layer 30b is reduced by the second metal bonding layer 30b to the second conductive layer 402b, i.e., the distribution position of the first conductive layer 402a substantially coincides with the first metal bonding layer 30a, and the distribution position of the second conductive layer 402b substantially coincides with the second metal bonding layer 30 b.
Fig. 8 is a schematic diagram of another process of bonding and heat treating the two wafers in fig. 6. In fig. 8, after the two wafers are bonded, if the reducibility of the materials of the second metal bonding layer 30b and the first metal bonding layer 30a near the side of the original auxiliary bonding layer 40 is higher than the reducibility of the simple substance corresponding to the normal valence element in the original auxiliary bonding layer 40, at this time, if the first metal bonding layer 30a and the second metal bonding layer 30b are disposed oppositely one by one but not aligned completely, the original auxiliary bonding layer 40 sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b and contacting with the two is reduced to the conductive layer 402 together by the two, that is, the obtained conductive layer 402 corresponds to the union of the auxiliary bonding layers contacting with the first metal bonding layer 30 a/the second metal bonding layer 30 b.
Therefore, even if the two wafers cannot be completely aligned with each metal bonding layer on the two wafers during bonding, the wafer bonding method provided by the embodiment of the application, which introduces the original auxiliary bonding layer, can still ensure the longitudinal conductive connection between the upper and lower metal bonding layers which are not completely aligned and the insulation separation between the metal bonding layers in the transverse direction.
Fig. 9 is a schematic diagram illustrating another modification of the wafer bonding method shown in fig. 5. Fig. 9 differs from fig. 5 in that: only one of the two wafers used carries a device function layer, in particular the second wafer 1b in fig. 9. Before forming the auxiliary bonding layer, the first wafer 1a includes only the first substrate 10a and the plurality of first metal bonding layers 30a formed on the first side 101a thereof at intervals, and the adjacent two first metal bonding layers 30a sandwich the first insulating bonding layer 31a. After the bonding and heat treatment of the two wafers, the second substrate 10b in the second wafer 1b with the device functional layer is removed.
Fig. 10 is a schematic diagram illustrating a process of a wafer bonding method according to another embodiment of the present application. The main differences between the method shown in fig. 10 and fig. 2 are also: the metal bonding layers are formed on the substrate at intervals, and an insulating bonding layer is introduced between the metal bonding layers. Fig. 10 is different from fig. 5 in that a metal bonding layer is formed on a substrate at intervals: the distribution of the device functional layers over the substrate is different. The wafer bonding method shown in fig. 10 may specifically include:
in step 1, as shown in fig. 10 (a), two wafers to be bonded, a first wafer 1a and a second wafer 1b are provided, the first wafer 1a including a first substrate 10a and a plurality of second device function layers 20a provided on a first side 101a of the first substrate 10a at intervals, and the second wafer 1b including a second substrate 10b and a plurality of first device function layers 20b provided on the first side 101b of the second substrate 10b at intervals.
And 2, respectively forming a plurality of metal bonding layers arranged at intervals on the two wafers, wherein the metal bonding layers are positioned on the first side of the substrate, and an insulating bonding layer is further formed between two adjacent metal bonding layers. Wherein, the surface of insulating bonding layer facing away from place substrate flushes with the surface of metal bonding layer facing away from place substrate. Thus, the auxiliary bonding layer with a flat surface is formed later, and the wafer bonding power is improved.
In fig. 10B, specifically, a first metal bonding layer 30a is formed on a side surface (may be referred to as a third surface 201 a) of each second device functional layer 20a facing away from the first substrate 10a, and a second metal bonding layer 30B is formed on a side surface (may be referred to as a third surface 201B) of each first device functional layer 20B facing away from the second substrate 10B, and is capable of covering the third surface 201B. Since the device functional layers are spaced apart on the substrate, the metal bonding layers disposed on the device functional layers are correspondingly spaced apart. Wherein, a first insulating bonding layer 31a is disposed between the laminated structure formed by the second device functional layer 20a and the first metal bonding layer 30a, and the first insulating bonding layer 31a may contact the first substrate 10a, and its thickness is equal to the sum of the thicknesses of the second device functional layer 20a and the first metal bonding layer 30a, so as to ensure that the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10 a. Similarly, a second insulating bonding layer 31b is provided between the stacked structure of the first device functional layer 20b and the second metal bonding layer 30b, and the second insulating bonding layer 31b may be in contact with the second substrate 10b, and the thickness of the second insulating bonding layer 31b may be equal to the sum of the thicknesses of the first device functional layer 20b and the second metal bonding layer 30b, so as to ensure that the surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with the surface of the second metal bonding layer 30b facing away from the second substrate 10 b.
Step 3, forming an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of two wafers with the metal bonding layer and the insulating bonding layer; wherein the original auxiliary bonding layer is an insulating compound. As shown in fig. 10 (C), a first side 101a of the first wafer is formed with a first original auxiliary bonding layer 40a covering the first metal bonding layer 30a and the first insulating bonding layer 31a, and a first side 101b of the second wafer is formed with a second original auxiliary bonding layer 40b covering the second metal bonding layer 30b and the second insulating bonding layer 31 b. The thickness, material, function, etc. of each auxiliary bonding layer can be selected according to the above description of the present application. As in fig. 5, the surface of the first primary auxiliary bonding layer 40a facing away from the first substrate 10a is planar, and the surface of the second primary auxiliary bonding layer 40b facing away from the second substrate 10b is planar. Thus, the bonding of two wafers can be more conveniently completed, and the bonding power is higher.
And 4, as shown in fig. 10 (D), bonding the two wafers processed in the steps 1-3, so that the metal bonding layers on the two wafers are arranged and aligned one by one, and correspondingly the insulating bonding layers are also arranged and aligned one by one, and performing heat treatment on the bonded two wafers, so that the original auxiliary bonding layer sandwiched between the two metal bonding layers arranged correspondingly in the two wafers is reduced to a conductive layer, as shown in fig. 10 (E). Specifically, the portion of the original auxiliary bonding layer that is in contact with the metal bonding layer during the heat treatment is reduced, while the auxiliary bonding layer in the other region remains as it is.
For hybrid bonding between two wafers with a conductive metal bonding layer and a non-conductive insulating bonding layer at the same time, in the wafer bonding method shown in fig. 10, by introducing an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of the two wafers, high-quality bonding between corresponding metal bonding layers and corresponding insulating bonding layers in the two wafers can be conveniently realized by means of the original auxiliary bonding layer, and in-situ reduction of only the part of the original auxiliary bonding layer sandwiched between the upper and lower metal bonding layers of the two wafers can realize conductive connection of the upper and lower device functional layers in the longitudinal direction between the two wafers and current insulation separation between the discrete device functional layers in the same wafer.
Fig. 11 is a schematic diagram illustrating a modification of the wafer bonding method shown in fig. 10. The main difference between the method shown in fig. 11 and fig. 10 is that: in fig. 11, only one original auxiliary bonding layer 40 is formed on the second wafer 1 b. After bonding and heat treatment of the two wafers, the conductive layer 402 sandwiched between the upper and lower metal bonding layers is also one layer in the thickness direction of the substrate.
With respect to the relationship between the material reducibility of the first and second metal bonding layers 30a and 30b and the material of the original auxiliary bonding layer 40 in fig. 11, reference is made to the description of fig. 6 above. The advantageous effects of the method of fig. 11 are similar to those of fig. 10 and are not described in detail here.
Fig. 12 is a schematic diagram illustrating another variation of the wafer bonding method shown in fig. 10. Fig. 12 differs from fig. 10 in that: only one of the two wafers is used with a device function layer, and in particular the second wafer 1b in fig. 12 has a plurality of first device function layers 20b arranged at intervals.
Before forming the original auxiliary bonding layer, the first wafer 1a includes only the first substrate 10a and a plurality of first metal bonding layers 30a formed on the first side 101a thereof at intervals, and two adjacent first metal bonding layers 30a sandwich the first insulating bonding layer 31a. The thickness of the first insulating bonding layer 31a is the same as the first metal bonding layer 30a so that the surfaces thereof facing away from the first substrate 10a may be flush. The second wafer 1b includes a second substrate 10b and a plurality of first device functional layers 20b disposed on a first side 101b of the second substrate 10b at intervals, a second metal bonding layer 30b capable of covering the first device functional layers 20b is formed on a surface of a side of each first device functional layer 20b facing away from the second substrate 10b, a second insulating bonding layer 31b is disposed between a laminated structure formed by the first device functional layers 20b and the second metal bonding layer 30b, and a thickness of the second insulating bonding layer 31b is equal to a sum of thicknesses of the first device functional layers 20b and the second metal bonding layer 30b, so as to ensure that a surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with a surface of the second metal bonding layer 30b facing away from the second substrate 10 b.
In fig. 12, after bonding and heat treatment of the two wafers, the second substrate 10b is removed from the second wafer 1b with the device functional layer, specifically, when the substrate is removed. The advantageous effects of the method of fig. 12 are similar to those of fig. 10 and are not described in detail here.
The wafer bonding method provided by the embodiment of the application can be suitable for wafer bonding in semiconductor manufacturing processes of power electronic devices, radio frequency electronic devices, LEDs (LIGHT EMITTING diode), MEMS (Micro Electro MECHANICAL SYSTEM), and the like.
The following describes a semiconductor structure provided by an embodiment of the present application. The semiconductor structure can be prepared by the wafer bonding method.
In some embodiments, a semiconductor structure is provided that includes both a metal bonding layer and an insulating bonding layer, so that the semiconductor structure in this case may also be referred to as a "hybrid bonding semiconductor structure".
Fig. 13A and 13B are schematic structural diagrams of a semiconductor structure according to some embodiments of the present application. Referring to fig. 13A and 13B, the semiconductor structure 100 specifically includes:
A first substrate 10a and a plurality of first metal bonding layers 30a, wherein the plurality of first metal bonding layers 30a are arranged on a first side 101a of the first substrate 10a at intervals, and a first insulating bonding layer 31a is arranged between two adjacent first metal bonding layers 30 a;
The first device functional layer 20b and the plurality of second metal bonding layers 30b, the second metal bonding layers 30b are disposed on a side of the first device functional layer 20b facing the first substrate 10a, the plurality of first metal bonding layers 30a are disposed opposite to the plurality of second metal bonding layers 30b one by one, and the second insulating bonding layers 31b are disposed between two adjacent second metal bonding layers 30b along a thickness direction perpendicular to the first substrate 10a (correspondingly, each second insulating bonding layer 31b is also disposed opposite to the first insulating bonding layer 31a one by one). A conductive layer 402 is further disposed between each first metal bonding layer 30a and the second metal bonding layer 30b opposite thereto, and an auxiliary bonding layer 401 is disposed between adjacent conductive layers 402 along a thickness direction (z direction in the drawing) perpendicular to the first substrate 10a, wherein the auxiliary bonding layer 401 is made of an insulating compound.
Wherein the conductive layer 402 contains the same element as the normal valence element in the auxiliary bonding layer 401, the material of the first metal bonding layer 30a and/or the second metal bonding layer 30b on the side close to the conductive layer 402 has a higher reducibility than the material of the conductive layer 402 in the thickness direction of the first substrate 10 a. As can be reflected by this, the conductive layer 402 is reduced by the first metal bonding layer 30a and/or the second metal bonding layer 30b, which is the same material as the auxiliary bonding layer 401.
In the semiconductor structure 100, the conductive layer 402 and the auxiliary bonding layer 401 disposed on the same plane thereof will be located between the structures on the upper and lower sides thereof to establish a bonding bridge, so as to ensure the stability of the overall structure of the semiconductor structure 100, realize high strength bonding between the upper and lower metal bonding layers and between the upper and lower insulating bonding layers, and not affect the longitudinal conductive connection between the upper and lower metal bonding layers and the lateral electrical insulation between the adjacent metal bonding layers in the thickness direction perpendicular to the first substrate.
In the embodiment of the present application, the interface of the first metal bonding layer 30a and/or the second metal bonding layer 30b near the conductive layer 402 contains the same element as the negative valence element in the auxiliary bonding layer 401. This may reflect that the first metal bonding layer 30a and/or the second metal bonding layer 30b deprives the same material of the negative valence element as the auxiliary bonding layer 401. It may also be reflected to some extent that the conductive layer 402 is a material that is the same as the auxiliary bonding layer 401, chemically reduced by the first metal bonding layer 30a and/or the second metal bonding layer 30 b. In addition, it can also be stated that covalent bonding can exist between the interface of the conductive layer and the upper and lower metal bonding layers, with higher bond strength.
In the embodiment of the present application, the surface of the conductive layer 402 contacting the first metal bonding layer 30a or the second metal bonding layer 30b is flat and has no breakage. The formation of the conductive layer 402 is a result of in-situ chemical reaction, and the surface state of the film layer is not significantly damaged compared with the surface state of the non-reduced auxiliary bonding layer 401, which is beneficial to ensuring good conductive connection between the conductive layer 402 and the first metal bonding layer 30a and the second metal bonding layer 30b, and ensuring that the structure of the semiconductor structure 100 is relatively stable.
For the above-described "auxiliary bonding layer 401 is sandwiched between adjacent conductive layers 402 in the thickness direction perpendicular to the first substrate 10 a", that is, the auxiliary bonding layer 401 is sandwiched between each first insulating bonding layer 31a and one second insulating bonding layer 31b in the thickness direction of the first substrate 10 a. Wherein the conductive layer 402 and the auxiliary bonding layer 401 have the same thickness, and are arranged in a coplanar manner.
The semiconductor structure 100 shown in fig. 13A may be fabricated using a method similar to that described above with respect to fig. 9 (except that the dielectric auxiliary layer is formed on only one wafer). In fig. 13A, the first device functional layer 20b is a complete film, and a plurality of second metal bonding layers 30b are disposed at intervals on a side of the first device functional layer 20b facing the first substrate 10 a. The first device functional layer 20b covers a side surface of the plurality of second metal bonding layers 30b facing away from the first substrate 10a, and a side surface of the plurality of second insulating bonding layers 31b facing away from the first substrate 10 a.
The semiconductor structure 100 shown in fig. 13B may be fabricated using a method similar to that described above with respect to fig. 12 (except that the dielectric auxiliary layer is formed on only one wafer). In fig. 13B, each of the second metal bonding layers 30B is provided with (specifically, covered with) one first device functional layer 20B on a side facing away from the first substrate 10 a. That is, the first device functional layer 20b has a plurality, the number of which is identical to the number of the second metal bonding layers 30 b; the orthographic projections of the plurality of first device functional layers 20b on the first substrate 10a are spaced apart. From another perspective, the first device functional layer in fig. 13B may be considered to be a discontinuous film layer, and may be considered to include a plurality of first device functional sublayers disposed at intervals, where each of the second metal bonding layers 30B is provided with a first device functional sublayer on a side facing away from the first substrate 10a, and no separate reference numerals are used herein.
In the embodiment of the present application, as shown in fig. 13A and 13B, the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10 a; the surface of the second insulating bonding layer 31b facing the first substrate 10a is flush with the surface of the second metal bonding layer 30b facing the first substrate 10 a. In this way, the surfaces of the conductive layer 402 and the auxiliary bonding layer 401 facing away from or towards the first substrate 10a are smooth, which is beneficial to ensuring smooth preparation of the semiconductor structure and maintaining good stability. In fig. 13A, the first insulating bonding layer 31a and the first metal bonding layer 30a have the same thickness, and the second insulating bonding layer 31b and the second metal bonding layer 30b have the same thickness; in fig. 13B, the thickness of the first insulating bonding layer 31a is the same as that of the first metal bonding layer 30a, but the thickness of the second insulating bonding layer 31B is equal to the sum of the thicknesses of the second metal bonding layer 30B and the first device functional layer 20B.
In the embodiment of the present application, the auxiliary bonding layer 401 may be one layer (as shown in fig. 13A and 13B) or two layers; the number of layers of the conductive layer 402 is the same as that of the auxiliary bonding layer 401. In some embodiments, the auxiliary bonding layer 401 and the conductive layer 402 are one layer, and the thicknesses of the auxiliary bonding layer 401 and the conductive layer 402 may be in the range of 0.5nm to 100nm, for example, preferably in the range of 0.5nm to 10nm, and particularly, reference is made to the description of the single-layer initial auxiliary bonding layer. In addition, the materials, thicknesses, etc. of the first metal bonding layer 30a and the second metal bonding layer 30b can also be referred to as the foregoing description.
In the embodiment of the present application, the material of the auxiliary bonding layer 401 includes one or more of metal oxide, metal nitride, silicon oxide containing doping element, silicon nitride containing doping element, and silicon oxynitride containing doping element. Wherein the metal elements in the metal oxide and the metal nitride comprise one or more of aluminum Al, tantalum Ta, hafnium Hf and zirconium Zr. Accordingly, the material of the conductive layer 402 includes elemental silicon containing a doping element or other metal materials, wherein the material of the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b near the conductive layer 402 has a higher reducibility than those of the other metal materials. Wherein the other metal material is a simple substance corresponding to a metal element in the metal oxide or the metal nitride. The other metal materials include one or more of aluminum Al, tantalum Ta, hafnium Hf, zirconium Zr.
Based on "the conductive layer 402 contains the same element as the normal valence element in the auxiliary bonding layer 401", it is understood that when the auxiliary bonding layer 401 is a metal oxide or a metal nitride, the conductive layer 402 is the other metal material. When the auxiliary bonding layer 401 is silicon oxide containing a doping element, silicon nitride containing a doping element, silicon oxynitride containing a doping element, the conductive layer 402 is a silicon simple substance containing a doping element.
In some embodiments of the present application, the auxiliary bonding layer 401 is an oxide or nitride of aluminum, and the material of the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b near the conductive layer 402 includes at least one of Ti, cr, and Ni. In other embodiments, the auxiliary bonding layer 401 is an oxide or nitride of tantalum, hafnium, zirconium, where the material of the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b adjacent to the conductive layer 402 includes at least one of Al, ti, cr, ni.
Fig. 13C is a schematic structural diagram of another semiconductor structure in the case where the auxiliary bonding layer 401 is two layers in fig. 13A, and fig. 13D is a schematic structural diagram of another semiconductor structure in the case where the auxiliary bonding layer 401 is two layers in fig. 13B. The semiconductor structure shown in fig. 13C may be manufactured by the method shown in fig. 9, and the semiconductor structure shown in fig. 13D may be manufactured by the method shown in fig. 12.
As shown in fig. 13C and 13D, the auxiliary bonding layer 401 is two layers, specifically including a first auxiliary bonding layer 401a and a second auxiliary bonding layer 401b that are stacked, and the first auxiliary bonding layer 401a is close to the first insulating bonding layer 31a; the conductive layer 402 includes a first conductive layer 402a and a second conductive layer 402b that are stacked, and the first conductive layer 402a is adjacent to the first metal bonding layer 30a. The first conductive layer 402a is formed by reducing the first metal bonding layer 30a with the same material as that of the first auxiliary bonding layer 401a, and the second conductive layer 402b is formed by reducing the second metal bonding layer 30b with the same material as that of the second auxiliary bonding layer 401 b. Accordingly, the first conductive layer 402a contains the same element as the normal valence element in the first auxiliary bonding layer 401a, and the material of the first metal bonding layer 30a on the side close to the first conductive layer 402a has a higher reducibility than the material of the first conductive layer 402 a; the second conductive layer 402b contains the same element as the normal valence element in the second auxiliary bonding layer 401b, and the material of the second metal bonding layer 30b on the side close to the second conductive layer 402b has a higher reducibility than the material of the second conductive layer 402 b.
When the auxiliary bonding layer 401 is two layers, the bonding interface is made of the same material, so that the covalent bonding can be better realized, the bonding strength is improved, and the structural stability of the semiconductor structure 100 is higher. It is understood that if the auxiliary bonding layer 401 is two layers, the thickness of the auxiliary bonding layer 401 or the conductive layer 402 may be in the range of 1nm to 200nm, preferably in the range of 1nm to 20nm, respectively.
In some embodiments of the present application, referring to fig. 13E, 13F, 13G, and 13H, the semiconductor structure 100 further includes a second device functional layer 20a, which is located between the first substrate 10a and the first metal bonding layer 30a and is disposed corresponding to the first device functional layer 20 b. Accordingly, the second device functional layer 20a is located on a side of the first substrate 10a facing the first device functional layer 20b (i.e., on the first side 101a of the first substrate 10 a), the plurality of first metal bonding layers 30a are disposed at intervals, and the first metal bonding layers 30a are disposed on a side of the second device functional layer 20a facing away from the first substrate 10 a.
The semiconductor structure shown in fig. 13E may be prepared by the method shown in fig. 5 (the second substrate 10b is removed on the basis of fig. 5), and the semiconductor structure shown in fig. 13F may be prepared by the method shown in fig. 6 (the second substrate 10b is removed on the basis of fig. 6). Fig. 13F differs from fig. 13E only in that: the auxiliary bonding layer 401 and the conductive layer 402 have different layers.
In fig. 13E and 13F, the second device functional layer 20a is a complete film layer, which entirely covers the first side 101a of the first substrate 10a, and a plurality of first metal bonding layers 30a are disposed on a surface of the second device functional layer 20a facing away from the first substrate 10 a. Since one first insulating bonding layer 31a is disposed between two adjacent first metal bonding layers 30a, a plurality of first insulating bonding layers 31a are also disposed at intervals on the side of the second device functional layer 20a facing away from the first substrate 10 a. The first device functional layer 20b is disposed opposite to the second device functional layer 20a, and similarly, a plurality of second metal bonding layers 30b are disposed on a surface of the first device functional layer 20b facing the first substrate 10a at intervals, and a second insulating bonding layer 31b is interposed between two adjacent second metal bonding layers 30 b. Regarding the distribution positions of the first auxiliary bonding layer 401a, the second auxiliary bonding layer 401b, the first conductive layer 402a, the second conductive layer 402b, and the like, reference is made to the description of fig. 13C and 13D above in connection with the present application.
The semiconductor structure shown in fig. 13G may be prepared by the method shown in fig. 10 described above (the second substrate 10b is removed on the basis of fig. 10), and the semiconductor structure shown in fig. 13H may be prepared by the method shown in fig. 11 described above (the second substrate 10b is removed on the basis of fig. 11). Fig. 13G differs from fig. 13H only in that: the auxiliary bonding layer 401 and the conductive layer 402 have different layers.
In fig. 13G and 13H, a plurality of second device functional layers 20a are disposed on the first side 101a of the first substrate 10a at intervals, and a surface of a side of each second device functional layer 20a facing away from the first substrate 10a is covered with a first metal bonding layer 30a. Such that the plurality of first metal bonding layers 30a are spaced apart on the first side 101a of the first substrate 10 a. The second device functional layer 20a and the first metal bonding layer 30a form a laminated structure, a first insulating bonding layer 31a is arranged between two adjacent laminated structures, and the thickness of the first insulating bonding layer 31a is equal to the sum of the thicknesses of the second device functional layer 20a and the first metal bonding layer 30a, so that the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a, and smooth preparation of the semiconductor structure and good stability are facilitated.
In fig. 13G and 13H, the plurality of second metal bonding layers 30b are disposed in one-to-one correspondence with the plurality of first metal bonding layers 30a, and the plurality of second insulating bonding layers 31b are disposed in one-to-one correspondence with the plurality of first insulating bonding layers 31 a. Correspondingly, one side of each second metal bonding layer 30b, which faces away from the first substrate 10a, is covered with a first device functional layer 20b, the first device functional layer 20b and the second metal bonding layers 30b form another laminated structure, a second insulating bonding layer 31b is sandwiched between two adjacent laminated structures, and the thickness of the second insulating bonding layer 31b is equal to the sum of the thicknesses of the first device functional layer 20b and the second metal bonding layer 30b, so that the surface of the second insulating bonding layer 31b facing the first substrate 10a and the surface of the second metal bonding layer 30b facing the first substrate 10a are flush, and smooth preparation of the semiconductor structure and good stability are facilitated.
As can be seen from the above description, the semiconductor structure shown in fig. 13E to 13H contains two device functional layers at the same time, so that stable integration of the device functional layers with different functions in one semiconductor structure can be realized.
In addition, the functional layers of the devices in the semiconductor structure 100 shown in fig. 13A to 13H may be one or more layers. In some embodiments, each device functional layer may be a semiconductor device including an epitaxial stacked structure formed based on a iii-v semiconductor material (e.g., gaN, gaAs, alN, alGaN, inN, etc.). For example, the second device functional layer 20a may include a first buffer layer, a first n-type doped layer, a first active layer, and a first p-type doped layer, which are stacked, with the first buffer layer being adjacent to the first substrate 10a; the first device functional layer 20b includes a second buffer layer, a second n-type doped layer, a second active layer, and a second p-type doped layer, which are stacked, and the second buffer layer is away from the first substrate. Such semiconductor structures are particularly suitable for the preparation of optoelectronic devices, such as inorganic electroluminescent devices, or photodetection devices, etc.
In addition, the semiconductor structures of fig. 13A to 13H are all illustrated with the first metal bonding layer 30a and the second metal bonding layer 30b being fully aligned, but as can be seen from the description of fig. 7 and 8, the semiconductor structures of the present application may be configured with the first metal bonding layer 30a and the second metal bonding layer 30b being not fully aligned, for example, with a certain alignment offset, but still ensure good structural stability of the semiconductor structures.
The embodiment of the application also provides a semiconductor device, which comprises the semiconductor structure provided by the embodiment of the application or the semiconductor structure obtained by the wafer bonding method provided by the embodiment of the application. The semiconductor device has high structural stability, can stably exert the functions thereof, and has strong market competitiveness.
The semiconductor structure of the embodiment of the application can be directly used as a part of a semiconductor device, or can be stripped off to be applied to the semiconductor device. The semiconductor device includes, but is not limited to, an optoelectronic device, or a power device (i.e., a power electronic device) or a radio frequency device, etc. In some embodiments, the optoelectronic device may be an electroluminescent device, for example, a light emitting Diode (LIGHT EMITTING Diode, LED) or a Laser Diode (LD), and in particular may be a nitride-based light emitting Diode, nitride-based quantum well Laser Diode. In other embodiments, the optoelectronic device may also be a photodetection device, such as an infrared detector, an ultraviolet detector, or the like. The power device and the radio frequency device can be transistors, and particularly can be field effect transistors.
The embodiment of the application also provides electronic equipment which comprises the semiconductor device.
The electronic device may be various consumer electronic products, such as a mobile phone, a tablet computer, a notebook computer, a mobile power supply, a portable device, other wearable or mobile electronic devices, a television, a video disc player, a video recorder, a video camera, a radio recorder, a combination sound, a record player, a laser record player, a home office device, a home electronic health care device, a vehicle such as an automobile, or an energy storage device.
It should be understood that the first, second, and various numerical numbers referred to herein are merely descriptive convenience and are not intended to limit the scope of the application.
In the present application, "and/or" describing the association relationship of the association object means that there may be three relationships, for example, a and/or B may mean: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, "at least one (individual) of a, b, or c," or "at least one (individual) of a, b, and c," may each represent: a, b, c, a-b (i.e., a and b), a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple, respectively.
It should be understood that, in various embodiments of the present application, the sequence number of each process described above does not mean that the execution sequence of some or all of the steps may be executed in parallel or executed sequentially, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Claims (19)
1. A semiconductor structure, comprising:
The semiconductor device comprises a first substrate and a plurality of first metal bonding layers, wherein the plurality of first metal bonding layers are arranged on one side of the first substrate at intervals, and a first insulating bonding layer is arranged between two adjacent first metal bonding layers;
The first device functional layer and the plurality of second metal bonding layers are arranged on one side, facing the first substrate, of the first device functional layer, the plurality of first metal bonding layers are arranged in a one-to-one opposite mode, and a second insulating bonding layer is arranged between two adjacent second metal bonding layers; a conductive layer is further arranged between each first metal bonding layer and the second metal bonding layer opposite to the first metal bonding layer, an auxiliary bonding layer is arranged between the adjacent conductive layers, and the auxiliary bonding layers are made of insulating compounds; the conductive layer contains the same element as the normal valence element in the auxiliary bonding layer, and the reducibility of the material of the first metal bonding layer and/or the second metal bonding layer close to the conductive layer is higher than that of the material of the conductive layer.
2. The semiconductor structure of claim 1, wherein a surface of the conductive layer in contact with the first metal bonding layer or with the second metal bonding layer is planar and free of breakage.
3. The semiconductor structure of claim 1 or 2, wherein an interface of the first metal bonding layer and/or the second metal bonding layer near the conductive layer contains the same element as the negative valence element in the auxiliary bonding layer.
4. The semiconductor structure of any of claims 1-3, wherein the auxiliary bonding layer comprises one or more of a metal oxide, a metal nitride, a doped silicon oxide, a doped silicon nitride, a doped silicon oxynitride;
The material of the conductive layer comprises a simple substance of silicon containing doping elements or a simple substance corresponding to the metal elements in the metal oxide or the metal nitride.
5. The semiconductor structure of claim 4, wherein the metal element in the metal oxide and the metal nitride comprises one or more of aluminum, tantalum, hafnium, zirconium.
6. The semiconductor structure of any of claims 1-5, wherein the material of the first metal bonding layer or the second metal bonding layer comprises one or more of Ti, cr, ni, ta, au, in, sn, ag, al, W and its alloys, tiN, taN.
7. The semiconductor structure of any of claims 4-6, wherein the auxiliary bonding layer is an oxide or nitride of aluminum, and the material of the first or second metal bonding layer on a side near the conductive layer comprises at least one of Ti, cr, ni.
8. The semiconductor structure of any of claims 4-6, wherein the auxiliary bonding layer is an oxide or nitride of tantalum, hafnium, zirconium, and the material of the first or second metal bonding layer on a side adjacent to the conductive layer comprises at least one of Al, ti, cr, ni.
9. The semiconductor structure of any of claims 1-8, wherein the conductive layer and the auxiliary bonding layer are each one layer, and the conductive layer and the auxiliary bonding layer each have a thickness in the range of 0.5nm to 10 nm.
10. The semiconductor structure of any of claims 1-8, wherein the auxiliary bonding layer comprises a first auxiliary bonding layer and a second auxiliary bonding layer disposed in a stack, and the first auxiliary bonding layer is adjacent to the first insulating bonding layer; the conductive layer comprises a first conductive layer and a second conductive layer which are stacked, and the first conductive layer is close to the first metal bonding layer; the first conductive layer is obtained by reducing the first metal bonding layer, and the second conductive layer is obtained by reducing the second metal bonding layer, wherein the material of the first conductive layer is the same as that of the first auxiliary bonding layer.
11. A semiconductor device comprising the semiconductor structure of any of claims 1-10.
12. The semiconductor device of claim 11, wherein the semiconductor device comprises one of an optoelectronic device, a power device, and a radio frequency device.
13. An electronic device, characterized in that the electronic device comprises the semiconductor device according to claim 11 or 12.
14. A wafer bonding method, comprising the steps of:
Providing two wafers to be bonded, wherein each wafer comprises a substrate, and a device functional layer is arranged on a first side of at least one of the two substrates;
forming metal bonding layers on the two wafers respectively, wherein the metal bonding layers are arranged on the first side of the substrate;
Forming an original auxiliary bonding layer covering the metal bonding layer on at least one of the two wafers with the metal bonding layer to obtain two processed wafers; wherein the original auxiliary bonding layer is an insulating compound;
and attaching the two wafers after the treatment so that the metal bonding layers on the two wafers are oppositely arranged, and performing heat treatment on the two wafers after the attachment so that the original auxiliary bonding layers clamped between the metal bonding layers correspondingly arranged in the two wafers are reduced to be conductive layers.
15. The wafer bonding method according to claim 14, wherein after the bonding, a material on a side of the metal bonding layer, which contacts the original auxiliary bonding layer, has a higher reducibility than a simple substance corresponding to a normal valence element in the original auxiliary bonding layer.
16. The wafer bonding method of claim 14 or 15, wherein the original auxiliary bonding layer comprises one of a metal oxide, a metal nitride, a doped silicon oxide, a doped silicon nitride, a doped silicon oxynitride.
17. The wafer bonding method according to any one of claims 14 to 16, wherein a thickness of the original auxiliary bonding layer is in a range of 0.5nm to 10 nm.
18. The wafer bonding method according to any one of claims 14 to 17, wherein the temperature of the heat treatment is 100 to 200 ℃.
19. The wafer bonding method of any of claims 14-18, wherein the metal bonding layer is formed spaced apart from a first side of the substrate;
The wafer bonding method further includes, prior to forming the original auxiliary bonding layer:
Insulating bonding layers are respectively formed between the adjacent metal bonding layers on the two wafers; the insulating bonding layer is arranged on the substrate, the metal bonding layer is arranged on the substrate, the insulating bonding layer is arranged on the substrate, one side surface of the insulating bonding layer facing away from the substrate is flush with one side surface of the metal bonding layer facing away from the substrate, and the original auxiliary bonding layer also covers the insulating bonding layer.
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| CN202211474673.1A CN118073307A (en) | 2022-11-23 | 2022-11-23 | Semiconductor structure, semiconductor device, electronic apparatus, and wafer bonding method |
| PCT/CN2023/127641 WO2024109459A1 (en) | 2022-11-23 | 2023-10-30 | Semiconductor structure, semiconductor device, electronic device, and wafer bonding method |
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| CN104183702A (en) * | 2013-05-23 | 2014-12-03 | 海洋王照明科技股份有限公司 | Flexible conductive graphene film and manufacturing method and application thereof |
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